xref: /openbmc/linux/arch/arm/mach-pxa/pxa3xx.c (revision 5d284e35) 
1 /*
2  * linux/arch/arm/mach-pxa/pxa3xx.c
3  *
4  * code specific to pxa3xx aka Monahans
5  *
6  * Copyright (C) 2006 Marvell International Ltd.
7  *
8  * 2007-09-02: eric miao <eric.miao@marvell.com>
9  *             initial version
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15 
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/pm.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/i2c/pxa-i2c.h>
25 
26 #include <asm/mach/map.h>
27 #include <mach/hardware.h>
28 #include <mach/gpio.h>
29 #include <mach/pxa3xx-regs.h>
30 #include <mach/reset.h>
31 #include <mach/ohci.h>
32 #include <mach/pm.h>
33 #include <mach/dma.h>
34 #include <mach/smemc.h>
35 
36 #include "generic.h"
37 #include "devices.h"
38 #include "clock.h"
39 
40 #define PECR_IE(n)	((1 << ((n) * 2)) << 28)
41 #define PECR_IS(n)	((1 << ((n) * 2)) << 29)
42 
43 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
44 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
45 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
46 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
47 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
48 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
49 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
50 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
51 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
52 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
53 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
54 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
55 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
56 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
57 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
58 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
59 
60 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
61 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
62 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
63 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
64 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
65 
66 static struct clk_lookup pxa3xx_clkregs[] = {
67 	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
68 	/* Power I2C clock is always on */
69 	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
70 	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
71 	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
72 	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
73 	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
74 	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
75 	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
76 	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
77 	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
78 	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
79 	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
80 	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
81 	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
82 	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
83 	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
84 	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
85 	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
86 	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
87 	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
88 	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
89 	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
90 	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
91 };
92 
93 #ifdef CONFIG_PM
94 
95 #define ISRAM_START	0x5c000000
96 #define ISRAM_SIZE	SZ_256K
97 
98 static void __iomem *sram;
99 static unsigned long wakeup_src;
100 
101 /*
102  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
103  * memory controller has to be reinitialised, so we place some code
104  * in the SRAM to perform this function.
105  *
106  * We disable FIQs across the standby - otherwise, we might receive a
107  * FIQ while the SDRAM is unavailable.
108  */
109 static void pxa3xx_cpu_standby(unsigned int pwrmode)
110 {
111 	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
112 	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
113 
114 	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
115 		    pm_enter_standby_end - pm_enter_standby_start);
116 
117 	AD2D0SR = ~0;
118 	AD2D1SR = ~0;
119 	AD2D0ER = wakeup_src;
120 	AD2D1ER = 0;
121 	ASCR = ASCR;
122 	ARSR = ARSR;
123 
124 	local_fiq_disable();
125 	fn(pwrmode);
126 	local_fiq_enable();
127 
128 	AD2D0ER = 0;
129 	AD2D1ER = 0;
130 }
131 
132 /*
133  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
134  * PXA3xx development kits assumes that the resuming process continues
135  * with the address stored within the first 4 bytes of SDRAM. The PSPR
136  * register is used privately by BootROM and OBM, and _must_ be set to
137  * 0x5c014000 for the moment.
138  */
139 static void pxa3xx_cpu_pm_suspend(void)
140 {
141 	volatile unsigned long *p = (volatile void *)0xc0000000;
142 	unsigned long saved_data = *p;
143 
144 	extern void pxa3xx_cpu_suspend(long);
145 
146 	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
147 	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
148 	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
149 
150 	/* clear and setup wakeup source */
151 	AD3SR = ~0;
152 	AD3ER = wakeup_src;
153 	ASCR = ASCR;
154 	ARSR = ARSR;
155 
156 	PCFR |= (1u << 13);			/* L1_DIS */
157 	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */
158 
159 	PSPR = 0x5c014000;
160 
161 	/* overwrite with the resume address */
162 	*p = virt_to_phys(cpu_resume);
163 
164 	pxa3xx_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET);
165 
166 	*p = saved_data;
167 
168 	AD3ER = 0;
169 }
170 
171 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
172 {
173 	/*
174 	 * Don't sleep if no wakeup sources are defined
175 	 */
176 	if (wakeup_src == 0) {
177 		printk(KERN_ERR "Not suspending: no wakeup sources\n");
178 		return;
179 	}
180 
181 	switch (state) {
182 	case PM_SUSPEND_STANDBY:
183 		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
184 		break;
185 
186 	case PM_SUSPEND_MEM:
187 		pxa3xx_cpu_pm_suspend();
188 		break;
189 	}
190 }
191 
192 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
193 {
194 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
195 }
196 
197 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
198 	.valid		= pxa3xx_cpu_pm_valid,
199 	.enter		= pxa3xx_cpu_pm_enter,
200 };
201 
202 static void __init pxa3xx_init_pm(void)
203 {
204 	sram = ioremap(ISRAM_START, ISRAM_SIZE);
205 	if (!sram) {
206 		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
207 		return;
208 	}
209 
210 	/*
211 	 * Since we copy wakeup code into the SRAM, we need to ensure
212 	 * that it is preserved over the low power modes.  Note: bit 8
213 	 * is undocumented in the developer manual, but must be set.
214 	 */
215 	AD1R |= ADXR_L2 | ADXR_R0;
216 	AD2R |= ADXR_L2 | ADXR_R0;
217 	AD3R |= ADXR_L2 | ADXR_R0;
218 
219 	/*
220 	 * Clear the resume enable registers.
221 	 */
222 	AD1D0ER = 0;
223 	AD2D0ER = 0;
224 	AD2D1ER = 0;
225 	AD3ER = 0;
226 
227 	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
228 }
229 
230 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
231 {
232 	unsigned long flags, mask = 0;
233 
234 	switch (d->irq) {
235 	case IRQ_SSP3:
236 		mask = ADXER_MFP_WSSP3;
237 		break;
238 	case IRQ_MSL:
239 		mask = ADXER_WMSL0;
240 		break;
241 	case IRQ_USBH2:
242 	case IRQ_USBH1:
243 		mask = ADXER_WUSBH;
244 		break;
245 	case IRQ_KEYPAD:
246 		mask = ADXER_WKP;
247 		break;
248 	case IRQ_AC97:
249 		mask = ADXER_MFP_WAC97;
250 		break;
251 	case IRQ_USIM:
252 		mask = ADXER_WUSIM0;
253 		break;
254 	case IRQ_SSP2:
255 		mask = ADXER_MFP_WSSP2;
256 		break;
257 	case IRQ_I2C:
258 		mask = ADXER_MFP_WI2C;
259 		break;
260 	case IRQ_STUART:
261 		mask = ADXER_MFP_WUART3;
262 		break;
263 	case IRQ_BTUART:
264 		mask = ADXER_MFP_WUART2;
265 		break;
266 	case IRQ_FFUART:
267 		mask = ADXER_MFP_WUART1;
268 		break;
269 	case IRQ_MMC:
270 		mask = ADXER_MFP_WMMC1;
271 		break;
272 	case IRQ_SSP:
273 		mask = ADXER_MFP_WSSP1;
274 		break;
275 	case IRQ_RTCAlrm:
276 		mask = ADXER_WRTC;
277 		break;
278 	case IRQ_SSP4:
279 		mask = ADXER_MFP_WSSP4;
280 		break;
281 	case IRQ_TSI:
282 		mask = ADXER_WTSI;
283 		break;
284 	case IRQ_USIM2:
285 		mask = ADXER_WUSIM1;
286 		break;
287 	case IRQ_MMC2:
288 		mask = ADXER_MFP_WMMC2;
289 		break;
290 	case IRQ_NAND:
291 		mask = ADXER_MFP_WFLASH;
292 		break;
293 	case IRQ_USB2:
294 		mask = ADXER_WUSB2;
295 		break;
296 	case IRQ_WAKEUP0:
297 		mask = ADXER_WEXTWAKE0;
298 		break;
299 	case IRQ_WAKEUP1:
300 		mask = ADXER_WEXTWAKE1;
301 		break;
302 	case IRQ_MMC3:
303 		mask = ADXER_MFP_GEN12;
304 		break;
305 	default:
306 		return -EINVAL;
307 	}
308 
309 	local_irq_save(flags);
310 	if (on)
311 		wakeup_src |= mask;
312 	else
313 		wakeup_src &= ~mask;
314 	local_irq_restore(flags);
315 
316 	return 0;
317 }
318 #else
319 static inline void pxa3xx_init_pm(void) {}
320 #define pxa3xx_set_wake	NULL
321 #endif
322 
323 static void pxa_ack_ext_wakeup(struct irq_data *d)
324 {
325 	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
326 }
327 
328 static void pxa_mask_ext_wakeup(struct irq_data *d)
329 {
330 	pxa_mask_irq(d);
331 	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
332 }
333 
334 static void pxa_unmask_ext_wakeup(struct irq_data *d)
335 {
336 	pxa_unmask_irq(d);
337 	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
338 }
339 
340 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
341 {
342 	if (flow_type & IRQ_TYPE_EDGE_RISING)
343 		PWER |= 1 << (d->irq - IRQ_WAKEUP0);
344 
345 	if (flow_type & IRQ_TYPE_EDGE_FALLING)
346 		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
347 
348 	return 0;
349 }
350 
351 static struct irq_chip pxa_ext_wakeup_chip = {
352 	.name		= "WAKEUP",
353 	.irq_ack	= pxa_ack_ext_wakeup,
354 	.irq_mask	= pxa_mask_ext_wakeup,
355 	.irq_unmask	= pxa_unmask_ext_wakeup,
356 	.irq_set_type	= pxa_set_ext_wakeup_type,
357 };
358 
359 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
360 {
361 	int irq;
362 
363 	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
364 		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
365 					 handle_edge_irq);
366 		set_irq_flags(irq, IRQF_VALID);
367 	}
368 
369 	pxa_ext_wakeup_chip.irq_set_wake = fn;
370 }
371 
372 void __init pxa3xx_init_irq(void)
373 {
374 	/* enable CP6 access */
375 	u32 value;
376 	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
377 	value |= (1 << 6);
378 	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
379 
380 	pxa_init_irq(56, pxa3xx_set_wake);
381 	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
382 	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
383 }
384 
385 static struct map_desc pxa3xx_io_desc[] __initdata = {
386 	{	/* Mem Ctl */
387 		.virtual	= SMEMC_VIRT,
388 		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
389 		.length		= 0x00200000,
390 		.type		= MT_DEVICE
391 	}
392 };
393 
394 void __init pxa3xx_map_io(void)
395 {
396 	pxa_map_io();
397 	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
398 	pxa3xx_get_clk_frequency_khz(1);
399 }
400 
401 /*
402  * device registration specific to PXA3xx.
403  */
404 
405 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
406 {
407 	pxa_register_device(&pxa3xx_device_i2c_power, info);
408 }
409 
410 static struct platform_device *devices[] __initdata = {
411 	&pxa27x_device_udc,
412 	&pxa_device_pmu,
413 	&pxa_device_i2s,
414 	&pxa_device_asoc_ssp1,
415 	&pxa_device_asoc_ssp2,
416 	&pxa_device_asoc_ssp3,
417 	&pxa_device_asoc_ssp4,
418 	&pxa_device_asoc_platform,
419 	&sa1100_device_rtc,
420 	&pxa_device_rtc,
421 	&pxa27x_device_ssp1,
422 	&pxa27x_device_ssp2,
423 	&pxa27x_device_ssp3,
424 	&pxa3xx_device_ssp4,
425 	&pxa27x_device_pwm0,
426 	&pxa27x_device_pwm1,
427 };
428 
429 static int __init pxa3xx_init(void)
430 {
431 	int ret = 0;
432 
433 	if (cpu_is_pxa3xx()) {
434 
435 		reset_status = ARSR;
436 
437 		/*
438 		 * clear RDH bit every time after reset
439 		 *
440 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
441 		 * preserve them here in case they will be referenced later
442 		 */
443 		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
444 
445 		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
446 
447 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
448 			return ret;
449 
450 		pxa3xx_init_pm();
451 
452 		register_syscore_ops(&pxa_irq_syscore_ops);
453 		register_syscore_ops(&pxa3xx_mfp_syscore_ops);
454 		register_syscore_ops(&pxa_gpio_syscore_ops);
455 		register_syscore_ops(&pxa3xx_clock_syscore_ops);
456 
457 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
458 	}
459 
460 	return ret;
461 }
462 
463 postcore_initcall(pxa3xx_init);
464