1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/pm.h> 19 #include <linux/platform_device.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/syscore_ops.h> 23 #include <linux/i2c/pxa-i2c.h> 24 25 #include <asm/mach/map.h> 26 #include <asm/suspend.h> 27 #include <mach/hardware.h> 28 #include <mach/gpio-pxa.h> 29 #include <mach/pxa3xx-regs.h> 30 #include <mach/reset.h> 31 #include <mach/ohci.h> 32 #include <mach/pm.h> 33 #include <mach/dma.h> 34 #include <mach/smemc.h> 35 36 #include "generic.h" 37 #include "devices.h" 38 #include "clock.h" 39 40 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 41 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 42 43 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 44 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 45 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 46 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 47 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 48 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 49 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 50 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 51 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 52 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 53 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 54 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 55 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 56 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 57 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 58 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 59 60 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 61 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); 62 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 63 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 64 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); 65 66 static struct clk_lookup pxa3xx_clkregs[] = { 67 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 68 /* Power I2C clock is always on */ 69 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 70 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 71 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 72 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 73 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 74 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 75 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 76 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 77 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 78 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 79 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 80 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 81 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 82 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 83 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 84 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 85 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 86 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 87 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 88 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 89 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 90 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), 91 }; 92 93 #ifdef CONFIG_PM 94 95 #define ISRAM_START 0x5c000000 96 #define ISRAM_SIZE SZ_256K 97 98 static void __iomem *sram; 99 static unsigned long wakeup_src; 100 101 /* 102 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 103 * memory controller has to be reinitialised, so we place some code 104 * in the SRAM to perform this function. 105 * 106 * We disable FIQs across the standby - otherwise, we might receive a 107 * FIQ while the SDRAM is unavailable. 108 */ 109 static void pxa3xx_cpu_standby(unsigned int pwrmode) 110 { 111 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 112 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 113 114 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 115 pm_enter_standby_end - pm_enter_standby_start); 116 117 AD2D0SR = ~0; 118 AD2D1SR = ~0; 119 AD2D0ER = wakeup_src; 120 AD2D1ER = 0; 121 ASCR = ASCR; 122 ARSR = ARSR; 123 124 local_fiq_disable(); 125 fn(pwrmode); 126 local_fiq_enable(); 127 128 AD2D0ER = 0; 129 AD2D1ER = 0; 130 } 131 132 /* 133 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 134 * PXA3xx development kits assumes that the resuming process continues 135 * with the address stored within the first 4 bytes of SDRAM. The PSPR 136 * register is used privately by BootROM and OBM, and _must_ be set to 137 * 0x5c014000 for the moment. 138 */ 139 static void pxa3xx_cpu_pm_suspend(void) 140 { 141 volatile unsigned long *p = (volatile void *)0xc0000000; 142 unsigned long saved_data = *p; 143 #ifndef CONFIG_IWMMXT 144 u64 acc0; 145 146 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); 147 #endif 148 149 extern int pxa3xx_finish_suspend(unsigned long); 150 151 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 152 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 153 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 154 155 /* clear and setup wakeup source */ 156 AD3SR = ~0; 157 AD3ER = wakeup_src; 158 ASCR = ASCR; 159 ARSR = ARSR; 160 161 PCFR |= (1u << 13); /* L1_DIS */ 162 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 163 164 PSPR = 0x5c014000; 165 166 /* overwrite with the resume address */ 167 *p = virt_to_phys(cpu_resume); 168 169 cpu_suspend(0, pxa3xx_finish_suspend); 170 171 *p = saved_data; 172 173 AD3ER = 0; 174 175 #ifndef CONFIG_IWMMXT 176 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); 177 #endif 178 } 179 180 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 181 { 182 /* 183 * Don't sleep if no wakeup sources are defined 184 */ 185 if (wakeup_src == 0) { 186 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 187 return; 188 } 189 190 switch (state) { 191 case PM_SUSPEND_STANDBY: 192 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 193 break; 194 195 case PM_SUSPEND_MEM: 196 pxa3xx_cpu_pm_suspend(); 197 break; 198 } 199 } 200 201 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 202 { 203 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 204 } 205 206 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 207 .valid = pxa3xx_cpu_pm_valid, 208 .enter = pxa3xx_cpu_pm_enter, 209 }; 210 211 static void __init pxa3xx_init_pm(void) 212 { 213 sram = ioremap(ISRAM_START, ISRAM_SIZE); 214 if (!sram) { 215 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 216 return; 217 } 218 219 /* 220 * Since we copy wakeup code into the SRAM, we need to ensure 221 * that it is preserved over the low power modes. Note: bit 8 222 * is undocumented in the developer manual, but must be set. 223 */ 224 AD1R |= ADXR_L2 | ADXR_R0; 225 AD2R |= ADXR_L2 | ADXR_R0; 226 AD3R |= ADXR_L2 | ADXR_R0; 227 228 /* 229 * Clear the resume enable registers. 230 */ 231 AD1D0ER = 0; 232 AD2D0ER = 0; 233 AD2D1ER = 0; 234 AD3ER = 0; 235 236 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 237 } 238 239 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 240 { 241 unsigned long flags, mask = 0; 242 243 switch (d->irq) { 244 case IRQ_SSP3: 245 mask = ADXER_MFP_WSSP3; 246 break; 247 case IRQ_MSL: 248 mask = ADXER_WMSL0; 249 break; 250 case IRQ_USBH2: 251 case IRQ_USBH1: 252 mask = ADXER_WUSBH; 253 break; 254 case IRQ_KEYPAD: 255 mask = ADXER_WKP; 256 break; 257 case IRQ_AC97: 258 mask = ADXER_MFP_WAC97; 259 break; 260 case IRQ_USIM: 261 mask = ADXER_WUSIM0; 262 break; 263 case IRQ_SSP2: 264 mask = ADXER_MFP_WSSP2; 265 break; 266 case IRQ_I2C: 267 mask = ADXER_MFP_WI2C; 268 break; 269 case IRQ_STUART: 270 mask = ADXER_MFP_WUART3; 271 break; 272 case IRQ_BTUART: 273 mask = ADXER_MFP_WUART2; 274 break; 275 case IRQ_FFUART: 276 mask = ADXER_MFP_WUART1; 277 break; 278 case IRQ_MMC: 279 mask = ADXER_MFP_WMMC1; 280 break; 281 case IRQ_SSP: 282 mask = ADXER_MFP_WSSP1; 283 break; 284 case IRQ_RTCAlrm: 285 mask = ADXER_WRTC; 286 break; 287 case IRQ_SSP4: 288 mask = ADXER_MFP_WSSP4; 289 break; 290 case IRQ_TSI: 291 mask = ADXER_WTSI; 292 break; 293 case IRQ_USIM2: 294 mask = ADXER_WUSIM1; 295 break; 296 case IRQ_MMC2: 297 mask = ADXER_MFP_WMMC2; 298 break; 299 case IRQ_NAND: 300 mask = ADXER_MFP_WFLASH; 301 break; 302 case IRQ_USB2: 303 mask = ADXER_WUSB2; 304 break; 305 case IRQ_WAKEUP0: 306 mask = ADXER_WEXTWAKE0; 307 break; 308 case IRQ_WAKEUP1: 309 mask = ADXER_WEXTWAKE1; 310 break; 311 case IRQ_MMC3: 312 mask = ADXER_MFP_GEN12; 313 break; 314 default: 315 return -EINVAL; 316 } 317 318 local_irq_save(flags); 319 if (on) 320 wakeup_src |= mask; 321 else 322 wakeup_src &= ~mask; 323 local_irq_restore(flags); 324 325 return 0; 326 } 327 #else 328 static inline void pxa3xx_init_pm(void) {} 329 #define pxa3xx_set_wake NULL 330 #endif 331 332 static void pxa_ack_ext_wakeup(struct irq_data *d) 333 { 334 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 335 } 336 337 static void pxa_mask_ext_wakeup(struct irq_data *d) 338 { 339 pxa_mask_irq(d); 340 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 341 } 342 343 static void pxa_unmask_ext_wakeup(struct irq_data *d) 344 { 345 pxa_unmask_irq(d); 346 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 347 } 348 349 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 350 { 351 if (flow_type & IRQ_TYPE_EDGE_RISING) 352 PWER |= 1 << (d->irq - IRQ_WAKEUP0); 353 354 if (flow_type & IRQ_TYPE_EDGE_FALLING) 355 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 356 357 return 0; 358 } 359 360 static struct irq_chip pxa_ext_wakeup_chip = { 361 .name = "WAKEUP", 362 .irq_ack = pxa_ack_ext_wakeup, 363 .irq_mask = pxa_mask_ext_wakeup, 364 .irq_unmask = pxa_unmask_ext_wakeup, 365 .irq_set_type = pxa_set_ext_wakeup_type, 366 }; 367 368 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 369 { 370 int irq; 371 372 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 373 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 374 handle_edge_irq); 375 set_irq_flags(irq, IRQF_VALID); 376 } 377 378 pxa_ext_wakeup_chip.irq_set_wake = fn; 379 } 380 381 void __init pxa3xx_init_irq(void) 382 { 383 /* enable CP6 access */ 384 u32 value; 385 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 386 value |= (1 << 6); 387 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 388 389 pxa_init_irq(56, pxa3xx_set_wake); 390 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 391 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 392 } 393 394 static struct map_desc pxa3xx_io_desc[] __initdata = { 395 { /* Mem Ctl */ 396 .virtual = (unsigned long)SMEMC_VIRT, 397 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 398 .length = 0x00200000, 399 .type = MT_DEVICE 400 } 401 }; 402 403 void __init pxa3xx_map_io(void) 404 { 405 pxa_map_io(); 406 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 407 pxa3xx_get_clk_frequency_khz(1); 408 } 409 410 /* 411 * device registration specific to PXA3xx. 412 */ 413 414 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 415 { 416 pxa_register_device(&pxa3xx_device_i2c_power, info); 417 } 418 419 static struct platform_device *devices[] __initdata = { 420 &pxa27x_device_udc, 421 &pxa_device_pmu, 422 &pxa_device_i2s, 423 &pxa_device_asoc_ssp1, 424 &pxa_device_asoc_ssp2, 425 &pxa_device_asoc_ssp3, 426 &pxa_device_asoc_ssp4, 427 &pxa_device_asoc_platform, 428 &sa1100_device_rtc, 429 &pxa_device_rtc, 430 &pxa27x_device_ssp1, 431 &pxa27x_device_ssp2, 432 &pxa27x_device_ssp3, 433 &pxa3xx_device_ssp4, 434 &pxa27x_device_pwm0, 435 &pxa27x_device_pwm1, 436 }; 437 438 static int __init pxa3xx_init(void) 439 { 440 int ret = 0; 441 442 if (cpu_is_pxa3xx()) { 443 444 reset_status = ARSR; 445 446 /* 447 * clear RDH bit every time after reset 448 * 449 * Note: the last 3 bits DxS are write-1-to-clear so carefully 450 * preserve them here in case they will be referenced later 451 */ 452 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 453 454 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 455 456 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 457 return ret; 458 459 pxa3xx_init_pm(); 460 461 register_syscore_ops(&pxa_irq_syscore_ops); 462 register_syscore_ops(&pxa3xx_mfp_syscore_ops); 463 register_syscore_ops(&pxa_gpio_syscore_ops); 464 register_syscore_ops(&pxa3xx_clock_syscore_ops); 465 466 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 467 } 468 469 return ret; 470 } 471 472 postcore_initcall(pxa3xx_init); 473