1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <mach/hardware.h> 26 #include <mach/gpio.h> 27 #include <mach/pxa3xx-regs.h> 28 #include <mach/reset.h> 29 #include <mach/ohci.h> 30 #include <mach/pm.h> 31 #include <mach/dma.h> 32 #include <mach/regs-intc.h> 33 #include <plat/i2c.h> 34 35 #include "generic.h" 36 #include "devices.h" 37 #include "clock.h" 38 39 /* Crystal clock: 13MHz */ 40 #define BASE_CLK 13000000 41 42 /* Ring Oscillator Clock: 60MHz */ 43 #define RO_CLK 60000000 44 45 #define ACCR_D0CS (1 << 26) 46 #define ACCR_PCCE (1 << 11) 47 48 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 49 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 50 51 /* crystal frequency to static memory controller multiplier (SMCFS) */ 52 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 53 54 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 55 static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; 56 57 /* 58 * Get the clock frequency as reflected by CCSR and the turbo flag. 59 * We assume these values have been applied via a fcs. 60 * If info is not 0 we also display the current settings. 61 */ 62 unsigned int pxa3xx_get_clk_frequency_khz(int info) 63 { 64 unsigned long acsr, xclkcfg; 65 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 66 67 /* Read XCLKCFG register turbo bit */ 68 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 69 t = xclkcfg & 0x1; 70 71 acsr = ACSR; 72 73 xl = acsr & 0x1f; 74 xn = (acsr >> 8) & 0x7; 75 hss = (acsr >> 14) & 0x3; 76 77 XL = xl * BASE_CLK; 78 XN = xn * XL; 79 80 ro = acsr & ACCR_D0CS; 81 82 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 83 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 84 85 if (info) { 86 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 87 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 88 (ro) ? "" : "in"); 89 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 90 XL / 1000000, (XL % 1000000) / 10000, xl); 91 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 92 XN / 1000000, (XN % 1000000) / 10000, xn, 93 (t) ? "" : "in"); 94 pr_info("HSIO bus clock: %d.%02dMHz\n", 95 HSS / 1000000, (HSS % 1000000) / 10000); 96 } 97 98 return CLK / 1000; 99 } 100 101 void pxa3xx_clear_reset_status(unsigned int mask) 102 { 103 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 104 ARSR = mask; 105 } 106 107 /* 108 * Return the current AC97 clock frequency. 109 */ 110 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 111 { 112 unsigned long rate = 312000000; 113 unsigned long ac97_div; 114 115 ac97_div = AC97_DIV; 116 117 /* This may loose precision for some rates but won't for the 118 * standard 24.576MHz. 119 */ 120 rate /= (ac97_div >> 12) & 0x7fff; 121 rate *= (ac97_div & 0xfff); 122 123 return rate; 124 } 125 126 /* 127 * Return the current HSIO bus clock frequency 128 */ 129 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 130 { 131 unsigned long acsr; 132 unsigned int hss, hsio_clk; 133 134 acsr = ACSR; 135 136 hss = (acsr >> 14) & 0x3; 137 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 138 139 return hsio_clk; 140 } 141 142 void clk_pxa3xx_cken_enable(struct clk *clk) 143 { 144 unsigned long mask = 1ul << (clk->cken & 0x1f); 145 146 if (clk->cken < 32) 147 CKENA |= mask; 148 else 149 CKENB |= mask; 150 } 151 152 void clk_pxa3xx_cken_disable(struct clk *clk) 153 { 154 unsigned long mask = 1ul << (clk->cken & 0x1f); 155 156 if (clk->cken < 32) 157 CKENA &= ~mask; 158 else 159 CKENB &= ~mask; 160 } 161 162 const struct clkops clk_pxa3xx_cken_ops = { 163 .enable = clk_pxa3xx_cken_enable, 164 .disable = clk_pxa3xx_cken_disable, 165 }; 166 167 static const struct clkops clk_pxa3xx_hsio_ops = { 168 .enable = clk_pxa3xx_cken_enable, 169 .disable = clk_pxa3xx_cken_disable, 170 .getrate = clk_pxa3xx_hsio_getrate, 171 }; 172 173 static const struct clkops clk_pxa3xx_ac97_ops = { 174 .enable = clk_pxa3xx_cken_enable, 175 .disable = clk_pxa3xx_cken_disable, 176 .getrate = clk_pxa3xx_ac97_getrate, 177 }; 178 179 static void clk_pout_enable(struct clk *clk) 180 { 181 OSCC |= OSCC_PEN; 182 } 183 184 static void clk_pout_disable(struct clk *clk) 185 { 186 OSCC &= ~OSCC_PEN; 187 } 188 189 static const struct clkops clk_pout_ops = { 190 .enable = clk_pout_enable, 191 .disable = clk_pout_disable, 192 }; 193 194 static void clk_dummy_enable(struct clk *clk) 195 { 196 } 197 198 static void clk_dummy_disable(struct clk *clk) 199 { 200 } 201 202 static const struct clkops clk_dummy_ops = { 203 .enable = clk_dummy_enable, 204 .disable = clk_dummy_disable, 205 }; 206 207 static struct clk clk_pxa3xx_pout = { 208 .ops = &clk_pout_ops, 209 .rate = 13000000, 210 .delay = 70, 211 }; 212 213 static struct clk clk_dummy = { 214 .ops = &clk_dummy_ops, 215 }; 216 217 static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 218 static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 219 static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 220 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 221 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 222 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 223 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 224 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 225 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 226 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 227 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 228 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 229 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 230 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 231 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 232 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 233 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 234 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 235 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 236 237 static struct clk_lookup pxa3xx_clkregs[] = { 238 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 239 /* Power I2C clock is always on */ 240 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 241 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 242 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 243 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 244 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 245 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 246 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 247 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 248 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 249 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 250 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 251 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 252 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 253 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 254 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 255 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 256 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 257 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 258 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 259 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 260 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 261 }; 262 263 #ifdef CONFIG_PM 264 265 #define ISRAM_START 0x5c000000 266 #define ISRAM_SIZE SZ_256K 267 268 static void __iomem *sram; 269 static unsigned long wakeup_src; 270 271 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 272 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 273 274 enum { SLEEP_SAVE_CKENA, 275 SLEEP_SAVE_CKENB, 276 SLEEP_SAVE_ACCR, 277 278 SLEEP_SAVE_COUNT, 279 }; 280 281 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 282 { 283 SAVE(CKENA); 284 SAVE(CKENB); 285 SAVE(ACCR); 286 } 287 288 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 289 { 290 RESTORE(ACCR); 291 RESTORE(CKENA); 292 RESTORE(CKENB); 293 } 294 295 /* 296 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 297 * memory controller has to be reinitialised, so we place some code 298 * in the SRAM to perform this function. 299 * 300 * We disable FIQs across the standby - otherwise, we might receive a 301 * FIQ while the SDRAM is unavailable. 302 */ 303 static void pxa3xx_cpu_standby(unsigned int pwrmode) 304 { 305 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 306 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 307 308 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 309 pm_enter_standby_end - pm_enter_standby_start); 310 311 AD2D0SR = ~0; 312 AD2D1SR = ~0; 313 AD2D0ER = wakeup_src; 314 AD2D1ER = 0; 315 ASCR = ASCR; 316 ARSR = ARSR; 317 318 local_fiq_disable(); 319 fn(pwrmode); 320 local_fiq_enable(); 321 322 AD2D0ER = 0; 323 AD2D1ER = 0; 324 } 325 326 /* 327 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 328 * PXA3xx development kits assumes that the resuming process continues 329 * with the address stored within the first 4 bytes of SDRAM. The PSPR 330 * register is used privately by BootROM and OBM, and _must_ be set to 331 * 0x5c014000 for the moment. 332 */ 333 static void pxa3xx_cpu_pm_suspend(void) 334 { 335 volatile unsigned long *p = (volatile void *)0xc0000000; 336 unsigned long saved_data = *p; 337 338 extern void pxa3xx_cpu_suspend(void); 339 extern void pxa3xx_cpu_resume(void); 340 341 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 342 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 343 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 344 345 /* clear and setup wakeup source */ 346 AD3SR = ~0; 347 AD3ER = wakeup_src; 348 ASCR = ASCR; 349 ARSR = ARSR; 350 351 PCFR |= (1u << 13); /* L1_DIS */ 352 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 353 354 PSPR = 0x5c014000; 355 356 /* overwrite with the resume address */ 357 *p = virt_to_phys(pxa3xx_cpu_resume); 358 359 pxa3xx_cpu_suspend(); 360 361 *p = saved_data; 362 363 AD3ER = 0; 364 } 365 366 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 367 { 368 /* 369 * Don't sleep if no wakeup sources are defined 370 */ 371 if (wakeup_src == 0) { 372 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 373 return; 374 } 375 376 switch (state) { 377 case PM_SUSPEND_STANDBY: 378 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 379 break; 380 381 case PM_SUSPEND_MEM: 382 pxa3xx_cpu_pm_suspend(); 383 break; 384 } 385 } 386 387 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 388 { 389 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 390 } 391 392 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 393 .save_count = SLEEP_SAVE_COUNT, 394 .save = pxa3xx_cpu_pm_save, 395 .restore = pxa3xx_cpu_pm_restore, 396 .valid = pxa3xx_cpu_pm_valid, 397 .enter = pxa3xx_cpu_pm_enter, 398 }; 399 400 static void __init pxa3xx_init_pm(void) 401 { 402 sram = ioremap(ISRAM_START, ISRAM_SIZE); 403 if (!sram) { 404 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 405 return; 406 } 407 408 /* 409 * Since we copy wakeup code into the SRAM, we need to ensure 410 * that it is preserved over the low power modes. Note: bit 8 411 * is undocumented in the developer manual, but must be set. 412 */ 413 AD1R |= ADXR_L2 | ADXR_R0; 414 AD2R |= ADXR_L2 | ADXR_R0; 415 AD3R |= ADXR_L2 | ADXR_R0; 416 417 /* 418 * Clear the resume enable registers. 419 */ 420 AD1D0ER = 0; 421 AD2D0ER = 0; 422 AD2D1ER = 0; 423 AD3ER = 0; 424 425 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 426 } 427 428 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 429 { 430 unsigned long flags, mask = 0; 431 432 switch (irq) { 433 case IRQ_SSP3: 434 mask = ADXER_MFP_WSSP3; 435 break; 436 case IRQ_MSL: 437 mask = ADXER_WMSL0; 438 break; 439 case IRQ_USBH2: 440 case IRQ_USBH1: 441 mask = ADXER_WUSBH; 442 break; 443 case IRQ_KEYPAD: 444 mask = ADXER_WKP; 445 break; 446 case IRQ_AC97: 447 mask = ADXER_MFP_WAC97; 448 break; 449 case IRQ_USIM: 450 mask = ADXER_WUSIM0; 451 break; 452 case IRQ_SSP2: 453 mask = ADXER_MFP_WSSP2; 454 break; 455 case IRQ_I2C: 456 mask = ADXER_MFP_WI2C; 457 break; 458 case IRQ_STUART: 459 mask = ADXER_MFP_WUART3; 460 break; 461 case IRQ_BTUART: 462 mask = ADXER_MFP_WUART2; 463 break; 464 case IRQ_FFUART: 465 mask = ADXER_MFP_WUART1; 466 break; 467 case IRQ_MMC: 468 mask = ADXER_MFP_WMMC1; 469 break; 470 case IRQ_SSP: 471 mask = ADXER_MFP_WSSP1; 472 break; 473 case IRQ_RTCAlrm: 474 mask = ADXER_WRTC; 475 break; 476 case IRQ_SSP4: 477 mask = ADXER_MFP_WSSP4; 478 break; 479 case IRQ_TSI: 480 mask = ADXER_WTSI; 481 break; 482 case IRQ_USIM2: 483 mask = ADXER_WUSIM1; 484 break; 485 case IRQ_MMC2: 486 mask = ADXER_MFP_WMMC2; 487 break; 488 case IRQ_NAND: 489 mask = ADXER_MFP_WFLASH; 490 break; 491 case IRQ_USB2: 492 mask = ADXER_WUSB2; 493 break; 494 case IRQ_WAKEUP0: 495 mask = ADXER_WEXTWAKE0; 496 break; 497 case IRQ_WAKEUP1: 498 mask = ADXER_WEXTWAKE1; 499 break; 500 case IRQ_MMC3: 501 mask = ADXER_MFP_GEN12; 502 break; 503 default: 504 return -EINVAL; 505 } 506 507 local_irq_save(flags); 508 if (on) 509 wakeup_src |= mask; 510 else 511 wakeup_src &= ~mask; 512 local_irq_restore(flags); 513 514 return 0; 515 } 516 #else 517 static inline void pxa3xx_init_pm(void) {} 518 #define pxa3xx_set_wake NULL 519 #endif 520 521 static void pxa_ack_ext_wakeup(unsigned int irq) 522 { 523 PECR |= PECR_IS(irq - IRQ_WAKEUP0); 524 } 525 526 static void pxa_mask_ext_wakeup(unsigned int irq) 527 { 528 ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); 529 PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); 530 } 531 532 static void pxa_unmask_ext_wakeup(unsigned int irq) 533 { 534 ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); 535 PECR |= PECR_IE(irq - IRQ_WAKEUP0); 536 } 537 538 static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type) 539 { 540 if (flow_type & IRQ_TYPE_EDGE_RISING) 541 PWER |= 1 << (irq - IRQ_WAKEUP0); 542 543 if (flow_type & IRQ_TYPE_EDGE_FALLING) 544 PWER |= 1 << (irq - IRQ_WAKEUP0 + 2); 545 546 return 0; 547 } 548 549 static struct irq_chip pxa_ext_wakeup_chip = { 550 .name = "WAKEUP", 551 .ack = pxa_ack_ext_wakeup, 552 .mask = pxa_mask_ext_wakeup, 553 .unmask = pxa_unmask_ext_wakeup, 554 .set_type = pxa_set_ext_wakeup_type, 555 }; 556 557 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 558 { 559 int irq; 560 561 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 562 set_irq_chip(irq, &pxa_ext_wakeup_chip); 563 set_irq_handler(irq, handle_edge_irq); 564 set_irq_flags(irq, IRQF_VALID); 565 } 566 567 pxa_ext_wakeup_chip.set_wake = fn; 568 } 569 570 void __init pxa3xx_init_irq(void) 571 { 572 /* enable CP6 access */ 573 u32 value; 574 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 575 value |= (1 << 6); 576 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 577 578 pxa_init_irq(56, pxa3xx_set_wake); 579 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 580 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 581 } 582 583 /* 584 * device registration specific to PXA3xx. 585 */ 586 587 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 588 { 589 pxa_register_device(&pxa3xx_device_i2c_power, info); 590 } 591 592 static struct platform_device *devices[] __initdata = { 593 &pxa27x_device_udc, 594 &pxa_device_pmu, 595 &pxa_device_i2s, 596 &pxa_device_asoc_ssp1, 597 &pxa_device_asoc_ssp2, 598 &pxa_device_asoc_ssp3, 599 &pxa_device_asoc_ssp4, 600 &pxa_device_asoc_platform, 601 &sa1100_device_rtc, 602 &pxa_device_rtc, 603 &pxa27x_device_ssp1, 604 &pxa27x_device_ssp2, 605 &pxa27x_device_ssp3, 606 &pxa3xx_device_ssp4, 607 &pxa27x_device_pwm0, 608 &pxa27x_device_pwm1, 609 }; 610 611 static struct sys_device pxa3xx_sysdev[] = { 612 { 613 .cls = &pxa_irq_sysclass, 614 }, { 615 .cls = &pxa3xx_mfp_sysclass, 616 }, { 617 .cls = &pxa_gpio_sysclass, 618 }, 619 }; 620 621 static int __init pxa3xx_init(void) 622 { 623 int i, ret = 0; 624 625 if (cpu_is_pxa3xx()) { 626 627 reset_status = ARSR; 628 629 /* 630 * clear RDH bit every time after reset 631 * 632 * Note: the last 3 bits DxS are write-1-to-clear so carefully 633 * preserve them here in case they will be referenced later 634 */ 635 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 636 637 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 638 639 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 640 return ret; 641 642 pxa3xx_init_pm(); 643 644 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 645 ret = sysdev_register(&pxa3xx_sysdev[i]); 646 if (ret) 647 pr_err("failed to register sysdev[%d]\n", i); 648 } 649 650 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 651 } 652 653 return ret; 654 } 655 656 postcore_initcall(pxa3xx_init); 657