1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/mach/map.h> 26 #include <mach/hardware.h> 27 #include <mach/gpio.h> 28 #include <mach/pxa3xx-regs.h> 29 #include <mach/reset.h> 30 #include <mach/ohci.h> 31 #include <mach/pm.h> 32 #include <mach/dma.h> 33 #include <mach/regs-intc.h> 34 #include <mach/smemc.h> 35 #include <plat/i2c.h> 36 37 #include "generic.h" 38 #include "devices.h" 39 #include "clock.h" 40 41 /* Crystal clock: 13MHz */ 42 #define BASE_CLK 13000000 43 44 /* Ring Oscillator Clock: 60MHz */ 45 #define RO_CLK 60000000 46 47 #define ACCR_D0CS (1 << 26) 48 #define ACCR_PCCE (1 << 11) 49 50 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 51 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 52 53 /* crystal frequency to static memory controller multiplier (SMCFS) */ 54 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 55 56 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 57 static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; 58 59 /* 60 * Get the clock frequency as reflected by CCSR and the turbo flag. 61 * We assume these values have been applied via a fcs. 62 * If info is not 0 we also display the current settings. 63 */ 64 unsigned int pxa3xx_get_clk_frequency_khz(int info) 65 { 66 unsigned long acsr, xclkcfg; 67 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 68 69 /* Read XCLKCFG register turbo bit */ 70 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 71 t = xclkcfg & 0x1; 72 73 acsr = ACSR; 74 75 xl = acsr & 0x1f; 76 xn = (acsr >> 8) & 0x7; 77 hss = (acsr >> 14) & 0x3; 78 79 XL = xl * BASE_CLK; 80 XN = xn * XL; 81 82 ro = acsr & ACCR_D0CS; 83 84 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 85 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 86 87 if (info) { 88 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 89 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 90 (ro) ? "" : "in"); 91 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 92 XL / 1000000, (XL % 1000000) / 10000, xl); 93 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 94 XN / 1000000, (XN % 1000000) / 10000, xn, 95 (t) ? "" : "in"); 96 pr_info("HSIO bus clock: %d.%02dMHz\n", 97 HSS / 1000000, (HSS % 1000000) / 10000); 98 } 99 100 return CLK / 1000; 101 } 102 103 void pxa3xx_clear_reset_status(unsigned int mask) 104 { 105 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 106 ARSR = mask; 107 } 108 109 /* 110 * Return the current AC97 clock frequency. 111 */ 112 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 113 { 114 unsigned long rate = 312000000; 115 unsigned long ac97_div; 116 117 ac97_div = AC97_DIV; 118 119 /* This may loose precision for some rates but won't for the 120 * standard 24.576MHz. 121 */ 122 rate /= (ac97_div >> 12) & 0x7fff; 123 rate *= (ac97_div & 0xfff); 124 125 return rate; 126 } 127 128 /* 129 * Return the current HSIO bus clock frequency 130 */ 131 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 132 { 133 unsigned long acsr; 134 unsigned int hss, hsio_clk; 135 136 acsr = ACSR; 137 138 hss = (acsr >> 14) & 0x3; 139 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 140 141 return hsio_clk; 142 } 143 144 void clk_pxa3xx_cken_enable(struct clk *clk) 145 { 146 unsigned long mask = 1ul << (clk->cken & 0x1f); 147 148 if (clk->cken < 32) 149 CKENA |= mask; 150 else 151 CKENB |= mask; 152 } 153 154 void clk_pxa3xx_cken_disable(struct clk *clk) 155 { 156 unsigned long mask = 1ul << (clk->cken & 0x1f); 157 158 if (clk->cken < 32) 159 CKENA &= ~mask; 160 else 161 CKENB &= ~mask; 162 } 163 164 const struct clkops clk_pxa3xx_cken_ops = { 165 .enable = clk_pxa3xx_cken_enable, 166 .disable = clk_pxa3xx_cken_disable, 167 }; 168 169 static const struct clkops clk_pxa3xx_hsio_ops = { 170 .enable = clk_pxa3xx_cken_enable, 171 .disable = clk_pxa3xx_cken_disable, 172 .getrate = clk_pxa3xx_hsio_getrate, 173 }; 174 175 static const struct clkops clk_pxa3xx_ac97_ops = { 176 .enable = clk_pxa3xx_cken_enable, 177 .disable = clk_pxa3xx_cken_disable, 178 .getrate = clk_pxa3xx_ac97_getrate, 179 }; 180 181 static void clk_pout_enable(struct clk *clk) 182 { 183 OSCC |= OSCC_PEN; 184 } 185 186 static void clk_pout_disable(struct clk *clk) 187 { 188 OSCC &= ~OSCC_PEN; 189 } 190 191 static const struct clkops clk_pout_ops = { 192 .enable = clk_pout_enable, 193 .disable = clk_pout_disable, 194 }; 195 196 static void clk_dummy_enable(struct clk *clk) 197 { 198 } 199 200 static void clk_dummy_disable(struct clk *clk) 201 { 202 } 203 204 static const struct clkops clk_dummy_ops = { 205 .enable = clk_dummy_enable, 206 .disable = clk_dummy_disable, 207 }; 208 209 static struct clk clk_pxa3xx_pout = { 210 .ops = &clk_pout_ops, 211 .rate = 13000000, 212 .delay = 70, 213 }; 214 215 static struct clk clk_dummy = { 216 .ops = &clk_dummy_ops, 217 }; 218 219 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 220 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 221 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 222 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 223 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 224 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 225 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 226 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 227 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 228 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 229 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 230 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 231 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 232 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 233 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 234 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 235 236 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 237 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 238 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 239 240 static struct clk_lookup pxa3xx_clkregs[] = { 241 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 242 /* Power I2C clock is always on */ 243 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 244 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 245 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 246 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 247 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 248 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 249 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 250 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 251 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 252 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 253 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 254 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 255 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 256 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 257 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 258 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 259 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 260 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 261 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 262 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 263 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 264 }; 265 266 #ifdef CONFIG_PM 267 268 #define ISRAM_START 0x5c000000 269 #define ISRAM_SIZE SZ_256K 270 271 static void __iomem *sram; 272 static unsigned long wakeup_src; 273 274 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 275 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 276 277 enum { SLEEP_SAVE_CKENA, 278 SLEEP_SAVE_CKENB, 279 SLEEP_SAVE_ACCR, 280 281 SLEEP_SAVE_COUNT, 282 }; 283 284 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 285 { 286 SAVE(CKENA); 287 SAVE(CKENB); 288 SAVE(ACCR); 289 } 290 291 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 292 { 293 RESTORE(ACCR); 294 RESTORE(CKENA); 295 RESTORE(CKENB); 296 } 297 298 /* 299 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 300 * memory controller has to be reinitialised, so we place some code 301 * in the SRAM to perform this function. 302 * 303 * We disable FIQs across the standby - otherwise, we might receive a 304 * FIQ while the SDRAM is unavailable. 305 */ 306 static void pxa3xx_cpu_standby(unsigned int pwrmode) 307 { 308 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 309 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 310 311 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 312 pm_enter_standby_end - pm_enter_standby_start); 313 314 AD2D0SR = ~0; 315 AD2D1SR = ~0; 316 AD2D0ER = wakeup_src; 317 AD2D1ER = 0; 318 ASCR = ASCR; 319 ARSR = ARSR; 320 321 local_fiq_disable(); 322 fn(pwrmode); 323 local_fiq_enable(); 324 325 AD2D0ER = 0; 326 AD2D1ER = 0; 327 } 328 329 /* 330 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 331 * PXA3xx development kits assumes that the resuming process continues 332 * with the address stored within the first 4 bytes of SDRAM. The PSPR 333 * register is used privately by BootROM and OBM, and _must_ be set to 334 * 0x5c014000 for the moment. 335 */ 336 static void pxa3xx_cpu_pm_suspend(void) 337 { 338 volatile unsigned long *p = (volatile void *)0xc0000000; 339 unsigned long saved_data = *p; 340 341 extern void pxa3xx_cpu_suspend(void); 342 extern void pxa3xx_cpu_resume(void); 343 344 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 345 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 346 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 347 348 /* clear and setup wakeup source */ 349 AD3SR = ~0; 350 AD3ER = wakeup_src; 351 ASCR = ASCR; 352 ARSR = ARSR; 353 354 PCFR |= (1u << 13); /* L1_DIS */ 355 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 356 357 PSPR = 0x5c014000; 358 359 /* overwrite with the resume address */ 360 *p = virt_to_phys(pxa3xx_cpu_resume); 361 362 pxa3xx_cpu_suspend(); 363 364 *p = saved_data; 365 366 AD3ER = 0; 367 } 368 369 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 370 { 371 /* 372 * Don't sleep if no wakeup sources are defined 373 */ 374 if (wakeup_src == 0) { 375 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 376 return; 377 } 378 379 switch (state) { 380 case PM_SUSPEND_STANDBY: 381 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 382 break; 383 384 case PM_SUSPEND_MEM: 385 pxa3xx_cpu_pm_suspend(); 386 break; 387 } 388 } 389 390 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 391 { 392 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 393 } 394 395 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 396 .save_count = SLEEP_SAVE_COUNT, 397 .save = pxa3xx_cpu_pm_save, 398 .restore = pxa3xx_cpu_pm_restore, 399 .valid = pxa3xx_cpu_pm_valid, 400 .enter = pxa3xx_cpu_pm_enter, 401 }; 402 403 static void __init pxa3xx_init_pm(void) 404 { 405 sram = ioremap(ISRAM_START, ISRAM_SIZE); 406 if (!sram) { 407 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 408 return; 409 } 410 411 /* 412 * Since we copy wakeup code into the SRAM, we need to ensure 413 * that it is preserved over the low power modes. Note: bit 8 414 * is undocumented in the developer manual, but must be set. 415 */ 416 AD1R |= ADXR_L2 | ADXR_R0; 417 AD2R |= ADXR_L2 | ADXR_R0; 418 AD3R |= ADXR_L2 | ADXR_R0; 419 420 /* 421 * Clear the resume enable registers. 422 */ 423 AD1D0ER = 0; 424 AD2D0ER = 0; 425 AD2D1ER = 0; 426 AD3ER = 0; 427 428 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 429 } 430 431 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 432 { 433 unsigned long flags, mask = 0; 434 435 switch (irq) { 436 case IRQ_SSP3: 437 mask = ADXER_MFP_WSSP3; 438 break; 439 case IRQ_MSL: 440 mask = ADXER_WMSL0; 441 break; 442 case IRQ_USBH2: 443 case IRQ_USBH1: 444 mask = ADXER_WUSBH; 445 break; 446 case IRQ_KEYPAD: 447 mask = ADXER_WKP; 448 break; 449 case IRQ_AC97: 450 mask = ADXER_MFP_WAC97; 451 break; 452 case IRQ_USIM: 453 mask = ADXER_WUSIM0; 454 break; 455 case IRQ_SSP2: 456 mask = ADXER_MFP_WSSP2; 457 break; 458 case IRQ_I2C: 459 mask = ADXER_MFP_WI2C; 460 break; 461 case IRQ_STUART: 462 mask = ADXER_MFP_WUART3; 463 break; 464 case IRQ_BTUART: 465 mask = ADXER_MFP_WUART2; 466 break; 467 case IRQ_FFUART: 468 mask = ADXER_MFP_WUART1; 469 break; 470 case IRQ_MMC: 471 mask = ADXER_MFP_WMMC1; 472 break; 473 case IRQ_SSP: 474 mask = ADXER_MFP_WSSP1; 475 break; 476 case IRQ_RTCAlrm: 477 mask = ADXER_WRTC; 478 break; 479 case IRQ_SSP4: 480 mask = ADXER_MFP_WSSP4; 481 break; 482 case IRQ_TSI: 483 mask = ADXER_WTSI; 484 break; 485 case IRQ_USIM2: 486 mask = ADXER_WUSIM1; 487 break; 488 case IRQ_MMC2: 489 mask = ADXER_MFP_WMMC2; 490 break; 491 case IRQ_NAND: 492 mask = ADXER_MFP_WFLASH; 493 break; 494 case IRQ_USB2: 495 mask = ADXER_WUSB2; 496 break; 497 case IRQ_WAKEUP0: 498 mask = ADXER_WEXTWAKE0; 499 break; 500 case IRQ_WAKEUP1: 501 mask = ADXER_WEXTWAKE1; 502 break; 503 case IRQ_MMC3: 504 mask = ADXER_MFP_GEN12; 505 break; 506 default: 507 return -EINVAL; 508 } 509 510 local_irq_save(flags); 511 if (on) 512 wakeup_src |= mask; 513 else 514 wakeup_src &= ~mask; 515 local_irq_restore(flags); 516 517 return 0; 518 } 519 #else 520 static inline void pxa3xx_init_pm(void) {} 521 #define pxa3xx_set_wake NULL 522 #endif 523 524 static void pxa_ack_ext_wakeup(unsigned int irq) 525 { 526 PECR |= PECR_IS(irq - IRQ_WAKEUP0); 527 } 528 529 static void pxa_mask_ext_wakeup(unsigned int irq) 530 { 531 ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); 532 PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); 533 } 534 535 static void pxa_unmask_ext_wakeup(unsigned int irq) 536 { 537 ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); 538 PECR |= PECR_IE(irq - IRQ_WAKEUP0); 539 } 540 541 static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type) 542 { 543 if (flow_type & IRQ_TYPE_EDGE_RISING) 544 PWER |= 1 << (irq - IRQ_WAKEUP0); 545 546 if (flow_type & IRQ_TYPE_EDGE_FALLING) 547 PWER |= 1 << (irq - IRQ_WAKEUP0 + 2); 548 549 return 0; 550 } 551 552 static struct irq_chip pxa_ext_wakeup_chip = { 553 .name = "WAKEUP", 554 .ack = pxa_ack_ext_wakeup, 555 .mask = pxa_mask_ext_wakeup, 556 .unmask = pxa_unmask_ext_wakeup, 557 .set_type = pxa_set_ext_wakeup_type, 558 }; 559 560 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 561 { 562 int irq; 563 564 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 565 set_irq_chip(irq, &pxa_ext_wakeup_chip); 566 set_irq_handler(irq, handle_edge_irq); 567 set_irq_flags(irq, IRQF_VALID); 568 } 569 570 pxa_ext_wakeup_chip.set_wake = fn; 571 } 572 573 void __init pxa3xx_init_irq(void) 574 { 575 /* enable CP6 access */ 576 u32 value; 577 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 578 value |= (1 << 6); 579 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 580 581 pxa_init_irq(56, pxa3xx_set_wake); 582 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 583 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 584 } 585 586 static struct map_desc pxa3xx_io_desc[] __initdata = { 587 { /* Mem Ctl */ 588 .virtual = SMEMC_VIRT, 589 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 590 .length = 0x00200000, 591 .type = MT_DEVICE 592 } 593 }; 594 595 void __init pxa3xx_map_io(void) 596 { 597 pxa_map_io(); 598 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 599 pxa3xx_get_clk_frequency_khz(1); 600 } 601 602 /* 603 * device registration specific to PXA3xx. 604 */ 605 606 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 607 { 608 pxa_register_device(&pxa3xx_device_i2c_power, info); 609 } 610 611 static struct platform_device *devices[] __initdata = { 612 &pxa27x_device_udc, 613 &pxa_device_pmu, 614 &pxa_device_i2s, 615 &pxa_device_asoc_ssp1, 616 &pxa_device_asoc_ssp2, 617 &pxa_device_asoc_ssp3, 618 &pxa_device_asoc_ssp4, 619 &pxa_device_asoc_platform, 620 &sa1100_device_rtc, 621 &pxa_device_rtc, 622 &pxa27x_device_ssp1, 623 &pxa27x_device_ssp2, 624 &pxa27x_device_ssp3, 625 &pxa3xx_device_ssp4, 626 &pxa27x_device_pwm0, 627 &pxa27x_device_pwm1, 628 }; 629 630 static struct sys_device pxa3xx_sysdev[] = { 631 { 632 .cls = &pxa_irq_sysclass, 633 }, { 634 .cls = &pxa3xx_mfp_sysclass, 635 }, { 636 .cls = &pxa_gpio_sysclass, 637 }, 638 }; 639 640 static int __init pxa3xx_init(void) 641 { 642 int i, ret = 0; 643 644 if (cpu_is_pxa3xx()) { 645 646 reset_status = ARSR; 647 648 /* 649 * clear RDH bit every time after reset 650 * 651 * Note: the last 3 bits DxS are write-1-to-clear so carefully 652 * preserve them here in case they will be referenced later 653 */ 654 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 655 656 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 657 658 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 659 return ret; 660 661 pxa3xx_init_pm(); 662 663 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 664 ret = sysdev_register(&pxa3xx_sysdev[i]); 665 if (ret) 666 pr_err("failed to register sysdev[%d]\n", i); 667 } 668 669 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 670 } 671 672 return ret; 673 } 674 675 postcore_initcall(pxa3xx_init); 676