1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/gpio-pxa.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/syscore_ops.h> 25 #include <linux/i2c/pxa-i2c.h> 26 27 #include <asm/mach/map.h> 28 #include <asm/suspend.h> 29 #include <mach/hardware.h> 30 #include <mach/pxa3xx-regs.h> 31 #include <mach/reset.h> 32 #include <linux/platform_data/usb-ohci-pxa27x.h> 33 #include <mach/pm.h> 34 #include <mach/dma.h> 35 #include <mach/smemc.h> 36 #include <mach/irqs.h> 37 38 #include "generic.h" 39 #include "devices.h" 40 #include "clock.h" 41 42 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 43 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 44 45 extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); 46 47 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 48 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 49 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 50 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 51 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 52 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 53 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 54 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 55 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 56 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 57 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 58 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 59 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 60 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 61 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 62 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 63 static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0); 64 65 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 66 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); 67 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 68 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 69 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); 70 71 static struct clk_lookup pxa3xx_clkregs[] = { 72 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 73 /* Power I2C clock is always on */ 74 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 75 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 76 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 77 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 78 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 79 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 80 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 81 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 82 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 83 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 84 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 85 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 86 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 87 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 88 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 89 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 90 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 91 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 92 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 93 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 94 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 95 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), 96 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL), 97 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL), 98 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), 99 }; 100 101 #ifdef CONFIG_PM 102 103 #define ISRAM_START 0x5c000000 104 #define ISRAM_SIZE SZ_256K 105 106 static void __iomem *sram; 107 static unsigned long wakeup_src; 108 109 /* 110 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 111 * memory controller has to be reinitialised, so we place some code 112 * in the SRAM to perform this function. 113 * 114 * We disable FIQs across the standby - otherwise, we might receive a 115 * FIQ while the SDRAM is unavailable. 116 */ 117 static void pxa3xx_cpu_standby(unsigned int pwrmode) 118 { 119 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 120 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 121 122 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 123 pm_enter_standby_end - pm_enter_standby_start); 124 125 AD2D0SR = ~0; 126 AD2D1SR = ~0; 127 AD2D0ER = wakeup_src; 128 AD2D1ER = 0; 129 ASCR = ASCR; 130 ARSR = ARSR; 131 132 local_fiq_disable(); 133 fn(pwrmode); 134 local_fiq_enable(); 135 136 AD2D0ER = 0; 137 AD2D1ER = 0; 138 } 139 140 /* 141 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 142 * PXA3xx development kits assumes that the resuming process continues 143 * with the address stored within the first 4 bytes of SDRAM. The PSPR 144 * register is used privately by BootROM and OBM, and _must_ be set to 145 * 0x5c014000 for the moment. 146 */ 147 static void pxa3xx_cpu_pm_suspend(void) 148 { 149 volatile unsigned long *p = (volatile void *)0xc0000000; 150 unsigned long saved_data = *p; 151 #ifndef CONFIG_IWMMXT 152 u64 acc0; 153 154 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); 155 #endif 156 157 extern int pxa3xx_finish_suspend(unsigned long); 158 159 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 160 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 161 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 162 163 /* clear and setup wakeup source */ 164 AD3SR = ~0; 165 AD3ER = wakeup_src; 166 ASCR = ASCR; 167 ARSR = ARSR; 168 169 PCFR |= (1u << 13); /* L1_DIS */ 170 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 171 172 PSPR = 0x5c014000; 173 174 /* overwrite with the resume address */ 175 *p = virt_to_phys(cpu_resume); 176 177 cpu_suspend(0, pxa3xx_finish_suspend); 178 179 *p = saved_data; 180 181 AD3ER = 0; 182 183 #ifndef CONFIG_IWMMXT 184 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); 185 #endif 186 } 187 188 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 189 { 190 /* 191 * Don't sleep if no wakeup sources are defined 192 */ 193 if (wakeup_src == 0) { 194 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 195 return; 196 } 197 198 switch (state) { 199 case PM_SUSPEND_STANDBY: 200 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 201 break; 202 203 case PM_SUSPEND_MEM: 204 pxa3xx_cpu_pm_suspend(); 205 break; 206 } 207 } 208 209 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 210 { 211 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 212 } 213 214 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 215 .valid = pxa3xx_cpu_pm_valid, 216 .enter = pxa3xx_cpu_pm_enter, 217 }; 218 219 static void __init pxa3xx_init_pm(void) 220 { 221 sram = ioremap(ISRAM_START, ISRAM_SIZE); 222 if (!sram) { 223 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 224 return; 225 } 226 227 /* 228 * Since we copy wakeup code into the SRAM, we need to ensure 229 * that it is preserved over the low power modes. Note: bit 8 230 * is undocumented in the developer manual, but must be set. 231 */ 232 AD1R |= ADXR_L2 | ADXR_R0; 233 AD2R |= ADXR_L2 | ADXR_R0; 234 AD3R |= ADXR_L2 | ADXR_R0; 235 236 /* 237 * Clear the resume enable registers. 238 */ 239 AD1D0ER = 0; 240 AD2D0ER = 0; 241 AD2D1ER = 0; 242 AD3ER = 0; 243 244 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 245 } 246 247 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 248 { 249 unsigned long flags, mask = 0; 250 251 switch (d->irq) { 252 case IRQ_SSP3: 253 mask = ADXER_MFP_WSSP3; 254 break; 255 case IRQ_MSL: 256 mask = ADXER_WMSL0; 257 break; 258 case IRQ_USBH2: 259 case IRQ_USBH1: 260 mask = ADXER_WUSBH; 261 break; 262 case IRQ_KEYPAD: 263 mask = ADXER_WKP; 264 break; 265 case IRQ_AC97: 266 mask = ADXER_MFP_WAC97; 267 break; 268 case IRQ_USIM: 269 mask = ADXER_WUSIM0; 270 break; 271 case IRQ_SSP2: 272 mask = ADXER_MFP_WSSP2; 273 break; 274 case IRQ_I2C: 275 mask = ADXER_MFP_WI2C; 276 break; 277 case IRQ_STUART: 278 mask = ADXER_MFP_WUART3; 279 break; 280 case IRQ_BTUART: 281 mask = ADXER_MFP_WUART2; 282 break; 283 case IRQ_FFUART: 284 mask = ADXER_MFP_WUART1; 285 break; 286 case IRQ_MMC: 287 mask = ADXER_MFP_WMMC1; 288 break; 289 case IRQ_SSP: 290 mask = ADXER_MFP_WSSP1; 291 break; 292 case IRQ_RTCAlrm: 293 mask = ADXER_WRTC; 294 break; 295 case IRQ_SSP4: 296 mask = ADXER_MFP_WSSP4; 297 break; 298 case IRQ_TSI: 299 mask = ADXER_WTSI; 300 break; 301 case IRQ_USIM2: 302 mask = ADXER_WUSIM1; 303 break; 304 case IRQ_MMC2: 305 mask = ADXER_MFP_WMMC2; 306 break; 307 case IRQ_NAND: 308 mask = ADXER_MFP_WFLASH; 309 break; 310 case IRQ_USB2: 311 mask = ADXER_WUSB2; 312 break; 313 case IRQ_WAKEUP0: 314 mask = ADXER_WEXTWAKE0; 315 break; 316 case IRQ_WAKEUP1: 317 mask = ADXER_WEXTWAKE1; 318 break; 319 case IRQ_MMC3: 320 mask = ADXER_MFP_GEN12; 321 break; 322 default: 323 return -EINVAL; 324 } 325 326 local_irq_save(flags); 327 if (on) 328 wakeup_src |= mask; 329 else 330 wakeup_src &= ~mask; 331 local_irq_restore(flags); 332 333 return 0; 334 } 335 #else 336 static inline void pxa3xx_init_pm(void) {} 337 #define pxa3xx_set_wake NULL 338 #endif 339 340 static void pxa_ack_ext_wakeup(struct irq_data *d) 341 { 342 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 343 } 344 345 static void pxa_mask_ext_wakeup(struct irq_data *d) 346 { 347 pxa_mask_irq(d); 348 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 349 } 350 351 static void pxa_unmask_ext_wakeup(struct irq_data *d) 352 { 353 pxa_unmask_irq(d); 354 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 355 } 356 357 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 358 { 359 if (flow_type & IRQ_TYPE_EDGE_RISING) 360 PWER |= 1 << (d->irq - IRQ_WAKEUP0); 361 362 if (flow_type & IRQ_TYPE_EDGE_FALLING) 363 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 364 365 return 0; 366 } 367 368 static struct irq_chip pxa_ext_wakeup_chip = { 369 .name = "WAKEUP", 370 .irq_ack = pxa_ack_ext_wakeup, 371 .irq_mask = pxa_mask_ext_wakeup, 372 .irq_unmask = pxa_unmask_ext_wakeup, 373 .irq_set_type = pxa_set_ext_wakeup_type, 374 }; 375 376 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, 377 unsigned int)) 378 { 379 int irq; 380 381 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 382 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 383 handle_edge_irq); 384 set_irq_flags(irq, IRQF_VALID); 385 } 386 387 pxa_ext_wakeup_chip.irq_set_wake = fn; 388 } 389 390 static void __init __pxa3xx_init_irq(void) 391 { 392 /* enable CP6 access */ 393 u32 value; 394 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 395 value |= (1 << 6); 396 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 397 398 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 399 } 400 401 void __init pxa3xx_init_irq(void) 402 { 403 __pxa3xx_init_irq(); 404 pxa_init_irq(56, pxa3xx_set_wake); 405 } 406 407 #ifdef CONFIG_OF 408 void __init pxa3xx_dt_init_irq(void) 409 { 410 __pxa3xx_init_irq(); 411 pxa_dt_irq_init(pxa3xx_set_wake); 412 } 413 #endif /* CONFIG_OF */ 414 415 static struct map_desc pxa3xx_io_desc[] __initdata = { 416 { /* Mem Ctl */ 417 .virtual = (unsigned long)SMEMC_VIRT, 418 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 419 .length = SMEMC_SIZE, 420 .type = MT_DEVICE 421 } 422 }; 423 424 void __init pxa3xx_map_io(void) 425 { 426 pxa_map_io(); 427 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 428 pxa3xx_get_clk_frequency_khz(1); 429 } 430 431 /* 432 * device registration specific to PXA3xx. 433 */ 434 435 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 436 { 437 pxa_register_device(&pxa3xx_device_i2c_power, info); 438 } 439 440 static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = { 441 .irq_base = PXA_GPIO_TO_IRQ(0), 442 }; 443 444 static struct platform_device *devices[] __initdata = { 445 &pxa27x_device_udc, 446 &pxa_device_pmu, 447 &pxa_device_i2s, 448 &pxa_device_asoc_ssp1, 449 &pxa_device_asoc_ssp2, 450 &pxa_device_asoc_ssp3, 451 &pxa_device_asoc_ssp4, 452 &pxa_device_asoc_platform, 453 &sa1100_device_rtc, 454 &pxa_device_rtc, 455 &pxa27x_device_ssp1, 456 &pxa27x_device_ssp2, 457 &pxa27x_device_ssp3, 458 &pxa3xx_device_ssp4, 459 &pxa27x_device_pwm0, 460 &pxa27x_device_pwm1, 461 }; 462 463 static int __init pxa3xx_init(void) 464 { 465 int ret = 0; 466 467 if (cpu_is_pxa3xx()) { 468 469 reset_status = ARSR; 470 471 /* 472 * clear RDH bit every time after reset 473 * 474 * Note: the last 3 bits DxS are write-1-to-clear so carefully 475 * preserve them here in case they will be referenced later 476 */ 477 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 478 479 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 480 481 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 482 return ret; 483 484 pxa3xx_init_pm(); 485 486 register_syscore_ops(&pxa_irq_syscore_ops); 487 register_syscore_ops(&pxa3xx_mfp_syscore_ops); 488 register_syscore_ops(&pxa3xx_clock_syscore_ops); 489 490 if (of_have_populated_dt()) 491 return 0; 492 493 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 494 if (ret) 495 return ret; 496 if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) { 497 platform_device_add_data(&pxa3xx_device_gpio, 498 &pxa3xx_gpio_pdata, 499 sizeof(pxa3xx_gpio_pdata)); 500 ret = platform_device_register(&pxa3xx_device_gpio); 501 } 502 } 503 504 return ret; 505 } 506 507 postcore_initcall(pxa3xx_init); 508