xref: /openbmc/linux/arch/arm/mach-pxa/pxa3xx.c (revision 22246614)
1 /*
2  * linux/arch/arm/mach-pxa/pxa3xx.c
3  *
4  * code specific to pxa3xx aka Monahans
5  *
6  * Copyright (C) 2006 Marvell International Ltd.
7  *
8  * 2007-09-02: eric miao <eric.miao@marvell.com>
9  *             initial version
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15 
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/pm.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/sysdev.h>
24 
25 #include <asm/hardware.h>
26 #include <asm/arch/pxa3xx-regs.h>
27 #include <asm/arch/ohci.h>
28 #include <asm/arch/pm.h>
29 #include <asm/arch/dma.h>
30 #include <asm/arch/ssp.h>
31 
32 #include "generic.h"
33 #include "devices.h"
34 #include "clock.h"
35 
36 /* Crystal clock: 13MHz */
37 #define BASE_CLK	13000000
38 
39 /* Ring Oscillator Clock: 60MHz */
40 #define RO_CLK		60000000
41 
42 #define ACCR_D0CS	(1 << 26)
43 #define ACCR_PCCE	(1 << 11)
44 
45 /* crystal frequency to static memory controller multiplier (SMCFS) */
46 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
47 
48 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
49 static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
50 
51 /*
52  * Get the clock frequency as reflected by CCSR and the turbo flag.
53  * We assume these values have been applied via a fcs.
54  * If info is not 0 we also display the current settings.
55  */
56 unsigned int pxa3xx_get_clk_frequency_khz(int info)
57 {
58 	unsigned long acsr, xclkcfg;
59 	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
60 
61 	/* Read XCLKCFG register turbo bit */
62 	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
63 	t = xclkcfg & 0x1;
64 
65 	acsr = ACSR;
66 
67 	xl  = acsr & 0x1f;
68 	xn  = (acsr >> 8) & 0x7;
69 	hss = (acsr >> 14) & 0x3;
70 
71 	XL = xl * BASE_CLK;
72 	XN = xn * XL;
73 
74 	ro = acsr & ACCR_D0CS;
75 
76 	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
77 	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
78 
79 	if (info) {
80 		pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
81 			RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
82 			(ro) ? "" : "in");
83 		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
84 			XL / 1000000, (XL % 1000000) / 10000, xl);
85 		pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
86 			XN / 1000000, (XN % 1000000) / 10000, xn,
87 			(t) ? "" : "in");
88 		pr_info("HSIO bus clock: %d.%02dMHz\n",
89 			HSS / 1000000, (HSS % 1000000) / 10000);
90 	}
91 
92 	return CLK / 1000;
93 }
94 
95 /*
96  * Return the current static memory controller clock frequency
97  * in units of 10kHz
98  */
99 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
100 {
101 	unsigned long acsr;
102 	unsigned int smcfs, clk = 0;
103 
104 	acsr = ACSR;
105 
106 	smcfs = (acsr >> 23) & 0x7;
107 	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
108 
109 	return (clk / 10000);
110 }
111 
112 /*
113  * Return the current AC97 clock frequency.
114  */
115 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
116 {
117 	unsigned long rate = 312000000;
118 	unsigned long ac97_div;
119 
120 	ac97_div = AC97_DIV;
121 
122 	/* This may loose precision for some rates but won't for the
123 	 * standard 24.576MHz.
124 	 */
125 	rate /= (ac97_div >> 12) & 0x7fff;
126 	rate *= (ac97_div & 0xfff);
127 
128 	return rate;
129 }
130 
131 /*
132  * Return the current HSIO bus clock frequency
133  */
134 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
135 {
136 	unsigned long acsr;
137 	unsigned int hss, hsio_clk;
138 
139 	acsr = ACSR;
140 
141 	hss = (acsr >> 14) & 0x3;
142 	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
143 
144 	return hsio_clk;
145 }
146 
147 static void clk_pxa3xx_cken_enable(struct clk *clk)
148 {
149 	unsigned long mask = 1ul << (clk->cken & 0x1f);
150 
151 	if (clk->cken < 32)
152 		CKENA |= mask;
153 	else
154 		CKENB |= mask;
155 }
156 
157 static void clk_pxa3xx_cken_disable(struct clk *clk)
158 {
159 	unsigned long mask = 1ul << (clk->cken & 0x1f);
160 
161 	if (clk->cken < 32)
162 		CKENA &= ~mask;
163 	else
164 		CKENB &= ~mask;
165 }
166 
167 static const struct clkops clk_pxa3xx_cken_ops = {
168 	.enable		= clk_pxa3xx_cken_enable,
169 	.disable	= clk_pxa3xx_cken_disable,
170 };
171 
172 static const struct clkops clk_pxa3xx_hsio_ops = {
173 	.enable		= clk_pxa3xx_cken_enable,
174 	.disable	= clk_pxa3xx_cken_disable,
175 	.getrate	= clk_pxa3xx_hsio_getrate,
176 };
177 
178 static const struct clkops clk_pxa3xx_ac97_ops = {
179 	.enable		= clk_pxa3xx_cken_enable,
180 	.disable	= clk_pxa3xx_cken_disable,
181 	.getrate	= clk_pxa3xx_ac97_getrate,
182 };
183 
184 static void clk_pout_enable(struct clk *clk)
185 {
186 	OSCC |= OSCC_PEN;
187 }
188 
189 static void clk_pout_disable(struct clk *clk)
190 {
191 	OSCC &= ~OSCC_PEN;
192 }
193 
194 static const struct clkops clk_pout_ops = {
195 	.enable		= clk_pout_enable,
196 	.disable	= clk_pout_disable,
197 };
198 
199 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev)	\
200 	{						\
201 		.name	= _name,			\
202 		.dev	= _dev,				\
203 		.ops	= &clk_pxa3xx_cken_ops,		\
204 		.rate	= _rate,			\
205 		.cken	= CKEN_##_cken,			\
206 		.delay	= _delay,			\
207 	}
208 
209 #define PXA3xx_CK(_name, _cken, _ops, _dev)		\
210 	{						\
211 		.name	= _name,			\
212 		.dev	= _dev,				\
213 		.ops	= _ops,				\
214 		.cken	= CKEN_##_cken,			\
215 	}
216 
217 static struct clk pxa3xx_clks[] = {
218 	{
219 		.name           = "CLK_POUT",
220 		.ops            = &clk_pout_ops,
221 		.rate           = 13000000,
222 		.delay          = 70,
223 	},
224 
225 	PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
226 	PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
227 	PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
228 
229 	PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
230 	PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
231 	PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
232 
233 	PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
234 	PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
235 	PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
236 	PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
237 
238 	PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
239 	PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
240 	PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
241 	PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
242 
243 	PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
244 	PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
245 	PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
246 };
247 
248 #ifdef CONFIG_PM
249 
250 #define ISRAM_START	0x5c000000
251 #define ISRAM_SIZE	SZ_256K
252 
253 static void __iomem *sram;
254 static unsigned long wakeup_src;
255 
256 #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
257 #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
258 
259 enum {	SLEEP_SAVE_CKENA,
260 	SLEEP_SAVE_CKENB,
261 	SLEEP_SAVE_ACCR,
262 
263 	SLEEP_SAVE_COUNT,
264 };
265 
266 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
267 {
268 	SAVE(CKENA);
269 	SAVE(CKENB);
270 	SAVE(ACCR);
271 }
272 
273 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
274 {
275 	RESTORE(ACCR);
276 	RESTORE(CKENA);
277 	RESTORE(CKENB);
278 }
279 
280 /*
281  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
282  * memory controller has to be reinitialised, so we place some code
283  * in the SRAM to perform this function.
284  *
285  * We disable FIQs across the standby - otherwise, we might receive a
286  * FIQ while the SDRAM is unavailable.
287  */
288 static void pxa3xx_cpu_standby(unsigned int pwrmode)
289 {
290 	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
291 	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
292 
293 	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
294 		    pm_enter_standby_end - pm_enter_standby_start);
295 
296 	AD2D0SR = ~0;
297 	AD2D1SR = ~0;
298 	AD2D0ER = wakeup_src;
299 	AD2D1ER = 0;
300 	ASCR = ASCR;
301 	ARSR = ARSR;
302 
303 	local_fiq_disable();
304 	fn(pwrmode);
305 	local_fiq_enable();
306 
307 	AD2D0ER = 0;
308 	AD2D1ER = 0;
309 }
310 
311 /*
312  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
313  * PXA3xx development kits assumes that the resuming process continues
314  * with the address stored within the first 4 bytes of SDRAM. The PSPR
315  * register is used privately by BootROM and OBM, and _must_ be set to
316  * 0x5c014000 for the moment.
317  */
318 static void pxa3xx_cpu_pm_suspend(void)
319 {
320 	volatile unsigned long *p = (volatile void *)0xc0000000;
321 	unsigned long saved_data = *p;
322 
323 	extern void pxa3xx_cpu_suspend(void);
324 	extern void pxa3xx_cpu_resume(void);
325 
326 	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
327 	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
328 	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
329 
330 	/* clear and setup wakeup source */
331 	AD3SR = ~0;
332 	AD3ER = wakeup_src;
333 	ASCR = ASCR;
334 	ARSR = ARSR;
335 
336 	PCFR |= (1u << 13);			/* L1_DIS */
337 	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */
338 
339 	PSPR = 0x5c014000;
340 
341 	/* overwrite with the resume address */
342 	*p = virt_to_phys(pxa3xx_cpu_resume);
343 
344 	pxa3xx_cpu_suspend();
345 
346 	*p = saved_data;
347 
348 	AD3ER = 0;
349 }
350 
351 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
352 {
353 	/*
354 	 * Don't sleep if no wakeup sources are defined
355 	 */
356 	if (wakeup_src == 0) {
357 		printk(KERN_ERR "Not suspending: no wakeup sources\n");
358 		return;
359 	}
360 
361 	switch (state) {
362 	case PM_SUSPEND_STANDBY:
363 		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
364 		break;
365 
366 	case PM_SUSPEND_MEM:
367 		pxa3xx_cpu_pm_suspend();
368 		break;
369 	}
370 }
371 
372 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
373 {
374 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
375 }
376 
377 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
378 	.save_count	= SLEEP_SAVE_COUNT,
379 	.save		= pxa3xx_cpu_pm_save,
380 	.restore	= pxa3xx_cpu_pm_restore,
381 	.valid		= pxa3xx_cpu_pm_valid,
382 	.enter		= pxa3xx_cpu_pm_enter,
383 };
384 
385 static void __init pxa3xx_init_pm(void)
386 {
387 	sram = ioremap(ISRAM_START, ISRAM_SIZE);
388 	if (!sram) {
389 		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
390 		return;
391 	}
392 
393 	/*
394 	 * Since we copy wakeup code into the SRAM, we need to ensure
395 	 * that it is preserved over the low power modes.  Note: bit 8
396 	 * is undocumented in the developer manual, but must be set.
397 	 */
398 	AD1R |= ADXR_L2 | ADXR_R0;
399 	AD2R |= ADXR_L2 | ADXR_R0;
400 	AD3R |= ADXR_L2 | ADXR_R0;
401 
402 	/*
403 	 * Clear the resume enable registers.
404 	 */
405 	AD1D0ER = 0;
406 	AD2D0ER = 0;
407 	AD2D1ER = 0;
408 	AD3ER = 0;
409 
410 	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
411 }
412 
413 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
414 {
415 	unsigned long flags, mask = 0;
416 
417 	switch (irq) {
418 	case IRQ_SSP3:
419 		mask = ADXER_MFP_WSSP3;
420 		break;
421 	case IRQ_MSL:
422 		mask = ADXER_WMSL0;
423 		break;
424 	case IRQ_USBH2:
425 	case IRQ_USBH1:
426 		mask = ADXER_WUSBH;
427 		break;
428 	case IRQ_KEYPAD:
429 		mask = ADXER_WKP;
430 		break;
431 	case IRQ_AC97:
432 		mask = ADXER_MFP_WAC97;
433 		break;
434 	case IRQ_USIM:
435 		mask = ADXER_WUSIM0;
436 		break;
437 	case IRQ_SSP2:
438 		mask = ADXER_MFP_WSSP2;
439 		break;
440 	case IRQ_I2C:
441 		mask = ADXER_MFP_WI2C;
442 		break;
443 	case IRQ_STUART:
444 		mask = ADXER_MFP_WUART3;
445 		break;
446 	case IRQ_BTUART:
447 		mask = ADXER_MFP_WUART2;
448 		break;
449 	case IRQ_FFUART:
450 		mask = ADXER_MFP_WUART1;
451 		break;
452 	case IRQ_MMC:
453 		mask = ADXER_MFP_WMMC1;
454 		break;
455 	case IRQ_SSP:
456 		mask = ADXER_MFP_WSSP1;
457 		break;
458 	case IRQ_RTCAlrm:
459 		mask = ADXER_WRTC;
460 		break;
461 	case IRQ_SSP4:
462 		mask = ADXER_MFP_WSSP4;
463 		break;
464 	case IRQ_TSI:
465 		mask = ADXER_WTSI;
466 		break;
467 	case IRQ_USIM2:
468 		mask = ADXER_WUSIM1;
469 		break;
470 	case IRQ_MMC2:
471 		mask = ADXER_MFP_WMMC2;
472 		break;
473 	case IRQ_NAND:
474 		mask = ADXER_MFP_WFLASH;
475 		break;
476 	case IRQ_USB2:
477 		mask = ADXER_WUSB2;
478 		break;
479 	case IRQ_WAKEUP0:
480 		mask = ADXER_WEXTWAKE0;
481 		break;
482 	case IRQ_WAKEUP1:
483 		mask = ADXER_WEXTWAKE1;
484 		break;
485 	case IRQ_MMC3:
486 		mask = ADXER_MFP_GEN12;
487 		break;
488 	default:
489 		return -EINVAL;
490 	}
491 
492 	local_irq_save(flags);
493 	if (on)
494 		wakeup_src |= mask;
495 	else
496 		wakeup_src &= ~mask;
497 	local_irq_restore(flags);
498 
499 	return 0;
500 }
501 #else
502 static inline void pxa3xx_init_pm(void) {}
503 #define pxa3xx_set_wake	NULL
504 #endif
505 
506 void __init pxa3xx_init_irq(void)
507 {
508 	/* enable CP6 access */
509 	u32 value;
510 	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
511 	value |= (1 << 6);
512 	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
513 
514 	pxa_init_irq(56, pxa3xx_set_wake);
515 	pxa_init_gpio(128, NULL);
516 }
517 
518 /*
519  * device registration specific to PXA3xx.
520  */
521 
522 static struct platform_device *devices[] __initdata = {
523 	&pxa_device_udc,
524 	&pxa_device_ffuart,
525 	&pxa_device_btuart,
526 	&pxa_device_stuart,
527 	&pxa_device_i2s,
528 	&pxa_device_rtc,
529 	&pxa27x_device_ssp1,
530 	&pxa27x_device_ssp2,
531 	&pxa27x_device_ssp3,
532 	&pxa3xx_device_ssp4,
533 };
534 
535 static struct sys_device pxa3xx_sysdev[] = {
536 	{
537 		.cls	= &pxa_irq_sysclass,
538 	}, {
539 		.cls	= &pxa3xx_mfp_sysclass,
540 	}, {
541 		.cls	= &pxa_gpio_sysclass,
542 	},
543 };
544 
545 static int __init pxa3xx_init(void)
546 {
547 	int i, ret = 0;
548 
549 	if (cpu_is_pxa3xx()) {
550 		/*
551 		 * clear RDH bit every time after reset
552 		 *
553 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
554 		 * preserve them here in case they will be referenced later
555 		 */
556 		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
557 
558 		clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
559 
560 		if ((ret = pxa_init_dma(32)))
561 			return ret;
562 
563 		pxa3xx_init_pm();
564 
565 		for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
566 			ret = sysdev_register(&pxa3xx_sysdev[i]);
567 			if (ret)
568 				pr_err("failed to register sysdev[%d]\n", i);
569 		}
570 
571 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
572 	}
573 
574 	return ret;
575 }
576 
577 postcore_initcall(pxa3xx_init);
578