1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/pm.h> 19 #include <linux/platform_device.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/syscore_ops.h> 23 #include <linux/i2c/pxa-i2c.h> 24 25 #include <asm/mach/map.h> 26 #include <asm/suspend.h> 27 #include <mach/hardware.h> 28 #include <mach/pxa3xx-regs.h> 29 #include <mach/reset.h> 30 #include <mach/ohci.h> 31 #include <mach/pm.h> 32 #include <mach/dma.h> 33 #include <mach/smemc.h> 34 35 #include "generic.h" 36 #include "devices.h" 37 #include "clock.h" 38 39 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 40 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 41 42 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 43 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 44 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 45 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 46 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 47 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 48 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 49 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 50 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 51 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 52 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 53 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 54 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 55 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 56 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 57 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 58 59 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 60 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); 61 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 62 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 63 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); 64 65 static struct clk_lookup pxa3xx_clkregs[] = { 66 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 67 /* Power I2C clock is always on */ 68 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 69 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 70 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 71 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 72 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 73 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 74 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 75 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 76 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 77 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 78 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 79 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 80 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 81 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 82 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 83 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 84 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 85 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 86 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 87 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 88 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 89 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), 90 }; 91 92 #ifdef CONFIG_PM 93 94 #define ISRAM_START 0x5c000000 95 #define ISRAM_SIZE SZ_256K 96 97 static void __iomem *sram; 98 static unsigned long wakeup_src; 99 100 /* 101 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 102 * memory controller has to be reinitialised, so we place some code 103 * in the SRAM to perform this function. 104 * 105 * We disable FIQs across the standby - otherwise, we might receive a 106 * FIQ while the SDRAM is unavailable. 107 */ 108 static void pxa3xx_cpu_standby(unsigned int pwrmode) 109 { 110 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 111 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 112 113 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 114 pm_enter_standby_end - pm_enter_standby_start); 115 116 AD2D0SR = ~0; 117 AD2D1SR = ~0; 118 AD2D0ER = wakeup_src; 119 AD2D1ER = 0; 120 ASCR = ASCR; 121 ARSR = ARSR; 122 123 local_fiq_disable(); 124 fn(pwrmode); 125 local_fiq_enable(); 126 127 AD2D0ER = 0; 128 AD2D1ER = 0; 129 } 130 131 /* 132 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 133 * PXA3xx development kits assumes that the resuming process continues 134 * with the address stored within the first 4 bytes of SDRAM. The PSPR 135 * register is used privately by BootROM and OBM, and _must_ be set to 136 * 0x5c014000 for the moment. 137 */ 138 static void pxa3xx_cpu_pm_suspend(void) 139 { 140 volatile unsigned long *p = (volatile void *)0xc0000000; 141 unsigned long saved_data = *p; 142 #ifndef CONFIG_IWMMXT 143 u64 acc0; 144 145 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); 146 #endif 147 148 extern int pxa3xx_finish_suspend(unsigned long); 149 150 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 151 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 152 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 153 154 /* clear and setup wakeup source */ 155 AD3SR = ~0; 156 AD3ER = wakeup_src; 157 ASCR = ASCR; 158 ARSR = ARSR; 159 160 PCFR |= (1u << 13); /* L1_DIS */ 161 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 162 163 PSPR = 0x5c014000; 164 165 /* overwrite with the resume address */ 166 *p = virt_to_phys(cpu_resume); 167 168 cpu_suspend(0, pxa3xx_finish_suspend); 169 170 *p = saved_data; 171 172 AD3ER = 0; 173 174 #ifndef CONFIG_IWMMXT 175 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); 176 #endif 177 } 178 179 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 180 { 181 /* 182 * Don't sleep if no wakeup sources are defined 183 */ 184 if (wakeup_src == 0) { 185 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 186 return; 187 } 188 189 switch (state) { 190 case PM_SUSPEND_STANDBY: 191 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 192 break; 193 194 case PM_SUSPEND_MEM: 195 pxa3xx_cpu_pm_suspend(); 196 break; 197 } 198 } 199 200 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 201 { 202 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 203 } 204 205 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 206 .valid = pxa3xx_cpu_pm_valid, 207 .enter = pxa3xx_cpu_pm_enter, 208 }; 209 210 static void __init pxa3xx_init_pm(void) 211 { 212 sram = ioremap(ISRAM_START, ISRAM_SIZE); 213 if (!sram) { 214 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 215 return; 216 } 217 218 /* 219 * Since we copy wakeup code into the SRAM, we need to ensure 220 * that it is preserved over the low power modes. Note: bit 8 221 * is undocumented in the developer manual, but must be set. 222 */ 223 AD1R |= ADXR_L2 | ADXR_R0; 224 AD2R |= ADXR_L2 | ADXR_R0; 225 AD3R |= ADXR_L2 | ADXR_R0; 226 227 /* 228 * Clear the resume enable registers. 229 */ 230 AD1D0ER = 0; 231 AD2D0ER = 0; 232 AD2D1ER = 0; 233 AD3ER = 0; 234 235 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 236 } 237 238 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 239 { 240 unsigned long flags, mask = 0; 241 242 switch (d->irq) { 243 case IRQ_SSP3: 244 mask = ADXER_MFP_WSSP3; 245 break; 246 case IRQ_MSL: 247 mask = ADXER_WMSL0; 248 break; 249 case IRQ_USBH2: 250 case IRQ_USBH1: 251 mask = ADXER_WUSBH; 252 break; 253 case IRQ_KEYPAD: 254 mask = ADXER_WKP; 255 break; 256 case IRQ_AC97: 257 mask = ADXER_MFP_WAC97; 258 break; 259 case IRQ_USIM: 260 mask = ADXER_WUSIM0; 261 break; 262 case IRQ_SSP2: 263 mask = ADXER_MFP_WSSP2; 264 break; 265 case IRQ_I2C: 266 mask = ADXER_MFP_WI2C; 267 break; 268 case IRQ_STUART: 269 mask = ADXER_MFP_WUART3; 270 break; 271 case IRQ_BTUART: 272 mask = ADXER_MFP_WUART2; 273 break; 274 case IRQ_FFUART: 275 mask = ADXER_MFP_WUART1; 276 break; 277 case IRQ_MMC: 278 mask = ADXER_MFP_WMMC1; 279 break; 280 case IRQ_SSP: 281 mask = ADXER_MFP_WSSP1; 282 break; 283 case IRQ_RTCAlrm: 284 mask = ADXER_WRTC; 285 break; 286 case IRQ_SSP4: 287 mask = ADXER_MFP_WSSP4; 288 break; 289 case IRQ_TSI: 290 mask = ADXER_WTSI; 291 break; 292 case IRQ_USIM2: 293 mask = ADXER_WUSIM1; 294 break; 295 case IRQ_MMC2: 296 mask = ADXER_MFP_WMMC2; 297 break; 298 case IRQ_NAND: 299 mask = ADXER_MFP_WFLASH; 300 break; 301 case IRQ_USB2: 302 mask = ADXER_WUSB2; 303 break; 304 case IRQ_WAKEUP0: 305 mask = ADXER_WEXTWAKE0; 306 break; 307 case IRQ_WAKEUP1: 308 mask = ADXER_WEXTWAKE1; 309 break; 310 case IRQ_MMC3: 311 mask = ADXER_MFP_GEN12; 312 break; 313 default: 314 return -EINVAL; 315 } 316 317 local_irq_save(flags); 318 if (on) 319 wakeup_src |= mask; 320 else 321 wakeup_src &= ~mask; 322 local_irq_restore(flags); 323 324 return 0; 325 } 326 #else 327 static inline void pxa3xx_init_pm(void) {} 328 #define pxa3xx_set_wake NULL 329 #endif 330 331 static void pxa_ack_ext_wakeup(struct irq_data *d) 332 { 333 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 334 } 335 336 static void pxa_mask_ext_wakeup(struct irq_data *d) 337 { 338 pxa_mask_irq(d); 339 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 340 } 341 342 static void pxa_unmask_ext_wakeup(struct irq_data *d) 343 { 344 pxa_unmask_irq(d); 345 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 346 } 347 348 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 349 { 350 if (flow_type & IRQ_TYPE_EDGE_RISING) 351 PWER |= 1 << (d->irq - IRQ_WAKEUP0); 352 353 if (flow_type & IRQ_TYPE_EDGE_FALLING) 354 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 355 356 return 0; 357 } 358 359 static struct irq_chip pxa_ext_wakeup_chip = { 360 .name = "WAKEUP", 361 .irq_ack = pxa_ack_ext_wakeup, 362 .irq_mask = pxa_mask_ext_wakeup, 363 .irq_unmask = pxa_unmask_ext_wakeup, 364 .irq_set_type = pxa_set_ext_wakeup_type, 365 }; 366 367 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, 368 unsigned int)) 369 { 370 int irq; 371 372 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 373 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 374 handle_edge_irq); 375 set_irq_flags(irq, IRQF_VALID); 376 } 377 378 pxa_ext_wakeup_chip.irq_set_wake = fn; 379 } 380 381 void __init pxa3xx_init_irq(void) 382 { 383 /* enable CP6 access */ 384 u32 value; 385 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 386 value |= (1 << 6); 387 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 388 389 pxa_init_irq(56, pxa3xx_set_wake); 390 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 391 } 392 393 static struct map_desc pxa3xx_io_desc[] __initdata = { 394 { /* Mem Ctl */ 395 .virtual = (unsigned long)SMEMC_VIRT, 396 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 397 .length = 0x00200000, 398 .type = MT_DEVICE 399 } 400 }; 401 402 void __init pxa3xx_map_io(void) 403 { 404 pxa_map_io(); 405 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 406 pxa3xx_get_clk_frequency_khz(1); 407 } 408 409 /* 410 * device registration specific to PXA3xx. 411 */ 412 413 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 414 { 415 pxa_register_device(&pxa3xx_device_i2c_power, info); 416 } 417 418 static struct platform_device *devices[] __initdata = { 419 &pxa_device_gpio, 420 &pxa27x_device_udc, 421 &pxa_device_pmu, 422 &pxa_device_i2s, 423 &pxa_device_asoc_ssp1, 424 &pxa_device_asoc_ssp2, 425 &pxa_device_asoc_ssp3, 426 &pxa_device_asoc_ssp4, 427 &pxa_device_asoc_platform, 428 &sa1100_device_rtc, 429 &pxa_device_rtc, 430 &pxa27x_device_ssp1, 431 &pxa27x_device_ssp2, 432 &pxa27x_device_ssp3, 433 &pxa3xx_device_ssp4, 434 &pxa27x_device_pwm0, 435 &pxa27x_device_pwm1, 436 }; 437 438 static int __init pxa3xx_init(void) 439 { 440 int ret = 0; 441 442 if (cpu_is_pxa3xx()) { 443 444 reset_status = ARSR; 445 446 /* 447 * clear RDH bit every time after reset 448 * 449 * Note: the last 3 bits DxS are write-1-to-clear so carefully 450 * preserve them here in case they will be referenced later 451 */ 452 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 453 454 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 455 456 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 457 return ret; 458 459 pxa3xx_init_pm(); 460 461 register_syscore_ops(&pxa_irq_syscore_ops); 462 register_syscore_ops(&pxa3xx_mfp_syscore_ops); 463 register_syscore_ops(&pxa_gpio_syscore_ops); 464 register_syscore_ops(&pxa3xx_clock_syscore_ops); 465 466 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 467 } 468 469 return ret; 470 } 471 472 postcore_initcall(pxa3xx_init); 473