12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao 162c8086a5Seric miao #include <linux/module.h> 172c8086a5Seric miao #include <linux/kernel.h> 182c8086a5Seric miao #include <linux/init.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 222c8086a5Seric miao 232c8086a5Seric miao #include <asm/hardware.h> 242c8086a5Seric miao #include <asm/arch/pxa3xx-regs.h> 252c8086a5Seric miao #include <asm/arch/ohci.h> 262c8086a5Seric miao #include <asm/arch/pm.h> 272c8086a5Seric miao #include <asm/arch/dma.h> 282c8086a5Seric miao #include <asm/arch/ssp.h> 292c8086a5Seric miao 302c8086a5Seric miao #include "generic.h" 312c8086a5Seric miao #include "devices.h" 322c8086a5Seric miao #include "clock.h" 332c8086a5Seric miao 342c8086a5Seric miao /* Crystal clock: 13MHz */ 352c8086a5Seric miao #define BASE_CLK 13000000 362c8086a5Seric miao 372c8086a5Seric miao /* Ring Oscillator Clock: 60MHz */ 382c8086a5Seric miao #define RO_CLK 60000000 392c8086a5Seric miao 402c8086a5Seric miao #define ACCR_D0CS (1 << 26) 412c8086a5Seric miao 422c8086a5Seric miao /* crystal frequency to static memory controller multiplier (SMCFS) */ 432c8086a5Seric miao static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 442c8086a5Seric miao 452c8086a5Seric miao /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 462c8086a5Seric miao static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 472c8086a5Seric miao 482c8086a5Seric miao /* 492c8086a5Seric miao * Get the clock frequency as reflected by CCSR and the turbo flag. 502c8086a5Seric miao * We assume these values have been applied via a fcs. 512c8086a5Seric miao * If info is not 0 we also display the current settings. 522c8086a5Seric miao */ 532c8086a5Seric miao unsigned int pxa3xx_get_clk_frequency_khz(int info) 542c8086a5Seric miao { 552c8086a5Seric miao unsigned long acsr, xclkcfg; 562c8086a5Seric miao unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 572c8086a5Seric miao 582c8086a5Seric miao /* Read XCLKCFG register turbo bit */ 592c8086a5Seric miao __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 602c8086a5Seric miao t = xclkcfg & 0x1; 612c8086a5Seric miao 622c8086a5Seric miao acsr = ACSR; 632c8086a5Seric miao 642c8086a5Seric miao xl = acsr & 0x1f; 652c8086a5Seric miao xn = (acsr >> 8) & 0x7; 662c8086a5Seric miao hss = (acsr >> 14) & 0x3; 672c8086a5Seric miao 682c8086a5Seric miao XL = xl * BASE_CLK; 692c8086a5Seric miao XN = xn * XL; 702c8086a5Seric miao 712c8086a5Seric miao ro = acsr & ACCR_D0CS; 722c8086a5Seric miao 732c8086a5Seric miao CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 742c8086a5Seric miao HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 752c8086a5Seric miao 762c8086a5Seric miao if (info) { 772c8086a5Seric miao pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 782c8086a5Seric miao RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 792c8086a5Seric miao (ro) ? "" : "in"); 802c8086a5Seric miao pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 812c8086a5Seric miao XL / 1000000, (XL % 1000000) / 10000, xl); 822c8086a5Seric miao pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 832c8086a5Seric miao XN / 1000000, (XN % 1000000) / 10000, xn, 842c8086a5Seric miao (t) ? "" : "in"); 852c8086a5Seric miao pr_info("HSIO bus clock: %d.%02dMHz\n", 862c8086a5Seric miao HSS / 1000000, (HSS % 1000000) / 10000); 872c8086a5Seric miao } 882c8086a5Seric miao 892c8086a5Seric miao return CLK; 902c8086a5Seric miao } 912c8086a5Seric miao 922c8086a5Seric miao /* 932c8086a5Seric miao * Return the current static memory controller clock frequency 942c8086a5Seric miao * in units of 10kHz 952c8086a5Seric miao */ 962c8086a5Seric miao unsigned int pxa3xx_get_memclk_frequency_10khz(void) 972c8086a5Seric miao { 982c8086a5Seric miao unsigned long acsr; 992c8086a5Seric miao unsigned int smcfs, clk = 0; 1002c8086a5Seric miao 1012c8086a5Seric miao acsr = ACSR; 1022c8086a5Seric miao 1032c8086a5Seric miao smcfs = (acsr >> 23) & 0x7; 1042c8086a5Seric miao clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 1052c8086a5Seric miao 1062c8086a5Seric miao return (clk / 10000); 1072c8086a5Seric miao } 1082c8086a5Seric miao 1092c8086a5Seric miao /* 1102c8086a5Seric miao * Return the current HSIO bus clock frequency 1112c8086a5Seric miao */ 1122c8086a5Seric miao static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 1132c8086a5Seric miao { 1142c8086a5Seric miao unsigned long acsr; 1152c8086a5Seric miao unsigned int hss, hsio_clk; 1162c8086a5Seric miao 1172c8086a5Seric miao acsr = ACSR; 1182c8086a5Seric miao 1192c8086a5Seric miao hss = (acsr >> 14) & 0x3; 1202c8086a5Seric miao hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 1212c8086a5Seric miao 1222c8086a5Seric miao return hsio_clk; 1232c8086a5Seric miao } 1242c8086a5Seric miao 1252c8086a5Seric miao static void clk_pxa3xx_cken_enable(struct clk *clk) 1262c8086a5Seric miao { 1272c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1282c8086a5Seric miao 1292c8086a5Seric miao local_irq_disable(); 1302c8086a5Seric miao 1312c8086a5Seric miao if (clk->cken < 32) 1322c8086a5Seric miao CKENA |= mask; 1332c8086a5Seric miao else 1342c8086a5Seric miao CKENB |= mask; 1352c8086a5Seric miao 1362c8086a5Seric miao local_irq_enable(); 1372c8086a5Seric miao } 1382c8086a5Seric miao 1392c8086a5Seric miao static void clk_pxa3xx_cken_disable(struct clk *clk) 1402c8086a5Seric miao { 1412c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1422c8086a5Seric miao 1432c8086a5Seric miao local_irq_disable(); 1442c8086a5Seric miao 1452c8086a5Seric miao if (clk->cken < 32) 1462c8086a5Seric miao CKENA &= ~mask; 1472c8086a5Seric miao else 1482c8086a5Seric miao CKENB &= ~mask; 1492c8086a5Seric miao 1502c8086a5Seric miao local_irq_enable(); 1512c8086a5Seric miao } 1522c8086a5Seric miao 1532a0d7187Seric miao static const struct clkops clk_pxa3xx_cken_ops = { 1542a0d7187Seric miao .enable = clk_pxa3xx_cken_enable, 1552a0d7187Seric miao .disable = clk_pxa3xx_cken_disable, 1562a0d7187Seric miao }; 1572a0d7187Seric miao 1582c8086a5Seric miao static const struct clkops clk_pxa3xx_hsio_ops = { 1592c8086a5Seric miao .enable = clk_pxa3xx_cken_enable, 1602c8086a5Seric miao .disable = clk_pxa3xx_cken_disable, 1612c8086a5Seric miao .getrate = clk_pxa3xx_hsio_getrate, 1622c8086a5Seric miao }; 1632c8086a5Seric miao 1642a0d7187Seric miao #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ 1652a0d7187Seric miao { \ 1662a0d7187Seric miao .name = _name, \ 1672a0d7187Seric miao .dev = _dev, \ 1682a0d7187Seric miao .ops = &clk_pxa3xx_cken_ops, \ 1692a0d7187Seric miao .rate = _rate, \ 1702a0d7187Seric miao .cken = CKEN_##_cken, \ 1712a0d7187Seric miao .delay = _delay, \ 1722a0d7187Seric miao } 1732a0d7187Seric miao 1742a0d7187Seric miao #define PXA3xx_CK(_name, _cken, _ops, _dev) \ 1752a0d7187Seric miao { \ 1762a0d7187Seric miao .name = _name, \ 1772a0d7187Seric miao .dev = _dev, \ 1782a0d7187Seric miao .ops = _ops, \ 1792a0d7187Seric miao .cken = CKEN_##_cken, \ 1802a0d7187Seric miao } 1812a0d7187Seric miao 1822c8086a5Seric miao static struct clk pxa3xx_clks[] = { 1832a0d7187Seric miao PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 1842a0d7187Seric miao PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 1852c8086a5Seric miao 1862a0d7187Seric miao PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 1872a0d7187Seric miao PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 1882a0d7187Seric miao PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 1892c8086a5Seric miao 1902a0d7187Seric miao PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 1912a0d7187Seric miao PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), 192f92a629cSeric miao PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 193d8e0db11Seric miao 194d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 195d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 196d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 197d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 198fafc9d3fSBridge Wu 199fafc9d3fSBridge Wu PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 2008d33b055SBridge Wu PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 2015a1f21b1SBridge Wu PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), 2022c8086a5Seric miao }; 2032c8086a5Seric miao 2042c8086a5Seric miao void __init pxa3xx_init_irq(void) 2052c8086a5Seric miao { 2062c8086a5Seric miao /* enable CP6 access */ 2072c8086a5Seric miao u32 value; 2082c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 2092c8086a5Seric miao value |= (1 << 6); 2102c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 2112c8086a5Seric miao 2122c8086a5Seric miao pxa_init_irq_low(); 2132c8086a5Seric miao pxa_init_irq_high(); 2142c8086a5Seric miao pxa_init_irq_gpio(128); 2152c8086a5Seric miao } 2162c8086a5Seric miao 2172c8086a5Seric miao /* 2182c8086a5Seric miao * device registration specific to PXA3xx. 2192c8086a5Seric miao */ 2202c8086a5Seric miao 2212c8086a5Seric miao static struct platform_device *devices[] __initdata = { 2222c8086a5Seric miao &pxa_device_udc, 2232c8086a5Seric miao &pxa_device_ffuart, 2242c8086a5Seric miao &pxa_device_btuart, 2252c8086a5Seric miao &pxa_device_stuart, 2262c8086a5Seric miao &pxa_device_i2s, 2272c8086a5Seric miao &pxa_device_rtc, 228d8e0db11Seric miao &pxa27x_device_ssp1, 229d8e0db11Seric miao &pxa27x_device_ssp2, 230d8e0db11Seric miao &pxa27x_device_ssp3, 231d8e0db11Seric miao &pxa3xx_device_ssp4, 2322c8086a5Seric miao }; 2332c8086a5Seric miao 2342c8086a5Seric miao static int __init pxa3xx_init(void) 2352c8086a5Seric miao { 2362c8086a5Seric miao int ret = 0; 2372c8086a5Seric miao 2382c8086a5Seric miao if (cpu_is_pxa3xx()) { 2392c8086a5Seric miao clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 2402c8086a5Seric miao 2412c8086a5Seric miao if ((ret = pxa_init_dma(32))) 2422c8086a5Seric miao return ret; 2432c8086a5Seric miao 2442c8086a5Seric miao return platform_add_devices(devices, ARRAY_SIZE(devices)); 2452c8086a5Seric miao } 2462c8086a5Seric miao return 0; 2472c8086a5Seric miao } 2482c8086a5Seric miao 2492c8086a5Seric miao subsys_initcall(pxa3xx_init); 250