12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao 162c8086a5Seric miao #include <linux/module.h> 172c8086a5Seric miao #include <linux/kernel.h> 182c8086a5Seric miao #include <linux/init.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 227b5dea12SRussell King #include <linux/io.h> 23c0165504Seric miao #include <linux/sysdev.h> 242c8086a5Seric miao 25a09e64fbSRussell King #include <mach/hardware.h> 26a58fbcd8SEric Miao #include <mach/gpio.h> 27a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 28afd2fc02SRussell King #include <mach/reset.h> 29a09e64fbSRussell King #include <mach/ohci.h> 30a09e64fbSRussell King #include <mach/pm.h> 31a09e64fbSRussell King #include <mach/dma.h> 32a09e64fbSRussell King #include <mach/ssp.h> 33f0a83701SEric Miao #include <plat/i2c.h> 342c8086a5Seric miao 352c8086a5Seric miao #include "generic.h" 362c8086a5Seric miao #include "devices.h" 372c8086a5Seric miao #include "clock.h" 382c8086a5Seric miao 392c8086a5Seric miao /* Crystal clock: 13MHz */ 402c8086a5Seric miao #define BASE_CLK 13000000 412c8086a5Seric miao 422c8086a5Seric miao /* Ring Oscillator Clock: 60MHz */ 432c8086a5Seric miao #define RO_CLK 60000000 442c8086a5Seric miao 452c8086a5Seric miao #define ACCR_D0CS (1 << 26) 46c4d1fb62Seric miao #define ACCR_PCCE (1 << 11) 472c8086a5Seric miao 482c8086a5Seric miao /* crystal frequency to static memory controller multiplier (SMCFS) */ 492c8086a5Seric miao static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 502c8086a5Seric miao 512c8086a5Seric miao /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 522c8086a5Seric miao static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 532c8086a5Seric miao 542c8086a5Seric miao /* 552c8086a5Seric miao * Get the clock frequency as reflected by CCSR and the turbo flag. 562c8086a5Seric miao * We assume these values have been applied via a fcs. 572c8086a5Seric miao * If info is not 0 we also display the current settings. 582c8086a5Seric miao */ 592c8086a5Seric miao unsigned int pxa3xx_get_clk_frequency_khz(int info) 602c8086a5Seric miao { 612c8086a5Seric miao unsigned long acsr, xclkcfg; 622c8086a5Seric miao unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 632c8086a5Seric miao 642c8086a5Seric miao /* Read XCLKCFG register turbo bit */ 652c8086a5Seric miao __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 662c8086a5Seric miao t = xclkcfg & 0x1; 672c8086a5Seric miao 682c8086a5Seric miao acsr = ACSR; 692c8086a5Seric miao 702c8086a5Seric miao xl = acsr & 0x1f; 712c8086a5Seric miao xn = (acsr >> 8) & 0x7; 722c8086a5Seric miao hss = (acsr >> 14) & 0x3; 732c8086a5Seric miao 742c8086a5Seric miao XL = xl * BASE_CLK; 752c8086a5Seric miao XN = xn * XL; 762c8086a5Seric miao 772c8086a5Seric miao ro = acsr & ACCR_D0CS; 782c8086a5Seric miao 792c8086a5Seric miao CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 802c8086a5Seric miao HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 812c8086a5Seric miao 822c8086a5Seric miao if (info) { 832c8086a5Seric miao pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 842c8086a5Seric miao RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 852c8086a5Seric miao (ro) ? "" : "in"); 862c8086a5Seric miao pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 872c8086a5Seric miao XL / 1000000, (XL % 1000000) / 10000, xl); 882c8086a5Seric miao pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 892c8086a5Seric miao XN / 1000000, (XN % 1000000) / 10000, xn, 902c8086a5Seric miao (t) ? "" : "in"); 912c8086a5Seric miao pr_info("HSIO bus clock: %d.%02dMHz\n", 922c8086a5Seric miao HSS / 1000000, (HSS % 1000000) / 10000); 932c8086a5Seric miao } 942c8086a5Seric miao 956232be32Seric miao return CLK / 1000; 962c8086a5Seric miao } 972c8086a5Seric miao 982c8086a5Seric miao /* 992c8086a5Seric miao * Return the current static memory controller clock frequency 1002c8086a5Seric miao * in units of 10kHz 1012c8086a5Seric miao */ 1022c8086a5Seric miao unsigned int pxa3xx_get_memclk_frequency_10khz(void) 1032c8086a5Seric miao { 1042c8086a5Seric miao unsigned long acsr; 1052c8086a5Seric miao unsigned int smcfs, clk = 0; 1062c8086a5Seric miao 1072c8086a5Seric miao acsr = ACSR; 1082c8086a5Seric miao 1092c8086a5Seric miao smcfs = (acsr >> 23) & 0x7; 1102c8086a5Seric miao clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 1112c8086a5Seric miao 1122c8086a5Seric miao return (clk / 10000); 1132c8086a5Seric miao } 1142c8086a5Seric miao 11504fef228SEric Miao void pxa3xx_clear_reset_status(unsigned int mask) 11604fef228SEric Miao { 11704fef228SEric Miao /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 11804fef228SEric Miao ARSR = mask; 11904fef228SEric Miao } 12004fef228SEric Miao 1212c8086a5Seric miao /* 12260bfe7faSMark Brown * Return the current AC97 clock frequency. 12360bfe7faSMark Brown */ 12460bfe7faSMark Brown static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 12560bfe7faSMark Brown { 12660bfe7faSMark Brown unsigned long rate = 312000000; 12760bfe7faSMark Brown unsigned long ac97_div; 12860bfe7faSMark Brown 12960bfe7faSMark Brown ac97_div = AC97_DIV; 13060bfe7faSMark Brown 13160bfe7faSMark Brown /* This may loose precision for some rates but won't for the 13260bfe7faSMark Brown * standard 24.576MHz. 13360bfe7faSMark Brown */ 13460bfe7faSMark Brown rate /= (ac97_div >> 12) & 0x7fff; 13560bfe7faSMark Brown rate *= (ac97_div & 0xfff); 13660bfe7faSMark Brown 13760bfe7faSMark Brown return rate; 13860bfe7faSMark Brown } 13960bfe7faSMark Brown 14060bfe7faSMark Brown /* 1412c8086a5Seric miao * Return the current HSIO bus clock frequency 1422c8086a5Seric miao */ 1432c8086a5Seric miao static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 1442c8086a5Seric miao { 1452c8086a5Seric miao unsigned long acsr; 1462c8086a5Seric miao unsigned int hss, hsio_clk; 1472c8086a5Seric miao 1482c8086a5Seric miao acsr = ACSR; 1492c8086a5Seric miao 1502c8086a5Seric miao hss = (acsr >> 14) & 0x3; 1512c8086a5Seric miao hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 1522c8086a5Seric miao 1532c8086a5Seric miao return hsio_clk; 1542c8086a5Seric miao } 1552c8086a5Seric miao 1567a2c5cb0Seric miao void clk_pxa3xx_cken_enable(struct clk *clk) 1572c8086a5Seric miao { 1582c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1592c8086a5Seric miao 1602c8086a5Seric miao if (clk->cken < 32) 1612c8086a5Seric miao CKENA |= mask; 1622c8086a5Seric miao else 1632c8086a5Seric miao CKENB |= mask; 1642c8086a5Seric miao } 1652c8086a5Seric miao 1667a2c5cb0Seric miao void clk_pxa3xx_cken_disable(struct clk *clk) 1672c8086a5Seric miao { 1682c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1692c8086a5Seric miao 1702c8086a5Seric miao if (clk->cken < 32) 1712c8086a5Seric miao CKENA &= ~mask; 1722c8086a5Seric miao else 1732c8086a5Seric miao CKENB &= ~mask; 1742c8086a5Seric miao } 1752c8086a5Seric miao 1767a2c5cb0Seric miao const struct clkops clk_pxa3xx_cken_ops = { 1772a0d7187Seric miao .enable = clk_pxa3xx_cken_enable, 1782a0d7187Seric miao .disable = clk_pxa3xx_cken_disable, 1792a0d7187Seric miao }; 1802a0d7187Seric miao 1812c8086a5Seric miao static const struct clkops clk_pxa3xx_hsio_ops = { 1822c8086a5Seric miao .enable = clk_pxa3xx_cken_enable, 1832c8086a5Seric miao .disable = clk_pxa3xx_cken_disable, 1842c8086a5Seric miao .getrate = clk_pxa3xx_hsio_getrate, 1852c8086a5Seric miao }; 1862c8086a5Seric miao 18760bfe7faSMark Brown static const struct clkops clk_pxa3xx_ac97_ops = { 18860bfe7faSMark Brown .enable = clk_pxa3xx_cken_enable, 18960bfe7faSMark Brown .disable = clk_pxa3xx_cken_disable, 19060bfe7faSMark Brown .getrate = clk_pxa3xx_ac97_getrate, 19160bfe7faSMark Brown }; 19260bfe7faSMark Brown 193dcc88a17SMark Brown static void clk_pout_enable(struct clk *clk) 194dcc88a17SMark Brown { 195dcc88a17SMark Brown OSCC |= OSCC_PEN; 196dcc88a17SMark Brown } 197dcc88a17SMark Brown 198dcc88a17SMark Brown static void clk_pout_disable(struct clk *clk) 199dcc88a17SMark Brown { 200dcc88a17SMark Brown OSCC &= ~OSCC_PEN; 201dcc88a17SMark Brown } 202dcc88a17SMark Brown 203dcc88a17SMark Brown static const struct clkops clk_pout_ops = { 204dcc88a17SMark Brown .enable = clk_pout_enable, 205dcc88a17SMark Brown .disable = clk_pout_disable, 206dcc88a17SMark Brown }; 207dcc88a17SMark Brown 2089ba63c4fSMike Rapoport static void clk_dummy_enable(struct clk *clk) 2099ba63c4fSMike Rapoport { 2109ba63c4fSMike Rapoport } 2119ba63c4fSMike Rapoport 2129ba63c4fSMike Rapoport static void clk_dummy_disable(struct clk *clk) 2139ba63c4fSMike Rapoport { 2149ba63c4fSMike Rapoport } 2159ba63c4fSMike Rapoport 2169ba63c4fSMike Rapoport static const struct clkops clk_dummy_ops = { 2179ba63c4fSMike Rapoport .enable = clk_dummy_enable, 2189ba63c4fSMike Rapoport .disable = clk_dummy_disable, 2199ba63c4fSMike Rapoport }; 2209ba63c4fSMike Rapoport 2218c3abc7dSRussell King static struct clk clk_pxa3xx_pout = { 222dcc88a17SMark Brown .ops = &clk_pout_ops, 223dcc88a17SMark Brown .rate = 13000000, 224dcc88a17SMark Brown .delay = 70, 2258c3abc7dSRussell King }; 226dcc88a17SMark Brown 2278c3abc7dSRussell King static struct clk clk_dummy = { 2289ba63c4fSMike Rapoport .ops = &clk_dummy_ops, 2298c3abc7dSRussell King }; 2309ba63c4fSMike Rapoport 2318c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 2328c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 2338c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 2348c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 2358c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 2368c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 2378c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 2388c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 2398c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 2408c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 2418c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 2428c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 2438c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 2448c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 2458c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 2468c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 2478c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 2488c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 2492c8086a5Seric miao 2508c3abc7dSRussell King static struct clk_lookup pxa3xx_clkregs[] = { 2518c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 2528c3abc7dSRussell King /* Power I2C clock is always on */ 2538c3abc7dSRussell King INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL), 2548c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 2558c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 2568c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 2578c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 2588c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 2598c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 2608c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 2618c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 2628c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 2638c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 2648c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 2658c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 2668c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 2678c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 2688c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 2698c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 2708c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 2718c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 2728c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 2732c8086a5Seric miao }; 2742c8086a5Seric miao 2757b5dea12SRussell King #ifdef CONFIG_PM 2767b5dea12SRussell King 2777b5dea12SRussell King #define ISRAM_START 0x5c000000 2787b5dea12SRussell King #define ISRAM_SIZE SZ_256K 2797b5dea12SRussell King 2807b5dea12SRussell King static void __iomem *sram; 2817b5dea12SRussell King static unsigned long wakeup_src; 2827b5dea12SRussell King 283c4d1fb62Seric miao #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 284c4d1fb62Seric miao #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 285c4d1fb62Seric miao 286649de51bSRobert Jarzmik enum { SLEEP_SAVE_CKENA, 287c4d1fb62Seric miao SLEEP_SAVE_CKENB, 288c4d1fb62Seric miao SLEEP_SAVE_ACCR, 289c4d1fb62Seric miao 290649de51bSRobert Jarzmik SLEEP_SAVE_COUNT, 291c4d1fb62Seric miao }; 292c4d1fb62Seric miao 2937b5dea12SRussell King static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 2947b5dea12SRussell King { 295c4d1fb62Seric miao SAVE(CKENA); 296c4d1fb62Seric miao SAVE(CKENB); 297c4d1fb62Seric miao SAVE(ACCR); 2987b5dea12SRussell King } 2997b5dea12SRussell King 3007b5dea12SRussell King static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 3017b5dea12SRussell King { 302c4d1fb62Seric miao RESTORE(ACCR); 303c4d1fb62Seric miao RESTORE(CKENA); 304c4d1fb62Seric miao RESTORE(CKENB); 3057b5dea12SRussell King } 3067b5dea12SRussell King 3077b5dea12SRussell King /* 3087b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 3097b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 3107b5dea12SRussell King * in the SRAM to perform this function. 3117b5dea12SRussell King * 3127b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 3137b5dea12SRussell King * FIQ while the SDRAM is unavailable. 3147b5dea12SRussell King */ 3157b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 3167b5dea12SRussell King { 3177b5dea12SRussell King extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 3187b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 3197b5dea12SRussell King 3207b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 3217b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 3227b5dea12SRussell King 3237b5dea12SRussell King AD2D0SR = ~0; 3247b5dea12SRussell King AD2D1SR = ~0; 3257b5dea12SRussell King AD2D0ER = wakeup_src; 3267b5dea12SRussell King AD2D1ER = 0; 3277b5dea12SRussell King ASCR = ASCR; 3287b5dea12SRussell King ARSR = ARSR; 3297b5dea12SRussell King 3307b5dea12SRussell King local_fiq_disable(); 3317b5dea12SRussell King fn(pwrmode); 3327b5dea12SRussell King local_fiq_enable(); 3337b5dea12SRussell King 3347b5dea12SRussell King AD2D0ER = 0; 3357b5dea12SRussell King AD2D1ER = 0; 3367b5dea12SRussell King } 3377b5dea12SRussell King 338c4d1fb62Seric miao /* 339c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 340c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 341c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 342c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 343c4d1fb62Seric miao * 0x5c014000 for the moment. 344c4d1fb62Seric miao */ 345c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 346c4d1fb62Seric miao { 347c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 348c4d1fb62Seric miao unsigned long saved_data = *p; 349c4d1fb62Seric miao 350c4d1fb62Seric miao extern void pxa3xx_cpu_suspend(void); 351c4d1fb62Seric miao extern void pxa3xx_cpu_resume(void); 352c4d1fb62Seric miao 353c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 354c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 355c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 356c4d1fb62Seric miao 357c4d1fb62Seric miao /* clear and setup wakeup source */ 358c4d1fb62Seric miao AD3SR = ~0; 359c4d1fb62Seric miao AD3ER = wakeup_src; 360c4d1fb62Seric miao ASCR = ASCR; 361c4d1fb62Seric miao ARSR = ARSR; 362c4d1fb62Seric miao 363c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 364c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 365c4d1fb62Seric miao 366c4d1fb62Seric miao PSPR = 0x5c014000; 367c4d1fb62Seric miao 368c4d1fb62Seric miao /* overwrite with the resume address */ 369c4d1fb62Seric miao *p = virt_to_phys(pxa3xx_cpu_resume); 370c4d1fb62Seric miao 371c4d1fb62Seric miao pxa3xx_cpu_suspend(); 372c4d1fb62Seric miao 373c4d1fb62Seric miao *p = saved_data; 374c4d1fb62Seric miao 375c4d1fb62Seric miao AD3ER = 0; 376c4d1fb62Seric miao } 377c4d1fb62Seric miao 3787b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 3797b5dea12SRussell King { 3807b5dea12SRussell King /* 3817b5dea12SRussell King * Don't sleep if no wakeup sources are defined 3827b5dea12SRussell King */ 383b86a5da8SMark Brown if (wakeup_src == 0) { 384b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 3857b5dea12SRussell King return; 386b86a5da8SMark Brown } 3877b5dea12SRussell King 3887b5dea12SRussell King switch (state) { 3897b5dea12SRussell King case PM_SUSPEND_STANDBY: 3907b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 3917b5dea12SRussell King break; 3927b5dea12SRussell King 3937b5dea12SRussell King case PM_SUSPEND_MEM: 394c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 3957b5dea12SRussell King break; 3967b5dea12SRussell King } 3977b5dea12SRussell King } 3987b5dea12SRussell King 3997b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 4007b5dea12SRussell King { 4017b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 4027b5dea12SRussell King } 4037b5dea12SRussell King 4047b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 405649de51bSRobert Jarzmik .save_count = SLEEP_SAVE_COUNT, 4067b5dea12SRussell King .save = pxa3xx_cpu_pm_save, 4077b5dea12SRussell King .restore = pxa3xx_cpu_pm_restore, 4087b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 4097b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 4107b5dea12SRussell King }; 4117b5dea12SRussell King 4127b5dea12SRussell King static void __init pxa3xx_init_pm(void) 4137b5dea12SRussell King { 4147b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 4157b5dea12SRussell King if (!sram) { 4167b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 4177b5dea12SRussell King return; 4187b5dea12SRussell King } 4197b5dea12SRussell King 4207b5dea12SRussell King /* 4217b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 4227b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 4237b5dea12SRussell King * is undocumented in the developer manual, but must be set. 4247b5dea12SRussell King */ 4257b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 4267b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 4277b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 4287b5dea12SRussell King 4297b5dea12SRussell King /* 4307b5dea12SRussell King * Clear the resume enable registers. 4317b5dea12SRussell King */ 4327b5dea12SRussell King AD1D0ER = 0; 4337b5dea12SRussell King AD2D0ER = 0; 4347b5dea12SRussell King AD2D1ER = 0; 4357b5dea12SRussell King AD3ER = 0; 4367b5dea12SRussell King 4377b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 4387b5dea12SRussell King } 4397b5dea12SRussell King 4407b5dea12SRussell King static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 4417b5dea12SRussell King { 4427b5dea12SRussell King unsigned long flags, mask = 0; 4437b5dea12SRussell King 4447b5dea12SRussell King switch (irq) { 4457b5dea12SRussell King case IRQ_SSP3: 4467b5dea12SRussell King mask = ADXER_MFP_WSSP3; 4477b5dea12SRussell King break; 4487b5dea12SRussell King case IRQ_MSL: 4497b5dea12SRussell King mask = ADXER_WMSL0; 4507b5dea12SRussell King break; 4517b5dea12SRussell King case IRQ_USBH2: 4527b5dea12SRussell King case IRQ_USBH1: 4537b5dea12SRussell King mask = ADXER_WUSBH; 4547b5dea12SRussell King break; 4557b5dea12SRussell King case IRQ_KEYPAD: 4567b5dea12SRussell King mask = ADXER_WKP; 4577b5dea12SRussell King break; 4587b5dea12SRussell King case IRQ_AC97: 4597b5dea12SRussell King mask = ADXER_MFP_WAC97; 4607b5dea12SRussell King break; 4617b5dea12SRussell King case IRQ_USIM: 4627b5dea12SRussell King mask = ADXER_WUSIM0; 4637b5dea12SRussell King break; 4647b5dea12SRussell King case IRQ_SSP2: 4657b5dea12SRussell King mask = ADXER_MFP_WSSP2; 4667b5dea12SRussell King break; 4677b5dea12SRussell King case IRQ_I2C: 4687b5dea12SRussell King mask = ADXER_MFP_WI2C; 4697b5dea12SRussell King break; 4707b5dea12SRussell King case IRQ_STUART: 4717b5dea12SRussell King mask = ADXER_MFP_WUART3; 4727b5dea12SRussell King break; 4737b5dea12SRussell King case IRQ_BTUART: 4747b5dea12SRussell King mask = ADXER_MFP_WUART2; 4757b5dea12SRussell King break; 4767b5dea12SRussell King case IRQ_FFUART: 4777b5dea12SRussell King mask = ADXER_MFP_WUART1; 4787b5dea12SRussell King break; 4797b5dea12SRussell King case IRQ_MMC: 4807b5dea12SRussell King mask = ADXER_MFP_WMMC1; 4817b5dea12SRussell King break; 4827b5dea12SRussell King case IRQ_SSP: 4837b5dea12SRussell King mask = ADXER_MFP_WSSP1; 4847b5dea12SRussell King break; 4857b5dea12SRussell King case IRQ_RTCAlrm: 4867b5dea12SRussell King mask = ADXER_WRTC; 4877b5dea12SRussell King break; 4887b5dea12SRussell King case IRQ_SSP4: 4897b5dea12SRussell King mask = ADXER_MFP_WSSP4; 4907b5dea12SRussell King break; 4917b5dea12SRussell King case IRQ_TSI: 4927b5dea12SRussell King mask = ADXER_WTSI; 4937b5dea12SRussell King break; 4947b5dea12SRussell King case IRQ_USIM2: 4957b5dea12SRussell King mask = ADXER_WUSIM1; 4967b5dea12SRussell King break; 4977b5dea12SRussell King case IRQ_MMC2: 4987b5dea12SRussell King mask = ADXER_MFP_WMMC2; 4997b5dea12SRussell King break; 5007b5dea12SRussell King case IRQ_NAND: 5017b5dea12SRussell King mask = ADXER_MFP_WFLASH; 5027b5dea12SRussell King break; 5037b5dea12SRussell King case IRQ_USB2: 5047b5dea12SRussell King mask = ADXER_WUSB2; 5057b5dea12SRussell King break; 5067b5dea12SRussell King case IRQ_WAKEUP0: 5077b5dea12SRussell King mask = ADXER_WEXTWAKE0; 5087b5dea12SRussell King break; 5097b5dea12SRussell King case IRQ_WAKEUP1: 5107b5dea12SRussell King mask = ADXER_WEXTWAKE1; 5117b5dea12SRussell King break; 5127b5dea12SRussell King case IRQ_MMC3: 5137b5dea12SRussell King mask = ADXER_MFP_GEN12; 5147b5dea12SRussell King break; 515e1217707SMark Brown default: 516e1217707SMark Brown return -EINVAL; 5177b5dea12SRussell King } 5187b5dea12SRussell King 5197b5dea12SRussell King local_irq_save(flags); 5207b5dea12SRussell King if (on) 5217b5dea12SRussell King wakeup_src |= mask; 5227b5dea12SRussell King else 5237b5dea12SRussell King wakeup_src &= ~mask; 5247b5dea12SRussell King local_irq_restore(flags); 5257b5dea12SRussell King 5267b5dea12SRussell King return 0; 5277b5dea12SRussell King } 5287b5dea12SRussell King #else 5297b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 530b9e25aceSeric miao #define pxa3xx_set_wake NULL 5317b5dea12SRussell King #endif 5327b5dea12SRussell King 5332c8086a5Seric miao void __init pxa3xx_init_irq(void) 5342c8086a5Seric miao { 5352c8086a5Seric miao /* enable CP6 access */ 5362c8086a5Seric miao u32 value; 5372c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 5382c8086a5Seric miao value |= (1 << 6); 5392c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 5402c8086a5Seric miao 541b9e25aceSeric miao pxa_init_irq(56, pxa3xx_set_wake); 542a58fbcd8SEric Miao pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 5432c8086a5Seric miao } 5442c8086a5Seric miao 5452c8086a5Seric miao /* 5462c8086a5Seric miao * device registration specific to PXA3xx. 5472c8086a5Seric miao */ 5482c8086a5Seric miao 5499ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 5509ba63c4fSMike Rapoport { 55114758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 5529ba63c4fSMike Rapoport } 5539ba63c4fSMike Rapoport 5542c8086a5Seric miao static struct platform_device *devices[] __initdata = { 555284d115eSRussell King /* &pxa_device_udc, The UDC driver is PXA25x only */ 5562c8086a5Seric miao &pxa_device_ffuart, 5572c8086a5Seric miao &pxa_device_btuart, 5582c8086a5Seric miao &pxa_device_stuart, 5592c8086a5Seric miao &pxa_device_i2s, 56072493146SRobert Jarzmik &sa1100_device_rtc, 5612c8086a5Seric miao &pxa_device_rtc, 562d8e0db11Seric miao &pxa27x_device_ssp1, 563d8e0db11Seric miao &pxa27x_device_ssp2, 564d8e0db11Seric miao &pxa27x_device_ssp3, 565d8e0db11Seric miao &pxa3xx_device_ssp4, 56675540c1aSeric miao &pxa27x_device_pwm0, 56775540c1aSeric miao &pxa27x_device_pwm1, 5682c8086a5Seric miao }; 5692c8086a5Seric miao 570c0165504Seric miao static struct sys_device pxa3xx_sysdev[] = { 571c0165504Seric miao { 572c0165504Seric miao .cls = &pxa_irq_sysclass, 57316dfdbf0Seric miao }, { 5744be35e23Seric miao .cls = &pxa3xx_mfp_sysclass, 5754be35e23Seric miao }, { 57616dfdbf0Seric miao .cls = &pxa_gpio_sysclass, 577c0165504Seric miao }, 578c0165504Seric miao }; 579c0165504Seric miao 5802c8086a5Seric miao static int __init pxa3xx_init(void) 5812c8086a5Seric miao { 582c0165504Seric miao int i, ret = 0; 5832c8086a5Seric miao 5842c8086a5Seric miao if (cpu_is_pxa3xx()) { 58504fef228SEric Miao 58604fef228SEric Miao reset_status = ARSR; 58704fef228SEric Miao 58886260f98SDmitry Krivoschekov /* 58986260f98SDmitry Krivoschekov * clear RDH bit every time after reset 59086260f98SDmitry Krivoschekov * 59186260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 59286260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 59386260f98SDmitry Krivoschekov */ 59486260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 59586260f98SDmitry Krivoschekov 5968c3abc7dSRussell King clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 5972c8086a5Seric miao 598fef1f99aSEric Miao if ((ret = pxa_init_dma(IRQ_DMA, 32))) 5992c8086a5Seric miao return ret; 6002c8086a5Seric miao 6017b5dea12SRussell King pxa3xx_init_pm(); 6027b5dea12SRussell King 603c0165504Seric miao for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 604c0165504Seric miao ret = sysdev_register(&pxa3xx_sysdev[i]); 605c0165504Seric miao if (ret) 606c0165504Seric miao pr_err("failed to register sysdev[%d]\n", i); 6072c8086a5Seric miao } 608c0165504Seric miao 609c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 610c0165504Seric miao } 611c0165504Seric miao 612c0165504Seric miao return ret; 6132c8086a5Seric miao } 6142c8086a5Seric miao 6151c104e0eSRussell King postcore_initcall(pxa3xx_init); 616