12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao 162c8086a5Seric miao #include <linux/module.h> 172c8086a5Seric miao #include <linux/kernel.h> 182c8086a5Seric miao #include <linux/init.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 227b5dea12SRussell King #include <linux/io.h> 23c0165504Seric miao #include <linux/sysdev.h> 242c8086a5Seric miao 25a09e64fbSRussell King #include <mach/hardware.h> 26a58fbcd8SEric Miao #include <mach/gpio.h> 27a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 28afd2fc02SRussell King #include <mach/reset.h> 29a09e64fbSRussell King #include <mach/ohci.h> 30a09e64fbSRussell King #include <mach/pm.h> 31a09e64fbSRussell King #include <mach/dma.h> 32a09e64fbSRussell King #include <mach/ssp.h> 33bf293aecSMike Rapoport #include <mach/regs-intc.h> 34f0a83701SEric Miao #include <plat/i2c.h> 352c8086a5Seric miao 362c8086a5Seric miao #include "generic.h" 372c8086a5Seric miao #include "devices.h" 382c8086a5Seric miao #include "clock.h" 392c8086a5Seric miao 402c8086a5Seric miao /* Crystal clock: 13MHz */ 412c8086a5Seric miao #define BASE_CLK 13000000 422c8086a5Seric miao 432c8086a5Seric miao /* Ring Oscillator Clock: 60MHz */ 442c8086a5Seric miao #define RO_CLK 60000000 452c8086a5Seric miao 462c8086a5Seric miao #define ACCR_D0CS (1 << 26) 47c4d1fb62Seric miao #define ACCR_PCCE (1 << 11) 482c8086a5Seric miao 49bf293aecSMike Rapoport #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 50bf293aecSMike Rapoport #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 51bf293aecSMike Rapoport 522c8086a5Seric miao /* crystal frequency to static memory controller multiplier (SMCFS) */ 532c8086a5Seric miao static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 542c8086a5Seric miao 552c8086a5Seric miao /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 562c8086a5Seric miao static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 572c8086a5Seric miao 582c8086a5Seric miao /* 592c8086a5Seric miao * Get the clock frequency as reflected by CCSR and the turbo flag. 602c8086a5Seric miao * We assume these values have been applied via a fcs. 612c8086a5Seric miao * If info is not 0 we also display the current settings. 622c8086a5Seric miao */ 632c8086a5Seric miao unsigned int pxa3xx_get_clk_frequency_khz(int info) 642c8086a5Seric miao { 652c8086a5Seric miao unsigned long acsr, xclkcfg; 662c8086a5Seric miao unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 672c8086a5Seric miao 682c8086a5Seric miao /* Read XCLKCFG register turbo bit */ 692c8086a5Seric miao __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 702c8086a5Seric miao t = xclkcfg & 0x1; 712c8086a5Seric miao 722c8086a5Seric miao acsr = ACSR; 732c8086a5Seric miao 742c8086a5Seric miao xl = acsr & 0x1f; 752c8086a5Seric miao xn = (acsr >> 8) & 0x7; 762c8086a5Seric miao hss = (acsr >> 14) & 0x3; 772c8086a5Seric miao 782c8086a5Seric miao XL = xl * BASE_CLK; 792c8086a5Seric miao XN = xn * XL; 802c8086a5Seric miao 812c8086a5Seric miao ro = acsr & ACCR_D0CS; 822c8086a5Seric miao 832c8086a5Seric miao CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 842c8086a5Seric miao HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 852c8086a5Seric miao 862c8086a5Seric miao if (info) { 872c8086a5Seric miao pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 882c8086a5Seric miao RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 892c8086a5Seric miao (ro) ? "" : "in"); 902c8086a5Seric miao pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 912c8086a5Seric miao XL / 1000000, (XL % 1000000) / 10000, xl); 922c8086a5Seric miao pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 932c8086a5Seric miao XN / 1000000, (XN % 1000000) / 10000, xn, 942c8086a5Seric miao (t) ? "" : "in"); 952c8086a5Seric miao pr_info("HSIO bus clock: %d.%02dMHz\n", 962c8086a5Seric miao HSS / 1000000, (HSS % 1000000) / 10000); 972c8086a5Seric miao } 982c8086a5Seric miao 996232be32Seric miao return CLK / 1000; 1002c8086a5Seric miao } 1012c8086a5Seric miao 1022c8086a5Seric miao /* 1032c8086a5Seric miao * Return the current static memory controller clock frequency 1042c8086a5Seric miao * in units of 10kHz 1052c8086a5Seric miao */ 1062c8086a5Seric miao unsigned int pxa3xx_get_memclk_frequency_10khz(void) 1072c8086a5Seric miao { 1082c8086a5Seric miao unsigned long acsr; 1092c8086a5Seric miao unsigned int smcfs, clk = 0; 1102c8086a5Seric miao 1112c8086a5Seric miao acsr = ACSR; 1122c8086a5Seric miao 1132c8086a5Seric miao smcfs = (acsr >> 23) & 0x7; 1142c8086a5Seric miao clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 1152c8086a5Seric miao 1162c8086a5Seric miao return (clk / 10000); 1172c8086a5Seric miao } 1182c8086a5Seric miao 11904fef228SEric Miao void pxa3xx_clear_reset_status(unsigned int mask) 12004fef228SEric Miao { 12104fef228SEric Miao /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 12204fef228SEric Miao ARSR = mask; 12304fef228SEric Miao } 12404fef228SEric Miao 1252c8086a5Seric miao /* 12660bfe7faSMark Brown * Return the current AC97 clock frequency. 12760bfe7faSMark Brown */ 12860bfe7faSMark Brown static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 12960bfe7faSMark Brown { 13060bfe7faSMark Brown unsigned long rate = 312000000; 13160bfe7faSMark Brown unsigned long ac97_div; 13260bfe7faSMark Brown 13360bfe7faSMark Brown ac97_div = AC97_DIV; 13460bfe7faSMark Brown 13560bfe7faSMark Brown /* This may loose precision for some rates but won't for the 13660bfe7faSMark Brown * standard 24.576MHz. 13760bfe7faSMark Brown */ 13860bfe7faSMark Brown rate /= (ac97_div >> 12) & 0x7fff; 13960bfe7faSMark Brown rate *= (ac97_div & 0xfff); 14060bfe7faSMark Brown 14160bfe7faSMark Brown return rate; 14260bfe7faSMark Brown } 14360bfe7faSMark Brown 14460bfe7faSMark Brown /* 1452c8086a5Seric miao * Return the current HSIO bus clock frequency 1462c8086a5Seric miao */ 1472c8086a5Seric miao static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 1482c8086a5Seric miao { 1492c8086a5Seric miao unsigned long acsr; 1502c8086a5Seric miao unsigned int hss, hsio_clk; 1512c8086a5Seric miao 1522c8086a5Seric miao acsr = ACSR; 1532c8086a5Seric miao 1542c8086a5Seric miao hss = (acsr >> 14) & 0x3; 1552c8086a5Seric miao hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 1562c8086a5Seric miao 1572c8086a5Seric miao return hsio_clk; 1582c8086a5Seric miao } 1592c8086a5Seric miao 1607a2c5cb0Seric miao void clk_pxa3xx_cken_enable(struct clk *clk) 1612c8086a5Seric miao { 1622c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1632c8086a5Seric miao 1642c8086a5Seric miao if (clk->cken < 32) 1652c8086a5Seric miao CKENA |= mask; 1662c8086a5Seric miao else 1672c8086a5Seric miao CKENB |= mask; 1682c8086a5Seric miao } 1692c8086a5Seric miao 1707a2c5cb0Seric miao void clk_pxa3xx_cken_disable(struct clk *clk) 1712c8086a5Seric miao { 1722c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1732c8086a5Seric miao 1742c8086a5Seric miao if (clk->cken < 32) 1752c8086a5Seric miao CKENA &= ~mask; 1762c8086a5Seric miao else 1772c8086a5Seric miao CKENB &= ~mask; 1782c8086a5Seric miao } 1792c8086a5Seric miao 1807a2c5cb0Seric miao const struct clkops clk_pxa3xx_cken_ops = { 1812a0d7187Seric miao .enable = clk_pxa3xx_cken_enable, 1822a0d7187Seric miao .disable = clk_pxa3xx_cken_disable, 1832a0d7187Seric miao }; 1842a0d7187Seric miao 1852c8086a5Seric miao static const struct clkops clk_pxa3xx_hsio_ops = { 1862c8086a5Seric miao .enable = clk_pxa3xx_cken_enable, 1872c8086a5Seric miao .disable = clk_pxa3xx_cken_disable, 1882c8086a5Seric miao .getrate = clk_pxa3xx_hsio_getrate, 1892c8086a5Seric miao }; 1902c8086a5Seric miao 19160bfe7faSMark Brown static const struct clkops clk_pxa3xx_ac97_ops = { 19260bfe7faSMark Brown .enable = clk_pxa3xx_cken_enable, 19360bfe7faSMark Brown .disable = clk_pxa3xx_cken_disable, 19460bfe7faSMark Brown .getrate = clk_pxa3xx_ac97_getrate, 19560bfe7faSMark Brown }; 19660bfe7faSMark Brown 197dcc88a17SMark Brown static void clk_pout_enable(struct clk *clk) 198dcc88a17SMark Brown { 199dcc88a17SMark Brown OSCC |= OSCC_PEN; 200dcc88a17SMark Brown } 201dcc88a17SMark Brown 202dcc88a17SMark Brown static void clk_pout_disable(struct clk *clk) 203dcc88a17SMark Brown { 204dcc88a17SMark Brown OSCC &= ~OSCC_PEN; 205dcc88a17SMark Brown } 206dcc88a17SMark Brown 207dcc88a17SMark Brown static const struct clkops clk_pout_ops = { 208dcc88a17SMark Brown .enable = clk_pout_enable, 209dcc88a17SMark Brown .disable = clk_pout_disable, 210dcc88a17SMark Brown }; 211dcc88a17SMark Brown 2129ba63c4fSMike Rapoport static void clk_dummy_enable(struct clk *clk) 2139ba63c4fSMike Rapoport { 2149ba63c4fSMike Rapoport } 2159ba63c4fSMike Rapoport 2169ba63c4fSMike Rapoport static void clk_dummy_disable(struct clk *clk) 2179ba63c4fSMike Rapoport { 2189ba63c4fSMike Rapoport } 2199ba63c4fSMike Rapoport 2209ba63c4fSMike Rapoport static const struct clkops clk_dummy_ops = { 2219ba63c4fSMike Rapoport .enable = clk_dummy_enable, 2229ba63c4fSMike Rapoport .disable = clk_dummy_disable, 2239ba63c4fSMike Rapoport }; 2249ba63c4fSMike Rapoport 2258c3abc7dSRussell King static struct clk clk_pxa3xx_pout = { 226dcc88a17SMark Brown .ops = &clk_pout_ops, 227dcc88a17SMark Brown .rate = 13000000, 228dcc88a17SMark Brown .delay = 70, 2298c3abc7dSRussell King }; 230dcc88a17SMark Brown 2318c3abc7dSRussell King static struct clk clk_dummy = { 2329ba63c4fSMike Rapoport .ops = &clk_dummy_ops, 2338c3abc7dSRussell King }; 2349ba63c4fSMike Rapoport 2358c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 2368c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 2378c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 2388c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 2398c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 2408c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 2418c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 2428c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 2438c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 244e68750aeSIgor Grinberg static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 2458c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 2468c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 2478c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 2488c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 2498c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 2508c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 2518c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 2528c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 2538c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 2542c8086a5Seric miao 2558c3abc7dSRussell King static struct clk_lookup pxa3xx_clkregs[] = { 2568c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 2578c3abc7dSRussell King /* Power I2C clock is always on */ 2585c68b099SDaniel Mack INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 2598c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 2608c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 2618c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 2628c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 2638c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 2648c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 2658c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 2668c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 2678c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 2688c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 269e68750aeSIgor Grinberg INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"), 2708c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 2718c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 2728c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 2738c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 2748c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 2758c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 2768c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 2778c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 2788c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 2792c8086a5Seric miao }; 2802c8086a5Seric miao 2817b5dea12SRussell King #ifdef CONFIG_PM 2827b5dea12SRussell King 2837b5dea12SRussell King #define ISRAM_START 0x5c000000 2847b5dea12SRussell King #define ISRAM_SIZE SZ_256K 2857b5dea12SRussell King 2867b5dea12SRussell King static void __iomem *sram; 2877b5dea12SRussell King static unsigned long wakeup_src; 2887b5dea12SRussell King 289c4d1fb62Seric miao #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 290c4d1fb62Seric miao #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 291c4d1fb62Seric miao 292649de51bSRobert Jarzmik enum { SLEEP_SAVE_CKENA, 293c4d1fb62Seric miao SLEEP_SAVE_CKENB, 294c4d1fb62Seric miao SLEEP_SAVE_ACCR, 295c4d1fb62Seric miao 296649de51bSRobert Jarzmik SLEEP_SAVE_COUNT, 297c4d1fb62Seric miao }; 298c4d1fb62Seric miao 2997b5dea12SRussell King static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 3007b5dea12SRussell King { 301c4d1fb62Seric miao SAVE(CKENA); 302c4d1fb62Seric miao SAVE(CKENB); 303c4d1fb62Seric miao SAVE(ACCR); 3047b5dea12SRussell King } 3057b5dea12SRussell King 3067b5dea12SRussell King static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 3077b5dea12SRussell King { 308c4d1fb62Seric miao RESTORE(ACCR); 309c4d1fb62Seric miao RESTORE(CKENA); 310c4d1fb62Seric miao RESTORE(CKENB); 3117b5dea12SRussell King } 3127b5dea12SRussell King 3137b5dea12SRussell King /* 3147b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 3157b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 3167b5dea12SRussell King * in the SRAM to perform this function. 3177b5dea12SRussell King * 3187b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 3197b5dea12SRussell King * FIQ while the SDRAM is unavailable. 3207b5dea12SRussell King */ 3217b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 3227b5dea12SRussell King { 3237b5dea12SRussell King extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 3247b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 3257b5dea12SRussell King 3267b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 3277b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 3287b5dea12SRussell King 3297b5dea12SRussell King AD2D0SR = ~0; 3307b5dea12SRussell King AD2D1SR = ~0; 3317b5dea12SRussell King AD2D0ER = wakeup_src; 3327b5dea12SRussell King AD2D1ER = 0; 3337b5dea12SRussell King ASCR = ASCR; 3347b5dea12SRussell King ARSR = ARSR; 3357b5dea12SRussell King 3367b5dea12SRussell King local_fiq_disable(); 3377b5dea12SRussell King fn(pwrmode); 3387b5dea12SRussell King local_fiq_enable(); 3397b5dea12SRussell King 3407b5dea12SRussell King AD2D0ER = 0; 3417b5dea12SRussell King AD2D1ER = 0; 3427b5dea12SRussell King } 3437b5dea12SRussell King 344c4d1fb62Seric miao /* 345c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 346c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 347c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 348c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 349c4d1fb62Seric miao * 0x5c014000 for the moment. 350c4d1fb62Seric miao */ 351c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 352c4d1fb62Seric miao { 353c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 354c4d1fb62Seric miao unsigned long saved_data = *p; 355c4d1fb62Seric miao 356c4d1fb62Seric miao extern void pxa3xx_cpu_suspend(void); 357c4d1fb62Seric miao extern void pxa3xx_cpu_resume(void); 358c4d1fb62Seric miao 359c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 360c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 361c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 362c4d1fb62Seric miao 363c4d1fb62Seric miao /* clear and setup wakeup source */ 364c4d1fb62Seric miao AD3SR = ~0; 365c4d1fb62Seric miao AD3ER = wakeup_src; 366c4d1fb62Seric miao ASCR = ASCR; 367c4d1fb62Seric miao ARSR = ARSR; 368c4d1fb62Seric miao 369c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 370c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 371c4d1fb62Seric miao 372c4d1fb62Seric miao PSPR = 0x5c014000; 373c4d1fb62Seric miao 374c4d1fb62Seric miao /* overwrite with the resume address */ 375c4d1fb62Seric miao *p = virt_to_phys(pxa3xx_cpu_resume); 376c4d1fb62Seric miao 377c4d1fb62Seric miao pxa3xx_cpu_suspend(); 378c4d1fb62Seric miao 379c4d1fb62Seric miao *p = saved_data; 380c4d1fb62Seric miao 381c4d1fb62Seric miao AD3ER = 0; 382c4d1fb62Seric miao } 383c4d1fb62Seric miao 3847b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 3857b5dea12SRussell King { 3867b5dea12SRussell King /* 3877b5dea12SRussell King * Don't sleep if no wakeup sources are defined 3887b5dea12SRussell King */ 389b86a5da8SMark Brown if (wakeup_src == 0) { 390b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 3917b5dea12SRussell King return; 392b86a5da8SMark Brown } 3937b5dea12SRussell King 3947b5dea12SRussell King switch (state) { 3957b5dea12SRussell King case PM_SUSPEND_STANDBY: 3967b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 3977b5dea12SRussell King break; 3987b5dea12SRussell King 3997b5dea12SRussell King case PM_SUSPEND_MEM: 400c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 4017b5dea12SRussell King break; 4027b5dea12SRussell King } 4037b5dea12SRussell King } 4047b5dea12SRussell King 4057b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 4067b5dea12SRussell King { 4077b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 4087b5dea12SRussell King } 4097b5dea12SRussell King 4107b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 411649de51bSRobert Jarzmik .save_count = SLEEP_SAVE_COUNT, 4127b5dea12SRussell King .save = pxa3xx_cpu_pm_save, 4137b5dea12SRussell King .restore = pxa3xx_cpu_pm_restore, 4147b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 4157b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 4167b5dea12SRussell King }; 4177b5dea12SRussell King 4187b5dea12SRussell King static void __init pxa3xx_init_pm(void) 4197b5dea12SRussell King { 4207b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 4217b5dea12SRussell King if (!sram) { 4227b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 4237b5dea12SRussell King return; 4247b5dea12SRussell King } 4257b5dea12SRussell King 4267b5dea12SRussell King /* 4277b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 4287b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 4297b5dea12SRussell King * is undocumented in the developer manual, but must be set. 4307b5dea12SRussell King */ 4317b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 4327b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 4337b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 4347b5dea12SRussell King 4357b5dea12SRussell King /* 4367b5dea12SRussell King * Clear the resume enable registers. 4377b5dea12SRussell King */ 4387b5dea12SRussell King AD1D0ER = 0; 4397b5dea12SRussell King AD2D0ER = 0; 4407b5dea12SRussell King AD2D1ER = 0; 4417b5dea12SRussell King AD3ER = 0; 4427b5dea12SRussell King 4437b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 4447b5dea12SRussell King } 4457b5dea12SRussell King 4467b5dea12SRussell King static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 4477b5dea12SRussell King { 4487b5dea12SRussell King unsigned long flags, mask = 0; 4497b5dea12SRussell King 4507b5dea12SRussell King switch (irq) { 4517b5dea12SRussell King case IRQ_SSP3: 4527b5dea12SRussell King mask = ADXER_MFP_WSSP3; 4537b5dea12SRussell King break; 4547b5dea12SRussell King case IRQ_MSL: 4557b5dea12SRussell King mask = ADXER_WMSL0; 4567b5dea12SRussell King break; 4577b5dea12SRussell King case IRQ_USBH2: 4587b5dea12SRussell King case IRQ_USBH1: 4597b5dea12SRussell King mask = ADXER_WUSBH; 4607b5dea12SRussell King break; 4617b5dea12SRussell King case IRQ_KEYPAD: 4627b5dea12SRussell King mask = ADXER_WKP; 4637b5dea12SRussell King break; 4647b5dea12SRussell King case IRQ_AC97: 4657b5dea12SRussell King mask = ADXER_MFP_WAC97; 4667b5dea12SRussell King break; 4677b5dea12SRussell King case IRQ_USIM: 4687b5dea12SRussell King mask = ADXER_WUSIM0; 4697b5dea12SRussell King break; 4707b5dea12SRussell King case IRQ_SSP2: 4717b5dea12SRussell King mask = ADXER_MFP_WSSP2; 4727b5dea12SRussell King break; 4737b5dea12SRussell King case IRQ_I2C: 4747b5dea12SRussell King mask = ADXER_MFP_WI2C; 4757b5dea12SRussell King break; 4767b5dea12SRussell King case IRQ_STUART: 4777b5dea12SRussell King mask = ADXER_MFP_WUART3; 4787b5dea12SRussell King break; 4797b5dea12SRussell King case IRQ_BTUART: 4807b5dea12SRussell King mask = ADXER_MFP_WUART2; 4817b5dea12SRussell King break; 4827b5dea12SRussell King case IRQ_FFUART: 4837b5dea12SRussell King mask = ADXER_MFP_WUART1; 4847b5dea12SRussell King break; 4857b5dea12SRussell King case IRQ_MMC: 4867b5dea12SRussell King mask = ADXER_MFP_WMMC1; 4877b5dea12SRussell King break; 4887b5dea12SRussell King case IRQ_SSP: 4897b5dea12SRussell King mask = ADXER_MFP_WSSP1; 4907b5dea12SRussell King break; 4917b5dea12SRussell King case IRQ_RTCAlrm: 4927b5dea12SRussell King mask = ADXER_WRTC; 4937b5dea12SRussell King break; 4947b5dea12SRussell King case IRQ_SSP4: 4957b5dea12SRussell King mask = ADXER_MFP_WSSP4; 4967b5dea12SRussell King break; 4977b5dea12SRussell King case IRQ_TSI: 4987b5dea12SRussell King mask = ADXER_WTSI; 4997b5dea12SRussell King break; 5007b5dea12SRussell King case IRQ_USIM2: 5017b5dea12SRussell King mask = ADXER_WUSIM1; 5027b5dea12SRussell King break; 5037b5dea12SRussell King case IRQ_MMC2: 5047b5dea12SRussell King mask = ADXER_MFP_WMMC2; 5057b5dea12SRussell King break; 5067b5dea12SRussell King case IRQ_NAND: 5077b5dea12SRussell King mask = ADXER_MFP_WFLASH; 5087b5dea12SRussell King break; 5097b5dea12SRussell King case IRQ_USB2: 5107b5dea12SRussell King mask = ADXER_WUSB2; 5117b5dea12SRussell King break; 5127b5dea12SRussell King case IRQ_WAKEUP0: 5137b5dea12SRussell King mask = ADXER_WEXTWAKE0; 5147b5dea12SRussell King break; 5157b5dea12SRussell King case IRQ_WAKEUP1: 5167b5dea12SRussell King mask = ADXER_WEXTWAKE1; 5177b5dea12SRussell King break; 5187b5dea12SRussell King case IRQ_MMC3: 5197b5dea12SRussell King mask = ADXER_MFP_GEN12; 5207b5dea12SRussell King break; 521e1217707SMark Brown default: 522e1217707SMark Brown return -EINVAL; 5237b5dea12SRussell King } 5247b5dea12SRussell King 5257b5dea12SRussell King local_irq_save(flags); 5267b5dea12SRussell King if (on) 5277b5dea12SRussell King wakeup_src |= mask; 5287b5dea12SRussell King else 5297b5dea12SRussell King wakeup_src &= ~mask; 5307b5dea12SRussell King local_irq_restore(flags); 5317b5dea12SRussell King 5327b5dea12SRussell King return 0; 5337b5dea12SRussell King } 5347b5dea12SRussell King #else 5357b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 536b9e25aceSeric miao #define pxa3xx_set_wake NULL 5377b5dea12SRussell King #endif 5387b5dea12SRussell King 539bf293aecSMike Rapoport static void pxa_ack_ext_wakeup(unsigned int irq) 540bf293aecSMike Rapoport { 541bf293aecSMike Rapoport PECR |= PECR_IS(irq - IRQ_WAKEUP0); 542bf293aecSMike Rapoport } 543bf293aecSMike Rapoport 544bf293aecSMike Rapoport static void pxa_mask_ext_wakeup(unsigned int irq) 545bf293aecSMike Rapoport { 546bf293aecSMike Rapoport ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); 547bf293aecSMike Rapoport PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); 548bf293aecSMike Rapoport } 549bf293aecSMike Rapoport 550bf293aecSMike Rapoport static void pxa_unmask_ext_wakeup(unsigned int irq) 551bf293aecSMike Rapoport { 552bf293aecSMike Rapoport ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); 553bf293aecSMike Rapoport PECR |= PECR_IE(irq - IRQ_WAKEUP0); 554bf293aecSMike Rapoport } 555bf293aecSMike Rapoport 556bf293aecSMike Rapoport static struct irq_chip pxa_ext_wakeup_chip = { 557bf293aecSMike Rapoport .name = "WAKEUP", 558bf293aecSMike Rapoport .ack = pxa_ack_ext_wakeup, 559bf293aecSMike Rapoport .mask = pxa_mask_ext_wakeup, 560bf293aecSMike Rapoport .unmask = pxa_unmask_ext_wakeup, 561bf293aecSMike Rapoport }; 562bf293aecSMike Rapoport 563bf293aecSMike Rapoport static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 564bf293aecSMike Rapoport { 565bf293aecSMike Rapoport int irq; 566bf293aecSMike Rapoport 567bf293aecSMike Rapoport for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 568bf293aecSMike Rapoport set_irq_chip(irq, &pxa_ext_wakeup_chip); 569bf293aecSMike Rapoport set_irq_handler(irq, handle_edge_irq); 570bf293aecSMike Rapoport set_irq_flags(irq, IRQF_VALID); 571bf293aecSMike Rapoport } 572bf293aecSMike Rapoport 573bf293aecSMike Rapoport pxa_ext_wakeup_chip.set_wake = fn; 574bf293aecSMike Rapoport } 575bf293aecSMike Rapoport 5762c8086a5Seric miao void __init pxa3xx_init_irq(void) 5772c8086a5Seric miao { 5782c8086a5Seric miao /* enable CP6 access */ 5792c8086a5Seric miao u32 value; 5802c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 5812c8086a5Seric miao value |= (1 << 6); 5822c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 5832c8086a5Seric miao 584b9e25aceSeric miao pxa_init_irq(56, pxa3xx_set_wake); 585bf293aecSMike Rapoport pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 586a58fbcd8SEric Miao pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 5872c8086a5Seric miao } 5882c8086a5Seric miao 5892c8086a5Seric miao /* 5902c8086a5Seric miao * device registration specific to PXA3xx. 5912c8086a5Seric miao */ 5922c8086a5Seric miao 5939ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 5949ba63c4fSMike Rapoport { 59514758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 5969ba63c4fSMike Rapoport } 5979ba63c4fSMike Rapoport 5982c8086a5Seric miao static struct platform_device *devices[] __initdata = { 59994c35a6bSRobert Jarzmik &pxa27x_device_udc, 6002c8086a5Seric miao &pxa_device_i2s, 60172493146SRobert Jarzmik &sa1100_device_rtc, 6022c8086a5Seric miao &pxa_device_rtc, 603d8e0db11Seric miao &pxa27x_device_ssp1, 604d8e0db11Seric miao &pxa27x_device_ssp2, 605d8e0db11Seric miao &pxa27x_device_ssp3, 606d8e0db11Seric miao &pxa3xx_device_ssp4, 60775540c1aSeric miao &pxa27x_device_pwm0, 60875540c1aSeric miao &pxa27x_device_pwm1, 6092c8086a5Seric miao }; 6102c8086a5Seric miao 611c0165504Seric miao static struct sys_device pxa3xx_sysdev[] = { 612c0165504Seric miao { 613c0165504Seric miao .cls = &pxa_irq_sysclass, 61416dfdbf0Seric miao }, { 6154be35e23Seric miao .cls = &pxa3xx_mfp_sysclass, 6164be35e23Seric miao }, { 61716dfdbf0Seric miao .cls = &pxa_gpio_sysclass, 618c0165504Seric miao }, 619c0165504Seric miao }; 620c0165504Seric miao 6212c8086a5Seric miao static int __init pxa3xx_init(void) 6222c8086a5Seric miao { 623c0165504Seric miao int i, ret = 0; 6242c8086a5Seric miao 6252c8086a5Seric miao if (cpu_is_pxa3xx()) { 62604fef228SEric Miao 62704fef228SEric Miao reset_status = ARSR; 62804fef228SEric Miao 62986260f98SDmitry Krivoschekov /* 63086260f98SDmitry Krivoschekov * clear RDH bit every time after reset 63186260f98SDmitry Krivoschekov * 63286260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 63386260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 63486260f98SDmitry Krivoschekov */ 63586260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 63686260f98SDmitry Krivoschekov 6378c3abc7dSRussell King clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 6382c8086a5Seric miao 639fef1f99aSEric Miao if ((ret = pxa_init_dma(IRQ_DMA, 32))) 6402c8086a5Seric miao return ret; 6412c8086a5Seric miao 6427b5dea12SRussell King pxa3xx_init_pm(); 6437b5dea12SRussell King 644c0165504Seric miao for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 645c0165504Seric miao ret = sysdev_register(&pxa3xx_sysdev[i]); 646c0165504Seric miao if (ret) 647c0165504Seric miao pr_err("failed to register sysdev[%d]\n", i); 6482c8086a5Seric miao } 649c0165504Seric miao 650c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 651c0165504Seric miao } 652c0165504Seric miao 653c0165504Seric miao return ret; 6542c8086a5Seric miao } 6552c8086a5Seric miao 6561c104e0eSRussell King postcore_initcall(pxa3xx_init); 657