12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao 162c8086a5Seric miao #include <linux/module.h> 172c8086a5Seric miao #include <linux/kernel.h> 182c8086a5Seric miao #include <linux/init.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 227b5dea12SRussell King #include <linux/io.h> 23c0165504Seric miao #include <linux/sysdev.h> 242c8086a5Seric miao 25851982c1SMarek Vasut #include <asm/mach/map.h> 26a09e64fbSRussell King #include <mach/hardware.h> 27a58fbcd8SEric Miao #include <mach/gpio.h> 28a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 29afd2fc02SRussell King #include <mach/reset.h> 30a09e64fbSRussell King #include <mach/ohci.h> 31a09e64fbSRussell King #include <mach/pm.h> 32a09e64fbSRussell King #include <mach/dma.h> 33bf293aecSMike Rapoport #include <mach/regs-intc.h> 34ad68bb9fSMarek Vasut #include <mach/smemc.h> 35f0a83701SEric Miao #include <plat/i2c.h> 362c8086a5Seric miao 372c8086a5Seric miao #include "generic.h" 382c8086a5Seric miao #include "devices.h" 392c8086a5Seric miao #include "clock.h" 402c8086a5Seric miao 412c8086a5Seric miao /* Crystal clock: 13MHz */ 422c8086a5Seric miao #define BASE_CLK 13000000 432c8086a5Seric miao 442c8086a5Seric miao /* Ring Oscillator Clock: 60MHz */ 452c8086a5Seric miao #define RO_CLK 60000000 462c8086a5Seric miao 472c8086a5Seric miao #define ACCR_D0CS (1 << 26) 48c4d1fb62Seric miao #define ACCR_PCCE (1 << 11) 492c8086a5Seric miao 50bf293aecSMike Rapoport #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 51bf293aecSMike Rapoport #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 52bf293aecSMike Rapoport 532c8086a5Seric miao /* crystal frequency to static memory controller multiplier (SMCFS) */ 542c8086a5Seric miao static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 552c8086a5Seric miao 562c8086a5Seric miao /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 575852984aSMarek Vasut static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; 582c8086a5Seric miao 592c8086a5Seric miao /* 602c8086a5Seric miao * Get the clock frequency as reflected by CCSR and the turbo flag. 612c8086a5Seric miao * We assume these values have been applied via a fcs. 622c8086a5Seric miao * If info is not 0 we also display the current settings. 632c8086a5Seric miao */ 642c8086a5Seric miao unsigned int pxa3xx_get_clk_frequency_khz(int info) 652c8086a5Seric miao { 662c8086a5Seric miao unsigned long acsr, xclkcfg; 672c8086a5Seric miao unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 682c8086a5Seric miao 692c8086a5Seric miao /* Read XCLKCFG register turbo bit */ 702c8086a5Seric miao __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 712c8086a5Seric miao t = xclkcfg & 0x1; 722c8086a5Seric miao 732c8086a5Seric miao acsr = ACSR; 742c8086a5Seric miao 752c8086a5Seric miao xl = acsr & 0x1f; 762c8086a5Seric miao xn = (acsr >> 8) & 0x7; 772c8086a5Seric miao hss = (acsr >> 14) & 0x3; 782c8086a5Seric miao 792c8086a5Seric miao XL = xl * BASE_CLK; 802c8086a5Seric miao XN = xn * XL; 812c8086a5Seric miao 822c8086a5Seric miao ro = acsr & ACCR_D0CS; 832c8086a5Seric miao 842c8086a5Seric miao CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 852c8086a5Seric miao HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 862c8086a5Seric miao 872c8086a5Seric miao if (info) { 882c8086a5Seric miao pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 892c8086a5Seric miao RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 902c8086a5Seric miao (ro) ? "" : "in"); 912c8086a5Seric miao pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 922c8086a5Seric miao XL / 1000000, (XL % 1000000) / 10000, xl); 932c8086a5Seric miao pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 942c8086a5Seric miao XN / 1000000, (XN % 1000000) / 10000, xn, 952c8086a5Seric miao (t) ? "" : "in"); 962c8086a5Seric miao pr_info("HSIO bus clock: %d.%02dMHz\n", 972c8086a5Seric miao HSS / 1000000, (HSS % 1000000) / 10000); 982c8086a5Seric miao } 992c8086a5Seric miao 1006232be32Seric miao return CLK / 1000; 1012c8086a5Seric miao } 1022c8086a5Seric miao 10304fef228SEric Miao void pxa3xx_clear_reset_status(unsigned int mask) 10404fef228SEric Miao { 10504fef228SEric Miao /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 10604fef228SEric Miao ARSR = mask; 10704fef228SEric Miao } 10804fef228SEric Miao 1092c8086a5Seric miao /* 11060bfe7faSMark Brown * Return the current AC97 clock frequency. 11160bfe7faSMark Brown */ 11260bfe7faSMark Brown static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 11360bfe7faSMark Brown { 11460bfe7faSMark Brown unsigned long rate = 312000000; 11560bfe7faSMark Brown unsigned long ac97_div; 11660bfe7faSMark Brown 11760bfe7faSMark Brown ac97_div = AC97_DIV; 11860bfe7faSMark Brown 11960bfe7faSMark Brown /* This may loose precision for some rates but won't for the 12060bfe7faSMark Brown * standard 24.576MHz. 12160bfe7faSMark Brown */ 12260bfe7faSMark Brown rate /= (ac97_div >> 12) & 0x7fff; 12360bfe7faSMark Brown rate *= (ac97_div & 0xfff); 12460bfe7faSMark Brown 12560bfe7faSMark Brown return rate; 12660bfe7faSMark Brown } 12760bfe7faSMark Brown 12860bfe7faSMark Brown /* 1292c8086a5Seric miao * Return the current HSIO bus clock frequency 1302c8086a5Seric miao */ 1312c8086a5Seric miao static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 1322c8086a5Seric miao { 1332c8086a5Seric miao unsigned long acsr; 1342c8086a5Seric miao unsigned int hss, hsio_clk; 1352c8086a5Seric miao 1362c8086a5Seric miao acsr = ACSR; 1372c8086a5Seric miao 1382c8086a5Seric miao hss = (acsr >> 14) & 0x3; 1392c8086a5Seric miao hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 1402c8086a5Seric miao 1412c8086a5Seric miao return hsio_clk; 1422c8086a5Seric miao } 1432c8086a5Seric miao 1447a2c5cb0Seric miao void clk_pxa3xx_cken_enable(struct clk *clk) 1452c8086a5Seric miao { 1462c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1472c8086a5Seric miao 1482c8086a5Seric miao if (clk->cken < 32) 1492c8086a5Seric miao CKENA |= mask; 1502c8086a5Seric miao else 1512c8086a5Seric miao CKENB |= mask; 1522c8086a5Seric miao } 1532c8086a5Seric miao 1547a2c5cb0Seric miao void clk_pxa3xx_cken_disable(struct clk *clk) 1552c8086a5Seric miao { 1562c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1572c8086a5Seric miao 1582c8086a5Seric miao if (clk->cken < 32) 1592c8086a5Seric miao CKENA &= ~mask; 1602c8086a5Seric miao else 1612c8086a5Seric miao CKENB &= ~mask; 1622c8086a5Seric miao } 1632c8086a5Seric miao 1647a2c5cb0Seric miao const struct clkops clk_pxa3xx_cken_ops = { 1652a0d7187Seric miao .enable = clk_pxa3xx_cken_enable, 1662a0d7187Seric miao .disable = clk_pxa3xx_cken_disable, 1672a0d7187Seric miao }; 1682a0d7187Seric miao 1692c8086a5Seric miao static const struct clkops clk_pxa3xx_hsio_ops = { 1702c8086a5Seric miao .enable = clk_pxa3xx_cken_enable, 1712c8086a5Seric miao .disable = clk_pxa3xx_cken_disable, 1722c8086a5Seric miao .getrate = clk_pxa3xx_hsio_getrate, 1732c8086a5Seric miao }; 1742c8086a5Seric miao 17560bfe7faSMark Brown static const struct clkops clk_pxa3xx_ac97_ops = { 17660bfe7faSMark Brown .enable = clk_pxa3xx_cken_enable, 17760bfe7faSMark Brown .disable = clk_pxa3xx_cken_disable, 17860bfe7faSMark Brown .getrate = clk_pxa3xx_ac97_getrate, 17960bfe7faSMark Brown }; 18060bfe7faSMark Brown 181dcc88a17SMark Brown static void clk_pout_enable(struct clk *clk) 182dcc88a17SMark Brown { 183dcc88a17SMark Brown OSCC |= OSCC_PEN; 184dcc88a17SMark Brown } 185dcc88a17SMark Brown 186dcc88a17SMark Brown static void clk_pout_disable(struct clk *clk) 187dcc88a17SMark Brown { 188dcc88a17SMark Brown OSCC &= ~OSCC_PEN; 189dcc88a17SMark Brown } 190dcc88a17SMark Brown 191dcc88a17SMark Brown static const struct clkops clk_pout_ops = { 192dcc88a17SMark Brown .enable = clk_pout_enable, 193dcc88a17SMark Brown .disable = clk_pout_disable, 194dcc88a17SMark Brown }; 195dcc88a17SMark Brown 1969ba63c4fSMike Rapoport static void clk_dummy_enable(struct clk *clk) 1979ba63c4fSMike Rapoport { 1989ba63c4fSMike Rapoport } 1999ba63c4fSMike Rapoport 2009ba63c4fSMike Rapoport static void clk_dummy_disable(struct clk *clk) 2019ba63c4fSMike Rapoport { 2029ba63c4fSMike Rapoport } 2039ba63c4fSMike Rapoport 2049ba63c4fSMike Rapoport static const struct clkops clk_dummy_ops = { 2059ba63c4fSMike Rapoport .enable = clk_dummy_enable, 2069ba63c4fSMike Rapoport .disable = clk_dummy_disable, 2079ba63c4fSMike Rapoport }; 2089ba63c4fSMike Rapoport 2098c3abc7dSRussell King static struct clk clk_pxa3xx_pout = { 210dcc88a17SMark Brown .ops = &clk_pout_ops, 211dcc88a17SMark Brown .rate = 13000000, 212dcc88a17SMark Brown .delay = 70, 2138c3abc7dSRussell King }; 214dcc88a17SMark Brown 2158c3abc7dSRussell King static struct clk clk_dummy = { 2169ba63c4fSMike Rapoport .ops = &clk_dummy_ops, 2178c3abc7dSRussell King }; 2189ba63c4fSMike Rapoport 2198c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 2208c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 2218c3abc7dSRussell King static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 2228c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 2238c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 2248c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 2258c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 2268c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 2278c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 228e68750aeSIgor Grinberg static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 2298c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 2308c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 2318c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 2328c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 2338c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 2348c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 2358c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 2368c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 2378c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 2382c8086a5Seric miao 2398c3abc7dSRussell King static struct clk_lookup pxa3xx_clkregs[] = { 2408c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 2418c3abc7dSRussell King /* Power I2C clock is always on */ 2425c68b099SDaniel Mack INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 2438c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 2448c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 2458c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 2468c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 2478c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 2488c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 2498c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 2508c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 2518c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 2528c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 25369f22be7SIgor Grinberg INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 2548c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 2558c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 2568c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 2578c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 2588c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 2598c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 2608c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 2618c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 2628c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 2632c8086a5Seric miao }; 2642c8086a5Seric miao 2657b5dea12SRussell King #ifdef CONFIG_PM 2667b5dea12SRussell King 2677b5dea12SRussell King #define ISRAM_START 0x5c000000 2687b5dea12SRussell King #define ISRAM_SIZE SZ_256K 2697b5dea12SRussell King 2707b5dea12SRussell King static void __iomem *sram; 2717b5dea12SRussell King static unsigned long wakeup_src; 2727b5dea12SRussell King 273c4d1fb62Seric miao #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 274c4d1fb62Seric miao #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 275c4d1fb62Seric miao 276649de51bSRobert Jarzmik enum { SLEEP_SAVE_CKENA, 277c4d1fb62Seric miao SLEEP_SAVE_CKENB, 278c4d1fb62Seric miao SLEEP_SAVE_ACCR, 279c4d1fb62Seric miao 280649de51bSRobert Jarzmik SLEEP_SAVE_COUNT, 281c4d1fb62Seric miao }; 282c4d1fb62Seric miao 2837b5dea12SRussell King static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 2847b5dea12SRussell King { 285c4d1fb62Seric miao SAVE(CKENA); 286c4d1fb62Seric miao SAVE(CKENB); 287c4d1fb62Seric miao SAVE(ACCR); 2887b5dea12SRussell King } 2897b5dea12SRussell King 2907b5dea12SRussell King static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 2917b5dea12SRussell King { 292c4d1fb62Seric miao RESTORE(ACCR); 293c4d1fb62Seric miao RESTORE(CKENA); 294c4d1fb62Seric miao RESTORE(CKENB); 2957b5dea12SRussell King } 2967b5dea12SRussell King 2977b5dea12SRussell King /* 2987b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 2997b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 3007b5dea12SRussell King * in the SRAM to perform this function. 3017b5dea12SRussell King * 3027b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 3037b5dea12SRussell King * FIQ while the SDRAM is unavailable. 3047b5dea12SRussell King */ 3057b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 3067b5dea12SRussell King { 3077b5dea12SRussell King extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 3087b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 3097b5dea12SRussell King 3107b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 3117b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 3127b5dea12SRussell King 3137b5dea12SRussell King AD2D0SR = ~0; 3147b5dea12SRussell King AD2D1SR = ~0; 3157b5dea12SRussell King AD2D0ER = wakeup_src; 3167b5dea12SRussell King AD2D1ER = 0; 3177b5dea12SRussell King ASCR = ASCR; 3187b5dea12SRussell King ARSR = ARSR; 3197b5dea12SRussell King 3207b5dea12SRussell King local_fiq_disable(); 3217b5dea12SRussell King fn(pwrmode); 3227b5dea12SRussell King local_fiq_enable(); 3237b5dea12SRussell King 3247b5dea12SRussell King AD2D0ER = 0; 3257b5dea12SRussell King AD2D1ER = 0; 3267b5dea12SRussell King } 3277b5dea12SRussell King 328c4d1fb62Seric miao /* 329c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 330c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 331c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 332c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 333c4d1fb62Seric miao * 0x5c014000 for the moment. 334c4d1fb62Seric miao */ 335c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 336c4d1fb62Seric miao { 337c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 338c4d1fb62Seric miao unsigned long saved_data = *p; 339c4d1fb62Seric miao 340c4d1fb62Seric miao extern void pxa3xx_cpu_suspend(void); 341c4d1fb62Seric miao extern void pxa3xx_cpu_resume(void); 342c4d1fb62Seric miao 343c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 344c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 345c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 346c4d1fb62Seric miao 347c4d1fb62Seric miao /* clear and setup wakeup source */ 348c4d1fb62Seric miao AD3SR = ~0; 349c4d1fb62Seric miao AD3ER = wakeup_src; 350c4d1fb62Seric miao ASCR = ASCR; 351c4d1fb62Seric miao ARSR = ARSR; 352c4d1fb62Seric miao 353c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 354c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 355c4d1fb62Seric miao 356c4d1fb62Seric miao PSPR = 0x5c014000; 357c4d1fb62Seric miao 358c4d1fb62Seric miao /* overwrite with the resume address */ 359c4d1fb62Seric miao *p = virt_to_phys(pxa3xx_cpu_resume); 360c4d1fb62Seric miao 361c4d1fb62Seric miao pxa3xx_cpu_suspend(); 362c4d1fb62Seric miao 363c4d1fb62Seric miao *p = saved_data; 364c4d1fb62Seric miao 365c4d1fb62Seric miao AD3ER = 0; 366c4d1fb62Seric miao } 367c4d1fb62Seric miao 3687b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 3697b5dea12SRussell King { 3707b5dea12SRussell King /* 3717b5dea12SRussell King * Don't sleep if no wakeup sources are defined 3727b5dea12SRussell King */ 373b86a5da8SMark Brown if (wakeup_src == 0) { 374b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 3757b5dea12SRussell King return; 376b86a5da8SMark Brown } 3777b5dea12SRussell King 3787b5dea12SRussell King switch (state) { 3797b5dea12SRussell King case PM_SUSPEND_STANDBY: 3807b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 3817b5dea12SRussell King break; 3827b5dea12SRussell King 3837b5dea12SRussell King case PM_SUSPEND_MEM: 384c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 3857b5dea12SRussell King break; 3867b5dea12SRussell King } 3877b5dea12SRussell King } 3887b5dea12SRussell King 3897b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 3907b5dea12SRussell King { 3917b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 3927b5dea12SRussell King } 3937b5dea12SRussell King 3947b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 395649de51bSRobert Jarzmik .save_count = SLEEP_SAVE_COUNT, 3967b5dea12SRussell King .save = pxa3xx_cpu_pm_save, 3977b5dea12SRussell King .restore = pxa3xx_cpu_pm_restore, 3987b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 3997b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 4007b5dea12SRussell King }; 4017b5dea12SRussell King 4027b5dea12SRussell King static void __init pxa3xx_init_pm(void) 4037b5dea12SRussell King { 4047b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 4057b5dea12SRussell King if (!sram) { 4067b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 4077b5dea12SRussell King return; 4087b5dea12SRussell King } 4097b5dea12SRussell King 4107b5dea12SRussell King /* 4117b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 4127b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 4137b5dea12SRussell King * is undocumented in the developer manual, but must be set. 4147b5dea12SRussell King */ 4157b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 4167b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 4177b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 4187b5dea12SRussell King 4197b5dea12SRussell King /* 4207b5dea12SRussell King * Clear the resume enable registers. 4217b5dea12SRussell King */ 4227b5dea12SRussell King AD1D0ER = 0; 4237b5dea12SRussell King AD2D0ER = 0; 4247b5dea12SRussell King AD2D1ER = 0; 4257b5dea12SRussell King AD3ER = 0; 4267b5dea12SRussell King 4277b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 4287b5dea12SRussell King } 4297b5dea12SRussell King 4307b5dea12SRussell King static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 4317b5dea12SRussell King { 4327b5dea12SRussell King unsigned long flags, mask = 0; 4337b5dea12SRussell King 4347b5dea12SRussell King switch (irq) { 4357b5dea12SRussell King case IRQ_SSP3: 4367b5dea12SRussell King mask = ADXER_MFP_WSSP3; 4377b5dea12SRussell King break; 4387b5dea12SRussell King case IRQ_MSL: 4397b5dea12SRussell King mask = ADXER_WMSL0; 4407b5dea12SRussell King break; 4417b5dea12SRussell King case IRQ_USBH2: 4427b5dea12SRussell King case IRQ_USBH1: 4437b5dea12SRussell King mask = ADXER_WUSBH; 4447b5dea12SRussell King break; 4457b5dea12SRussell King case IRQ_KEYPAD: 4467b5dea12SRussell King mask = ADXER_WKP; 4477b5dea12SRussell King break; 4487b5dea12SRussell King case IRQ_AC97: 4497b5dea12SRussell King mask = ADXER_MFP_WAC97; 4507b5dea12SRussell King break; 4517b5dea12SRussell King case IRQ_USIM: 4527b5dea12SRussell King mask = ADXER_WUSIM0; 4537b5dea12SRussell King break; 4547b5dea12SRussell King case IRQ_SSP2: 4557b5dea12SRussell King mask = ADXER_MFP_WSSP2; 4567b5dea12SRussell King break; 4577b5dea12SRussell King case IRQ_I2C: 4587b5dea12SRussell King mask = ADXER_MFP_WI2C; 4597b5dea12SRussell King break; 4607b5dea12SRussell King case IRQ_STUART: 4617b5dea12SRussell King mask = ADXER_MFP_WUART3; 4627b5dea12SRussell King break; 4637b5dea12SRussell King case IRQ_BTUART: 4647b5dea12SRussell King mask = ADXER_MFP_WUART2; 4657b5dea12SRussell King break; 4667b5dea12SRussell King case IRQ_FFUART: 4677b5dea12SRussell King mask = ADXER_MFP_WUART1; 4687b5dea12SRussell King break; 4697b5dea12SRussell King case IRQ_MMC: 4707b5dea12SRussell King mask = ADXER_MFP_WMMC1; 4717b5dea12SRussell King break; 4727b5dea12SRussell King case IRQ_SSP: 4737b5dea12SRussell King mask = ADXER_MFP_WSSP1; 4747b5dea12SRussell King break; 4757b5dea12SRussell King case IRQ_RTCAlrm: 4767b5dea12SRussell King mask = ADXER_WRTC; 4777b5dea12SRussell King break; 4787b5dea12SRussell King case IRQ_SSP4: 4797b5dea12SRussell King mask = ADXER_MFP_WSSP4; 4807b5dea12SRussell King break; 4817b5dea12SRussell King case IRQ_TSI: 4827b5dea12SRussell King mask = ADXER_WTSI; 4837b5dea12SRussell King break; 4847b5dea12SRussell King case IRQ_USIM2: 4857b5dea12SRussell King mask = ADXER_WUSIM1; 4867b5dea12SRussell King break; 4877b5dea12SRussell King case IRQ_MMC2: 4887b5dea12SRussell King mask = ADXER_MFP_WMMC2; 4897b5dea12SRussell King break; 4907b5dea12SRussell King case IRQ_NAND: 4917b5dea12SRussell King mask = ADXER_MFP_WFLASH; 4927b5dea12SRussell King break; 4937b5dea12SRussell King case IRQ_USB2: 4947b5dea12SRussell King mask = ADXER_WUSB2; 4957b5dea12SRussell King break; 4967b5dea12SRussell King case IRQ_WAKEUP0: 4977b5dea12SRussell King mask = ADXER_WEXTWAKE0; 4987b5dea12SRussell King break; 4997b5dea12SRussell King case IRQ_WAKEUP1: 5007b5dea12SRussell King mask = ADXER_WEXTWAKE1; 5017b5dea12SRussell King break; 5027b5dea12SRussell King case IRQ_MMC3: 5037b5dea12SRussell King mask = ADXER_MFP_GEN12; 5047b5dea12SRussell King break; 505e1217707SMark Brown default: 506e1217707SMark Brown return -EINVAL; 5077b5dea12SRussell King } 5087b5dea12SRussell King 5097b5dea12SRussell King local_irq_save(flags); 5107b5dea12SRussell King if (on) 5117b5dea12SRussell King wakeup_src |= mask; 5127b5dea12SRussell King else 5137b5dea12SRussell King wakeup_src &= ~mask; 5147b5dea12SRussell King local_irq_restore(flags); 5157b5dea12SRussell King 5167b5dea12SRussell King return 0; 5177b5dea12SRussell King } 5187b5dea12SRussell King #else 5197b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 520b9e25aceSeric miao #define pxa3xx_set_wake NULL 5217b5dea12SRussell King #endif 5227b5dea12SRussell King 523bf293aecSMike Rapoport static void pxa_ack_ext_wakeup(unsigned int irq) 524bf293aecSMike Rapoport { 525bf293aecSMike Rapoport PECR |= PECR_IS(irq - IRQ_WAKEUP0); 526bf293aecSMike Rapoport } 527bf293aecSMike Rapoport 528bf293aecSMike Rapoport static void pxa_mask_ext_wakeup(unsigned int irq) 529bf293aecSMike Rapoport { 530bf293aecSMike Rapoport ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); 531bf293aecSMike Rapoport PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); 532bf293aecSMike Rapoport } 533bf293aecSMike Rapoport 534bf293aecSMike Rapoport static void pxa_unmask_ext_wakeup(unsigned int irq) 535bf293aecSMike Rapoport { 536bf293aecSMike Rapoport ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); 537bf293aecSMike Rapoport PECR |= PECR_IE(irq - IRQ_WAKEUP0); 538bf293aecSMike Rapoport } 539bf293aecSMike Rapoport 54012882096SIgor Grinberg static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type) 54112882096SIgor Grinberg { 54212882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_RISING) 54312882096SIgor Grinberg PWER |= 1 << (irq - IRQ_WAKEUP0); 54412882096SIgor Grinberg 54512882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_FALLING) 54612882096SIgor Grinberg PWER |= 1 << (irq - IRQ_WAKEUP0 + 2); 54712882096SIgor Grinberg 54812882096SIgor Grinberg return 0; 54912882096SIgor Grinberg } 55012882096SIgor Grinberg 551bf293aecSMike Rapoport static struct irq_chip pxa_ext_wakeup_chip = { 552bf293aecSMike Rapoport .name = "WAKEUP", 553bf293aecSMike Rapoport .ack = pxa_ack_ext_wakeup, 554bf293aecSMike Rapoport .mask = pxa_mask_ext_wakeup, 555bf293aecSMike Rapoport .unmask = pxa_unmask_ext_wakeup, 55612882096SIgor Grinberg .set_type = pxa_set_ext_wakeup_type, 557bf293aecSMike Rapoport }; 558bf293aecSMike Rapoport 559bf293aecSMike Rapoport static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 560bf293aecSMike Rapoport { 561bf293aecSMike Rapoport int irq; 562bf293aecSMike Rapoport 563bf293aecSMike Rapoport for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 564bf293aecSMike Rapoport set_irq_chip(irq, &pxa_ext_wakeup_chip); 565bf293aecSMike Rapoport set_irq_handler(irq, handle_edge_irq); 566bf293aecSMike Rapoport set_irq_flags(irq, IRQF_VALID); 567bf293aecSMike Rapoport } 568bf293aecSMike Rapoport 569bf293aecSMike Rapoport pxa_ext_wakeup_chip.set_wake = fn; 570bf293aecSMike Rapoport } 571bf293aecSMike Rapoport 5722c8086a5Seric miao void __init pxa3xx_init_irq(void) 5732c8086a5Seric miao { 5742c8086a5Seric miao /* enable CP6 access */ 5752c8086a5Seric miao u32 value; 5762c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 5772c8086a5Seric miao value |= (1 << 6); 5782c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 5792c8086a5Seric miao 580b9e25aceSeric miao pxa_init_irq(56, pxa3xx_set_wake); 581bf293aecSMike Rapoport pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 582a58fbcd8SEric Miao pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 5832c8086a5Seric miao } 5842c8086a5Seric miao 585851982c1SMarek Vasut static struct map_desc pxa3xx_io_desc[] __initdata = { 586851982c1SMarek Vasut { /* Mem Ctl */ 587ad68bb9fSMarek Vasut .virtual = SMEMC_VIRT, 588ad68bb9fSMarek Vasut .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 589851982c1SMarek Vasut .length = 0x00200000, 590851982c1SMarek Vasut .type = MT_DEVICE 591851982c1SMarek Vasut } 592851982c1SMarek Vasut }; 593851982c1SMarek Vasut 594851982c1SMarek Vasut void __init pxa3xx_map_io(void) 595851982c1SMarek Vasut { 596851982c1SMarek Vasut pxa_map_io(); 597851982c1SMarek Vasut iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 598851982c1SMarek Vasut pxa3xx_get_clk_frequency_khz(1); 599851982c1SMarek Vasut } 600851982c1SMarek Vasut 6012c8086a5Seric miao /* 6022c8086a5Seric miao * device registration specific to PXA3xx. 6032c8086a5Seric miao */ 6042c8086a5Seric miao 6059ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 6069ba63c4fSMike Rapoport { 60714758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 6089ba63c4fSMike Rapoport } 6099ba63c4fSMike Rapoport 6102c8086a5Seric miao static struct platform_device *devices[] __initdata = { 61194c35a6bSRobert Jarzmik &pxa27x_device_udc, 61209a5358dSEric Miao &pxa_device_pmu, 6132c8086a5Seric miao &pxa_device_i2s, 614f0fba2adSLiam Girdwood &pxa_device_asoc_ssp1, 615f0fba2adSLiam Girdwood &pxa_device_asoc_ssp2, 616f0fba2adSLiam Girdwood &pxa_device_asoc_ssp3, 617f0fba2adSLiam Girdwood &pxa_device_asoc_ssp4, 618f0fba2adSLiam Girdwood &pxa_device_asoc_platform, 61972493146SRobert Jarzmik &sa1100_device_rtc, 6202c8086a5Seric miao &pxa_device_rtc, 621d8e0db11Seric miao &pxa27x_device_ssp1, 622d8e0db11Seric miao &pxa27x_device_ssp2, 623d8e0db11Seric miao &pxa27x_device_ssp3, 624d8e0db11Seric miao &pxa3xx_device_ssp4, 62575540c1aSeric miao &pxa27x_device_pwm0, 62675540c1aSeric miao &pxa27x_device_pwm1, 6272c8086a5Seric miao }; 6282c8086a5Seric miao 629c0165504Seric miao static struct sys_device pxa3xx_sysdev[] = { 630c0165504Seric miao { 631c0165504Seric miao .cls = &pxa_irq_sysclass, 63216dfdbf0Seric miao }, { 6334be35e23Seric miao .cls = &pxa3xx_mfp_sysclass, 6344be35e23Seric miao }, { 63516dfdbf0Seric miao .cls = &pxa_gpio_sysclass, 636c0165504Seric miao }, 637c0165504Seric miao }; 638c0165504Seric miao 6392c8086a5Seric miao static int __init pxa3xx_init(void) 6402c8086a5Seric miao { 641c0165504Seric miao int i, ret = 0; 6422c8086a5Seric miao 6432c8086a5Seric miao if (cpu_is_pxa3xx()) { 64404fef228SEric Miao 64504fef228SEric Miao reset_status = ARSR; 64604fef228SEric Miao 64786260f98SDmitry Krivoschekov /* 64886260f98SDmitry Krivoschekov * clear RDH bit every time after reset 64986260f98SDmitry Krivoschekov * 65086260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 65186260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 65286260f98SDmitry Krivoschekov */ 65386260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 65486260f98SDmitry Krivoschekov 6550a0300dcSRussell King clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 6562c8086a5Seric miao 657fef1f99aSEric Miao if ((ret = pxa_init_dma(IRQ_DMA, 32))) 6582c8086a5Seric miao return ret; 6592c8086a5Seric miao 6607b5dea12SRussell King pxa3xx_init_pm(); 6617b5dea12SRussell King 662c0165504Seric miao for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 663c0165504Seric miao ret = sysdev_register(&pxa3xx_sysdev[i]); 664c0165504Seric miao if (ret) 665c0165504Seric miao pr_err("failed to register sysdev[%d]\n", i); 6662c8086a5Seric miao } 667c0165504Seric miao 668c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 669c0165504Seric miao } 670c0165504Seric miao 671c0165504Seric miao return ret; 6722c8086a5Seric miao } 6732c8086a5Seric miao 6741c104e0eSRussell King postcore_initcall(pxa3xx_init); 675