12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao 162c8086a5Seric miao #include <linux/module.h> 172c8086a5Seric miao #include <linux/kernel.h> 182c8086a5Seric miao #include <linux/init.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 227b5dea12SRussell King #include <linux/io.h> 23c0165504Seric miao #include <linux/sysdev.h> 242c8086a5Seric miao 25851982c1SMarek Vasut #include <asm/mach/map.h> 26a09e64fbSRussell King #include <mach/hardware.h> 27a58fbcd8SEric Miao #include <mach/gpio.h> 28a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 29afd2fc02SRussell King #include <mach/reset.h> 30a09e64fbSRussell King #include <mach/ohci.h> 31a09e64fbSRussell King #include <mach/pm.h> 32a09e64fbSRussell King #include <mach/dma.h> 33bf293aecSMike Rapoport #include <mach/regs-intc.h> 34ad68bb9fSMarek Vasut #include <mach/smemc.h> 35f0a83701SEric Miao #include <plat/i2c.h> 362c8086a5Seric miao 372c8086a5Seric miao #include "generic.h" 382c8086a5Seric miao #include "devices.h" 392c8086a5Seric miao #include "clock.h" 402c8086a5Seric miao 41bf293aecSMike Rapoport #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 42bf293aecSMike Rapoport #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 43bf293aecSMike Rapoport 448c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 458c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 468c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 478c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 488c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 498c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 50e68750aeSIgor Grinberg static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 518c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 528c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 538c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 548c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 558c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 568c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 578c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 588c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 598c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 602c8086a5Seric miao 612e8581e7SEric Miao static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 62c085052bSEric Miao static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); 632e8581e7SEric Miao static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 642e8581e7SEric Miao static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 654029813cSEric Miao static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); 662e8581e7SEric Miao 678c3abc7dSRussell King static struct clk_lookup pxa3xx_clkregs[] = { 688c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 698c3abc7dSRussell King /* Power I2C clock is always on */ 705c68b099SDaniel Mack INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 718c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 728c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 738c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 748c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 758c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 768c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 778c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 788c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 798c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 808c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 8169f22be7SIgor Grinberg INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 828c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 838c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 848c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 858c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 868c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 878c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 888c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 898c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 908c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 91c085052bSEric Miao INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), 922c8086a5Seric miao }; 932c8086a5Seric miao 947b5dea12SRussell King #ifdef CONFIG_PM 957b5dea12SRussell King 967b5dea12SRussell King #define ISRAM_START 0x5c000000 977b5dea12SRussell King #define ISRAM_SIZE SZ_256K 987b5dea12SRussell King 997b5dea12SRussell King static void __iomem *sram; 1007b5dea12SRussell King static unsigned long wakeup_src; 1017b5dea12SRussell King 1027b5dea12SRussell King /* 1037b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 1047b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 1057b5dea12SRussell King * in the SRAM to perform this function. 1067b5dea12SRussell King * 1077b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 1087b5dea12SRussell King * FIQ while the SDRAM is unavailable. 1097b5dea12SRussell King */ 1107b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 1117b5dea12SRussell King { 1127b5dea12SRussell King extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 1137b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 1147b5dea12SRussell King 1157b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 1167b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 1177b5dea12SRussell King 1187b5dea12SRussell King AD2D0SR = ~0; 1197b5dea12SRussell King AD2D1SR = ~0; 1207b5dea12SRussell King AD2D0ER = wakeup_src; 1217b5dea12SRussell King AD2D1ER = 0; 1227b5dea12SRussell King ASCR = ASCR; 1237b5dea12SRussell King ARSR = ARSR; 1247b5dea12SRussell King 1257b5dea12SRussell King local_fiq_disable(); 1267b5dea12SRussell King fn(pwrmode); 1277b5dea12SRussell King local_fiq_enable(); 1287b5dea12SRussell King 1297b5dea12SRussell King AD2D0ER = 0; 1307b5dea12SRussell King AD2D1ER = 0; 1317b5dea12SRussell King } 1327b5dea12SRussell King 133c4d1fb62Seric miao /* 134c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 135c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 136c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 137c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 138c4d1fb62Seric miao * 0x5c014000 for the moment. 139c4d1fb62Seric miao */ 140c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 141c4d1fb62Seric miao { 142c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 143c4d1fb62Seric miao unsigned long saved_data = *p; 144c4d1fb62Seric miao 145c4d1fb62Seric miao extern void pxa3xx_cpu_suspend(void); 146c4d1fb62Seric miao extern void pxa3xx_cpu_resume(void); 147c4d1fb62Seric miao 148c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 149c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 150c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 151c4d1fb62Seric miao 152c4d1fb62Seric miao /* clear and setup wakeup source */ 153c4d1fb62Seric miao AD3SR = ~0; 154c4d1fb62Seric miao AD3ER = wakeup_src; 155c4d1fb62Seric miao ASCR = ASCR; 156c4d1fb62Seric miao ARSR = ARSR; 157c4d1fb62Seric miao 158c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 159c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 160c4d1fb62Seric miao 161c4d1fb62Seric miao PSPR = 0x5c014000; 162c4d1fb62Seric miao 163c4d1fb62Seric miao /* overwrite with the resume address */ 164c4d1fb62Seric miao *p = virt_to_phys(pxa3xx_cpu_resume); 165c4d1fb62Seric miao 166c4d1fb62Seric miao pxa3xx_cpu_suspend(); 167c4d1fb62Seric miao 168c4d1fb62Seric miao *p = saved_data; 169c4d1fb62Seric miao 170c4d1fb62Seric miao AD3ER = 0; 171c4d1fb62Seric miao } 172c4d1fb62Seric miao 1737b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 1747b5dea12SRussell King { 1757b5dea12SRussell King /* 1767b5dea12SRussell King * Don't sleep if no wakeup sources are defined 1777b5dea12SRussell King */ 178b86a5da8SMark Brown if (wakeup_src == 0) { 179b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 1807b5dea12SRussell King return; 181b86a5da8SMark Brown } 1827b5dea12SRussell King 1837b5dea12SRussell King switch (state) { 1847b5dea12SRussell King case PM_SUSPEND_STANDBY: 1857b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 1867b5dea12SRussell King break; 1877b5dea12SRussell King 1887b5dea12SRussell King case PM_SUSPEND_MEM: 189c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 1907b5dea12SRussell King break; 1917b5dea12SRussell King } 1927b5dea12SRussell King } 1937b5dea12SRussell King 1947b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 1957b5dea12SRussell King { 1967b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 1977b5dea12SRussell King } 1987b5dea12SRussell King 1997b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 2007b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 2017b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 2027b5dea12SRussell King }; 2037b5dea12SRussell King 2047b5dea12SRussell King static void __init pxa3xx_init_pm(void) 2057b5dea12SRussell King { 2067b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 2077b5dea12SRussell King if (!sram) { 2087b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 2097b5dea12SRussell King return; 2107b5dea12SRussell King } 2117b5dea12SRussell King 2127b5dea12SRussell King /* 2137b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 2147b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 2157b5dea12SRussell King * is undocumented in the developer manual, but must be set. 2167b5dea12SRussell King */ 2177b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 2187b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 2197b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 2207b5dea12SRussell King 2217b5dea12SRussell King /* 2227b5dea12SRussell King * Clear the resume enable registers. 2237b5dea12SRussell King */ 2247b5dea12SRussell King AD1D0ER = 0; 2257b5dea12SRussell King AD2D0ER = 0; 2267b5dea12SRussell King AD2D1ER = 0; 2277b5dea12SRussell King AD3ER = 0; 2287b5dea12SRussell King 2297b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 2307b5dea12SRussell King } 2317b5dea12SRussell King 232a3f4c927SLennert Buytenhek static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 2337b5dea12SRussell King { 2347b5dea12SRussell King unsigned long flags, mask = 0; 2357b5dea12SRussell King 236a3f4c927SLennert Buytenhek switch (d->irq) { 2377b5dea12SRussell King case IRQ_SSP3: 2387b5dea12SRussell King mask = ADXER_MFP_WSSP3; 2397b5dea12SRussell King break; 2407b5dea12SRussell King case IRQ_MSL: 2417b5dea12SRussell King mask = ADXER_WMSL0; 2427b5dea12SRussell King break; 2437b5dea12SRussell King case IRQ_USBH2: 2447b5dea12SRussell King case IRQ_USBH1: 2457b5dea12SRussell King mask = ADXER_WUSBH; 2467b5dea12SRussell King break; 2477b5dea12SRussell King case IRQ_KEYPAD: 2487b5dea12SRussell King mask = ADXER_WKP; 2497b5dea12SRussell King break; 2507b5dea12SRussell King case IRQ_AC97: 2517b5dea12SRussell King mask = ADXER_MFP_WAC97; 2527b5dea12SRussell King break; 2537b5dea12SRussell King case IRQ_USIM: 2547b5dea12SRussell King mask = ADXER_WUSIM0; 2557b5dea12SRussell King break; 2567b5dea12SRussell King case IRQ_SSP2: 2577b5dea12SRussell King mask = ADXER_MFP_WSSP2; 2587b5dea12SRussell King break; 2597b5dea12SRussell King case IRQ_I2C: 2607b5dea12SRussell King mask = ADXER_MFP_WI2C; 2617b5dea12SRussell King break; 2627b5dea12SRussell King case IRQ_STUART: 2637b5dea12SRussell King mask = ADXER_MFP_WUART3; 2647b5dea12SRussell King break; 2657b5dea12SRussell King case IRQ_BTUART: 2667b5dea12SRussell King mask = ADXER_MFP_WUART2; 2677b5dea12SRussell King break; 2687b5dea12SRussell King case IRQ_FFUART: 2697b5dea12SRussell King mask = ADXER_MFP_WUART1; 2707b5dea12SRussell King break; 2717b5dea12SRussell King case IRQ_MMC: 2727b5dea12SRussell King mask = ADXER_MFP_WMMC1; 2737b5dea12SRussell King break; 2747b5dea12SRussell King case IRQ_SSP: 2757b5dea12SRussell King mask = ADXER_MFP_WSSP1; 2767b5dea12SRussell King break; 2777b5dea12SRussell King case IRQ_RTCAlrm: 2787b5dea12SRussell King mask = ADXER_WRTC; 2797b5dea12SRussell King break; 2807b5dea12SRussell King case IRQ_SSP4: 2817b5dea12SRussell King mask = ADXER_MFP_WSSP4; 2827b5dea12SRussell King break; 2837b5dea12SRussell King case IRQ_TSI: 2847b5dea12SRussell King mask = ADXER_WTSI; 2857b5dea12SRussell King break; 2867b5dea12SRussell King case IRQ_USIM2: 2877b5dea12SRussell King mask = ADXER_WUSIM1; 2887b5dea12SRussell King break; 2897b5dea12SRussell King case IRQ_MMC2: 2907b5dea12SRussell King mask = ADXER_MFP_WMMC2; 2917b5dea12SRussell King break; 2927b5dea12SRussell King case IRQ_NAND: 2937b5dea12SRussell King mask = ADXER_MFP_WFLASH; 2947b5dea12SRussell King break; 2957b5dea12SRussell King case IRQ_USB2: 2967b5dea12SRussell King mask = ADXER_WUSB2; 2977b5dea12SRussell King break; 2987b5dea12SRussell King case IRQ_WAKEUP0: 2997b5dea12SRussell King mask = ADXER_WEXTWAKE0; 3007b5dea12SRussell King break; 3017b5dea12SRussell King case IRQ_WAKEUP1: 3027b5dea12SRussell King mask = ADXER_WEXTWAKE1; 3037b5dea12SRussell King break; 3047b5dea12SRussell King case IRQ_MMC3: 3057b5dea12SRussell King mask = ADXER_MFP_GEN12; 3067b5dea12SRussell King break; 307e1217707SMark Brown default: 308e1217707SMark Brown return -EINVAL; 3097b5dea12SRussell King } 3107b5dea12SRussell King 3117b5dea12SRussell King local_irq_save(flags); 3127b5dea12SRussell King if (on) 3137b5dea12SRussell King wakeup_src |= mask; 3147b5dea12SRussell King else 3157b5dea12SRussell King wakeup_src &= ~mask; 3167b5dea12SRussell King local_irq_restore(flags); 3177b5dea12SRussell King 3187b5dea12SRussell King return 0; 3197b5dea12SRussell King } 3207b5dea12SRussell King #else 3217b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 322b9e25aceSeric miao #define pxa3xx_set_wake NULL 3237b5dea12SRussell King #endif 3247b5dea12SRussell King 325a3f4c927SLennert Buytenhek static void pxa_ack_ext_wakeup(struct irq_data *d) 326bf293aecSMike Rapoport { 327a3f4c927SLennert Buytenhek PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 328bf293aecSMike Rapoport } 329bf293aecSMike Rapoport 330a3f4c927SLennert Buytenhek static void pxa_mask_ext_wakeup(struct irq_data *d) 331bf293aecSMike Rapoport { 332a3f4c927SLennert Buytenhek ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f)); 333a3f4c927SLennert Buytenhek PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 334bf293aecSMike Rapoport } 335bf293aecSMike Rapoport 336a3f4c927SLennert Buytenhek static void pxa_unmask_ext_wakeup(struct irq_data *d) 337bf293aecSMike Rapoport { 338a3f4c927SLennert Buytenhek ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f); 339a3f4c927SLennert Buytenhek PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 340bf293aecSMike Rapoport } 341bf293aecSMike Rapoport 342a3f4c927SLennert Buytenhek static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 34312882096SIgor Grinberg { 34412882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_RISING) 345a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0); 34612882096SIgor Grinberg 34712882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_FALLING) 348a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 34912882096SIgor Grinberg 35012882096SIgor Grinberg return 0; 35112882096SIgor Grinberg } 35212882096SIgor Grinberg 353bf293aecSMike Rapoport static struct irq_chip pxa_ext_wakeup_chip = { 354bf293aecSMike Rapoport .name = "WAKEUP", 355a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_ext_wakeup, 356a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_ext_wakeup, 357a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_ext_wakeup, 358a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_ext_wakeup_type, 359bf293aecSMike Rapoport }; 360bf293aecSMike Rapoport 361bf293aecSMike Rapoport static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 362bf293aecSMike Rapoport { 363bf293aecSMike Rapoport int irq; 364bf293aecSMike Rapoport 365bf293aecSMike Rapoport for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 366bf293aecSMike Rapoport set_irq_chip(irq, &pxa_ext_wakeup_chip); 367bf293aecSMike Rapoport set_irq_handler(irq, handle_edge_irq); 368bf293aecSMike Rapoport set_irq_flags(irq, IRQF_VALID); 369bf293aecSMike Rapoport } 370bf293aecSMike Rapoport 371a3f4c927SLennert Buytenhek pxa_ext_wakeup_chip.irq_set_wake = fn; 372bf293aecSMike Rapoport } 373bf293aecSMike Rapoport 3742c8086a5Seric miao void __init pxa3xx_init_irq(void) 3752c8086a5Seric miao { 3762c8086a5Seric miao /* enable CP6 access */ 3772c8086a5Seric miao u32 value; 3782c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 3792c8086a5Seric miao value |= (1 << 6); 3802c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 3812c8086a5Seric miao 382b9e25aceSeric miao pxa_init_irq(56, pxa3xx_set_wake); 383bf293aecSMike Rapoport pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 384a58fbcd8SEric Miao pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 3852c8086a5Seric miao } 3862c8086a5Seric miao 387851982c1SMarek Vasut static struct map_desc pxa3xx_io_desc[] __initdata = { 388851982c1SMarek Vasut { /* Mem Ctl */ 389ad68bb9fSMarek Vasut .virtual = SMEMC_VIRT, 390ad68bb9fSMarek Vasut .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 391851982c1SMarek Vasut .length = 0x00200000, 392851982c1SMarek Vasut .type = MT_DEVICE 393851982c1SMarek Vasut } 394851982c1SMarek Vasut }; 395851982c1SMarek Vasut 396851982c1SMarek Vasut void __init pxa3xx_map_io(void) 397851982c1SMarek Vasut { 398851982c1SMarek Vasut pxa_map_io(); 399851982c1SMarek Vasut iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 400851982c1SMarek Vasut pxa3xx_get_clk_frequency_khz(1); 401851982c1SMarek Vasut } 402851982c1SMarek Vasut 4032c8086a5Seric miao /* 4042c8086a5Seric miao * device registration specific to PXA3xx. 4052c8086a5Seric miao */ 4062c8086a5Seric miao 4079ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 4089ba63c4fSMike Rapoport { 40914758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 4109ba63c4fSMike Rapoport } 4119ba63c4fSMike Rapoport 4122c8086a5Seric miao static struct platform_device *devices[] __initdata = { 41394c35a6bSRobert Jarzmik &pxa27x_device_udc, 41409a5358dSEric Miao &pxa_device_pmu, 4152c8086a5Seric miao &pxa_device_i2s, 416f0fba2adSLiam Girdwood &pxa_device_asoc_ssp1, 417f0fba2adSLiam Girdwood &pxa_device_asoc_ssp2, 418f0fba2adSLiam Girdwood &pxa_device_asoc_ssp3, 419f0fba2adSLiam Girdwood &pxa_device_asoc_ssp4, 420f0fba2adSLiam Girdwood &pxa_device_asoc_platform, 42172493146SRobert Jarzmik &sa1100_device_rtc, 4222c8086a5Seric miao &pxa_device_rtc, 423d8e0db11Seric miao &pxa27x_device_ssp1, 424d8e0db11Seric miao &pxa27x_device_ssp2, 425d8e0db11Seric miao &pxa27x_device_ssp3, 426d8e0db11Seric miao &pxa3xx_device_ssp4, 42775540c1aSeric miao &pxa27x_device_pwm0, 42875540c1aSeric miao &pxa27x_device_pwm1, 4292c8086a5Seric miao }; 4302c8086a5Seric miao 431c0165504Seric miao static struct sys_device pxa3xx_sysdev[] = { 432c0165504Seric miao { 433c0165504Seric miao .cls = &pxa_irq_sysclass, 43416dfdbf0Seric miao }, { 4354be35e23Seric miao .cls = &pxa3xx_mfp_sysclass, 4364be35e23Seric miao }, { 43716dfdbf0Seric miao .cls = &pxa_gpio_sysclass, 438aae8224dSEric Miao }, { 439aae8224dSEric Miao .cls = &pxa3xx_clock_sysclass, 440aae8224dSEric Miao } 441c0165504Seric miao }; 442c0165504Seric miao 4432c8086a5Seric miao static int __init pxa3xx_init(void) 4442c8086a5Seric miao { 445c0165504Seric miao int i, ret = 0; 4462c8086a5Seric miao 4472c8086a5Seric miao if (cpu_is_pxa3xx()) { 44804fef228SEric Miao 44904fef228SEric Miao reset_status = ARSR; 45004fef228SEric Miao 45186260f98SDmitry Krivoschekov /* 45286260f98SDmitry Krivoschekov * clear RDH bit every time after reset 45386260f98SDmitry Krivoschekov * 45486260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 45586260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 45686260f98SDmitry Krivoschekov */ 45786260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 45886260f98SDmitry Krivoschekov 4590a0300dcSRussell King clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 4602c8086a5Seric miao 461fef1f99aSEric Miao if ((ret = pxa_init_dma(IRQ_DMA, 32))) 4622c8086a5Seric miao return ret; 4632c8086a5Seric miao 4647b5dea12SRussell King pxa3xx_init_pm(); 4657b5dea12SRussell King 466c0165504Seric miao for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 467c0165504Seric miao ret = sysdev_register(&pxa3xx_sysdev[i]); 468c0165504Seric miao if (ret) 469c0165504Seric miao pr_err("failed to register sysdev[%d]\n", i); 4702c8086a5Seric miao } 471c0165504Seric miao 472c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 473c0165504Seric miao } 474c0165504Seric miao 475c0165504Seric miao return ret; 4762c8086a5Seric miao } 4772c8086a5Seric miao 4781c104e0eSRussell King postcore_initcall(pxa3xx_init); 479