12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao #include <linux/module.h> 162c8086a5Seric miao #include <linux/kernel.h> 172c8086a5Seric miao #include <linux/init.h> 18b8f649f1SHaojian Zhuang #include <linux/gpio-pxa.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 2232f17997SRobert Jarzmik #include <linux/irqchip.h> 237b5dea12SRussell King #include <linux/io.h> 2482ce44d1SDaniel Mack #include <linux/of.h> 252eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 26b459396eSSebastian Andrzej Siewior #include <linux/i2c/pxa-i2c.h> 272c8086a5Seric miao 28851982c1SMarek Vasut #include <asm/mach/map.h> 292c74a0ceSRussell King #include <asm/suspend.h> 30a09e64fbSRussell King #include <mach/hardware.h> 31a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 32afd2fc02SRussell King #include <mach/reset.h> 33293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h> 344c25c5d2SArnd Bergmann #include "pm.h" 35a09e64fbSRussell King #include <mach/dma.h> 36ad68bb9fSMarek Vasut #include <mach/smemc.h> 374e611091SRob Herring #include <mach/irqs.h> 382c8086a5Seric miao 392c8086a5Seric miao #include "generic.h" 402c8086a5Seric miao #include "devices.h" 412c8086a5Seric miao 42bf293aecSMike Rapoport #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 43bf293aecSMike Rapoport #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 44bf293aecSMike Rapoport 45089d0362SDaniel Mack extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); 467b5dea12SRussell King 47adf3442cSRobert Jarzmik /* 48adf3442cSRobert Jarzmik * NAND NFC: DFI bus arbitration subset 49adf3442cSRobert Jarzmik */ 50adf3442cSRobert Jarzmik #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0)) 51adf3442cSRobert Jarzmik #define NDCR_ND_ARB_EN (1 << 12) 52adf3442cSRobert Jarzmik #define NDCR_ND_ARB_CNTL (1 << 19) 53adf3442cSRobert Jarzmik 5463910745SArnd Bergmann #ifdef CONFIG_PM 5563910745SArnd Bergmann 5663910745SArnd Bergmann #define ISRAM_START 0x5c000000 5763910745SArnd Bergmann #define ISRAM_SIZE SZ_256K 5863910745SArnd Bergmann 597b5dea12SRussell King static void __iomem *sram; 607b5dea12SRussell King static unsigned long wakeup_src; 617b5dea12SRussell King 627b5dea12SRussell King /* 637b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 647b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 657b5dea12SRussell King * in the SRAM to perform this function. 667b5dea12SRussell King * 677b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 687b5dea12SRussell King * FIQ while the SDRAM is unavailable. 697b5dea12SRussell King */ 707b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 717b5dea12SRussell King { 727b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 737b5dea12SRussell King 747b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 757b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 767b5dea12SRussell King 777b5dea12SRussell King AD2D0SR = ~0; 787b5dea12SRussell King AD2D1SR = ~0; 797b5dea12SRussell King AD2D0ER = wakeup_src; 807b5dea12SRussell King AD2D1ER = 0; 817b5dea12SRussell King ASCR = ASCR; 827b5dea12SRussell King ARSR = ARSR; 837b5dea12SRussell King 847b5dea12SRussell King local_fiq_disable(); 857b5dea12SRussell King fn(pwrmode); 867b5dea12SRussell King local_fiq_enable(); 877b5dea12SRussell King 887b5dea12SRussell King AD2D0ER = 0; 897b5dea12SRussell King AD2D1ER = 0; 907b5dea12SRussell King } 917b5dea12SRussell King 92c4d1fb62Seric miao /* 93c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 94c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 95c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 96c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 97c4d1fb62Seric miao * 0x5c014000 for the moment. 98c4d1fb62Seric miao */ 99c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 100c4d1fb62Seric miao { 101c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 102c4d1fb62Seric miao unsigned long saved_data = *p; 103a9503d21SRussell King #ifndef CONFIG_IWMMXT 104a9503d21SRussell King u64 acc0; 105c4d1fb62Seric miao 106343c1cdbSArnd Bergmann asm volatile(".arch_extension xscale\n\t" 107343c1cdbSArnd Bergmann "mra %Q0, %R0, acc0" : "=r" (acc0)); 108a9503d21SRussell King #endif 109a9503d21SRussell King 110c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 111c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 112c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 113c4d1fb62Seric miao 114c4d1fb62Seric miao /* clear and setup wakeup source */ 115c4d1fb62Seric miao AD3SR = ~0; 116c4d1fb62Seric miao AD3ER = wakeup_src; 117c4d1fb62Seric miao ASCR = ASCR; 118c4d1fb62Seric miao ARSR = ARSR; 119c4d1fb62Seric miao 120c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 121c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 122c4d1fb62Seric miao 123c4d1fb62Seric miao PSPR = 0x5c014000; 124c4d1fb62Seric miao 125c4d1fb62Seric miao /* overwrite with the resume address */ 12664fc2a94SFlorian Fainelli *p = __pa_symbol(cpu_resume); 127c4d1fb62Seric miao 1282c74a0ceSRussell King cpu_suspend(0, pxa3xx_finish_suspend); 129c4d1fb62Seric miao 130c4d1fb62Seric miao *p = saved_data; 131c4d1fb62Seric miao 132c4d1fb62Seric miao AD3ER = 0; 133a9503d21SRussell King 134a9503d21SRussell King #ifndef CONFIG_IWMMXT 135343c1cdbSArnd Bergmann asm volatile(".arch_extension xscale\n\t" 136343c1cdbSArnd Bergmann "mar acc0, %Q0, %R0" : "=r" (acc0)); 137a9503d21SRussell King #endif 138c4d1fb62Seric miao } 139c4d1fb62Seric miao 1407b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 1417b5dea12SRussell King { 1427b5dea12SRussell King /* 1437b5dea12SRussell King * Don't sleep if no wakeup sources are defined 1447b5dea12SRussell King */ 145b86a5da8SMark Brown if (wakeup_src == 0) { 146b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 1477b5dea12SRussell King return; 148b86a5da8SMark Brown } 1497b5dea12SRussell King 1507b5dea12SRussell King switch (state) { 1517b5dea12SRussell King case PM_SUSPEND_STANDBY: 1527b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 1537b5dea12SRussell King break; 1547b5dea12SRussell King 1557b5dea12SRussell King case PM_SUSPEND_MEM: 156c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 1577b5dea12SRussell King break; 1587b5dea12SRussell King } 1597b5dea12SRussell King } 1607b5dea12SRussell King 1617b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 1627b5dea12SRussell King { 1637b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 1647b5dea12SRussell King } 1657b5dea12SRussell King 1667b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 1677b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 1687b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 1697b5dea12SRussell King }; 1707b5dea12SRussell King 1717b5dea12SRussell King static void __init pxa3xx_init_pm(void) 1727b5dea12SRussell King { 1737b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 1747b5dea12SRussell King if (!sram) { 1757b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 1767b5dea12SRussell King return; 1777b5dea12SRussell King } 1787b5dea12SRussell King 1797b5dea12SRussell King /* 1807b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 1817b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 1827b5dea12SRussell King * is undocumented in the developer manual, but must be set. 1837b5dea12SRussell King */ 1847b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 1857b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 1867b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 1877b5dea12SRussell King 1887b5dea12SRussell King /* 1897b5dea12SRussell King * Clear the resume enable registers. 1907b5dea12SRussell King */ 1917b5dea12SRussell King AD1D0ER = 0; 1927b5dea12SRussell King AD2D0ER = 0; 1937b5dea12SRussell King AD2D1ER = 0; 1947b5dea12SRussell King AD3ER = 0; 1957b5dea12SRussell King 1967b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 1977b5dea12SRussell King } 1987b5dea12SRussell King 199a3f4c927SLennert Buytenhek static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 2007b5dea12SRussell King { 2017b5dea12SRussell King unsigned long flags, mask = 0; 2027b5dea12SRussell King 203a3f4c927SLennert Buytenhek switch (d->irq) { 2047b5dea12SRussell King case IRQ_SSP3: 2057b5dea12SRussell King mask = ADXER_MFP_WSSP3; 2067b5dea12SRussell King break; 2077b5dea12SRussell King case IRQ_MSL: 2087b5dea12SRussell King mask = ADXER_WMSL0; 2097b5dea12SRussell King break; 2107b5dea12SRussell King case IRQ_USBH2: 2117b5dea12SRussell King case IRQ_USBH1: 2127b5dea12SRussell King mask = ADXER_WUSBH; 2137b5dea12SRussell King break; 2147b5dea12SRussell King case IRQ_KEYPAD: 2157b5dea12SRussell King mask = ADXER_WKP; 2167b5dea12SRussell King break; 2177b5dea12SRussell King case IRQ_AC97: 2187b5dea12SRussell King mask = ADXER_MFP_WAC97; 2197b5dea12SRussell King break; 2207b5dea12SRussell King case IRQ_USIM: 2217b5dea12SRussell King mask = ADXER_WUSIM0; 2227b5dea12SRussell King break; 2237b5dea12SRussell King case IRQ_SSP2: 2247b5dea12SRussell King mask = ADXER_MFP_WSSP2; 2257b5dea12SRussell King break; 2267b5dea12SRussell King case IRQ_I2C: 2277b5dea12SRussell King mask = ADXER_MFP_WI2C; 2287b5dea12SRussell King break; 2297b5dea12SRussell King case IRQ_STUART: 2307b5dea12SRussell King mask = ADXER_MFP_WUART3; 2317b5dea12SRussell King break; 2327b5dea12SRussell King case IRQ_BTUART: 2337b5dea12SRussell King mask = ADXER_MFP_WUART2; 2347b5dea12SRussell King break; 2357b5dea12SRussell King case IRQ_FFUART: 2367b5dea12SRussell King mask = ADXER_MFP_WUART1; 2377b5dea12SRussell King break; 2387b5dea12SRussell King case IRQ_MMC: 2397b5dea12SRussell King mask = ADXER_MFP_WMMC1; 2407b5dea12SRussell King break; 2417b5dea12SRussell King case IRQ_SSP: 2427b5dea12SRussell King mask = ADXER_MFP_WSSP1; 2437b5dea12SRussell King break; 2447b5dea12SRussell King case IRQ_RTCAlrm: 2457b5dea12SRussell King mask = ADXER_WRTC; 2467b5dea12SRussell King break; 2477b5dea12SRussell King case IRQ_SSP4: 2487b5dea12SRussell King mask = ADXER_MFP_WSSP4; 2497b5dea12SRussell King break; 2507b5dea12SRussell King case IRQ_TSI: 2517b5dea12SRussell King mask = ADXER_WTSI; 2527b5dea12SRussell King break; 2537b5dea12SRussell King case IRQ_USIM2: 2547b5dea12SRussell King mask = ADXER_WUSIM1; 2557b5dea12SRussell King break; 2567b5dea12SRussell King case IRQ_MMC2: 2577b5dea12SRussell King mask = ADXER_MFP_WMMC2; 2587b5dea12SRussell King break; 2597b5dea12SRussell King case IRQ_NAND: 2607b5dea12SRussell King mask = ADXER_MFP_WFLASH; 2617b5dea12SRussell King break; 2627b5dea12SRussell King case IRQ_USB2: 2637b5dea12SRussell King mask = ADXER_WUSB2; 2647b5dea12SRussell King break; 2657b5dea12SRussell King case IRQ_WAKEUP0: 2667b5dea12SRussell King mask = ADXER_WEXTWAKE0; 2677b5dea12SRussell King break; 2687b5dea12SRussell King case IRQ_WAKEUP1: 2697b5dea12SRussell King mask = ADXER_WEXTWAKE1; 2707b5dea12SRussell King break; 2717b5dea12SRussell King case IRQ_MMC3: 2727b5dea12SRussell King mask = ADXER_MFP_GEN12; 2737b5dea12SRussell King break; 274e1217707SMark Brown default: 275e1217707SMark Brown return -EINVAL; 2767b5dea12SRussell King } 2777b5dea12SRussell King 2787b5dea12SRussell King local_irq_save(flags); 2797b5dea12SRussell King if (on) 2807b5dea12SRussell King wakeup_src |= mask; 2817b5dea12SRussell King else 2827b5dea12SRussell King wakeup_src &= ~mask; 2837b5dea12SRussell King local_irq_restore(flags); 2847b5dea12SRussell King 2857b5dea12SRussell King return 0; 2867b5dea12SRussell King } 2877b5dea12SRussell King #else 2887b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 289b9e25aceSeric miao #define pxa3xx_set_wake NULL 2907b5dea12SRussell King #endif 2917b5dea12SRussell King 292a3f4c927SLennert Buytenhek static void pxa_ack_ext_wakeup(struct irq_data *d) 293bf293aecSMike Rapoport { 294a3f4c927SLennert Buytenhek PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 295bf293aecSMike Rapoport } 296bf293aecSMike Rapoport 297a3f4c927SLennert Buytenhek static void pxa_mask_ext_wakeup(struct irq_data *d) 298bf293aecSMike Rapoport { 2995d284e35SEric Miao pxa_mask_irq(d); 300a3f4c927SLennert Buytenhek PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 301bf293aecSMike Rapoport } 302bf293aecSMike Rapoport 303a3f4c927SLennert Buytenhek static void pxa_unmask_ext_wakeup(struct irq_data *d) 304bf293aecSMike Rapoport { 3055d284e35SEric Miao pxa_unmask_irq(d); 306a3f4c927SLennert Buytenhek PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 307bf293aecSMike Rapoport } 308bf293aecSMike Rapoport 309a3f4c927SLennert Buytenhek static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 31012882096SIgor Grinberg { 31112882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_RISING) 312a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0); 31312882096SIgor Grinberg 31412882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_FALLING) 315a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 31612882096SIgor Grinberg 31712882096SIgor Grinberg return 0; 31812882096SIgor Grinberg } 31912882096SIgor Grinberg 320bf293aecSMike Rapoport static struct irq_chip pxa_ext_wakeup_chip = { 321bf293aecSMike Rapoport .name = "WAKEUP", 322a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_ext_wakeup, 323a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_ext_wakeup, 324a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_ext_wakeup, 325a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_ext_wakeup_type, 326bf293aecSMike Rapoport }; 327bf293aecSMike Rapoport 328157d2644SHaojian Zhuang static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, 329157d2644SHaojian Zhuang unsigned int)) 330bf293aecSMike Rapoport { 331bf293aecSMike Rapoport int irq; 332bf293aecSMike Rapoport 333bf293aecSMike Rapoport for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 334f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 335f38c02f3SThomas Gleixner handle_edge_irq); 336e8d36d5dSRob Herring irq_clear_status_flags(irq, IRQ_NOREQUEST); 337bf293aecSMike Rapoport } 338bf293aecSMike Rapoport 339a3f4c927SLennert Buytenhek pxa_ext_wakeup_chip.irq_set_wake = fn; 340bf293aecSMike Rapoport } 341bf293aecSMike Rapoport 342089d0362SDaniel Mack static void __init __pxa3xx_init_irq(void) 3432c8086a5Seric miao { 3442c8086a5Seric miao /* enable CP6 access */ 3452c8086a5Seric miao u32 value; 3462c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 3472c8086a5Seric miao value |= (1 << 6); 3482c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 3492c8086a5Seric miao 350bf293aecSMike Rapoport pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 3512c8086a5Seric miao } 3522c8086a5Seric miao 353089d0362SDaniel Mack void __init pxa3xx_init_irq(void) 354089d0362SDaniel Mack { 355089d0362SDaniel Mack __pxa3xx_init_irq(); 356089d0362SDaniel Mack pxa_init_irq(56, pxa3xx_set_wake); 357089d0362SDaniel Mack } 358089d0362SDaniel Mack 359e6c509c8SHaojian Zhuang #ifdef CONFIG_OF 36032f17997SRobert Jarzmik static int __init __init 36132f17997SRobert Jarzmik pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent) 362089d0362SDaniel Mack { 363089d0362SDaniel Mack __pxa3xx_init_irq(); 364089d0362SDaniel Mack pxa_dt_irq_init(pxa3xx_set_wake); 36532f17997SRobert Jarzmik set_handle_irq(ichp_handle_irq); 36632f17997SRobert Jarzmik 36732f17997SRobert Jarzmik return 0; 368089d0362SDaniel Mack } 36932f17997SRobert Jarzmik IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq); 370e6c509c8SHaojian Zhuang #endif /* CONFIG_OF */ 371089d0362SDaniel Mack 372851982c1SMarek Vasut static struct map_desc pxa3xx_io_desc[] __initdata = { 373851982c1SMarek Vasut { /* Mem Ctl */ 37497b09da4SArnd Bergmann .virtual = (unsigned long)SMEMC_VIRT, 375ad68bb9fSMarek Vasut .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 3760e32986cSLaurent Pinchart .length = SMEMC_SIZE, 377851982c1SMarek Vasut .type = MT_DEVICE 378adf3442cSRobert Jarzmik }, { 379adf3442cSRobert Jarzmik .virtual = (unsigned long)NAND_VIRT, 380adf3442cSRobert Jarzmik .pfn = __phys_to_pfn(NAND_PHYS), 381adf3442cSRobert Jarzmik .length = NAND_SIZE, 382adf3442cSRobert Jarzmik .type = MT_DEVICE 383adf3442cSRobert Jarzmik }, 384851982c1SMarek Vasut }; 385851982c1SMarek Vasut 386851982c1SMarek Vasut void __init pxa3xx_map_io(void) 387851982c1SMarek Vasut { 388851982c1SMarek Vasut pxa_map_io(); 389851982c1SMarek Vasut iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 390851982c1SMarek Vasut pxa3xx_get_clk_frequency_khz(1); 391851982c1SMarek Vasut } 392851982c1SMarek Vasut 3932c8086a5Seric miao /* 3942c8086a5Seric miao * device registration specific to PXA3xx. 3952c8086a5Seric miao */ 3962c8086a5Seric miao 3979ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 3989ba63c4fSMike Rapoport { 39914758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 4009ba63c4fSMike Rapoport } 4019ba63c4fSMike Rapoport 402b8f649f1SHaojian Zhuang static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = { 403b8f649f1SHaojian Zhuang .irq_base = PXA_GPIO_TO_IRQ(0), 404b8f649f1SHaojian Zhuang }; 405b8f649f1SHaojian Zhuang 4062c8086a5Seric miao static struct platform_device *devices[] __initdata = { 40794c35a6bSRobert Jarzmik &pxa27x_device_udc, 40809a5358dSEric Miao &pxa_device_pmu, 4092c8086a5Seric miao &pxa_device_i2s, 410f0fba2adSLiam Girdwood &pxa_device_asoc_ssp1, 411f0fba2adSLiam Girdwood &pxa_device_asoc_ssp2, 412f0fba2adSLiam Girdwood &pxa_device_asoc_ssp3, 413f0fba2adSLiam Girdwood &pxa_device_asoc_ssp4, 414f0fba2adSLiam Girdwood &pxa_device_asoc_platform, 4152c8086a5Seric miao &pxa_device_rtc, 4160da0e227SDaniel Mack &pxa3xx_device_ssp1, 4170da0e227SDaniel Mack &pxa3xx_device_ssp2, 4180da0e227SDaniel Mack &pxa3xx_device_ssp3, 419d8e0db11Seric miao &pxa3xx_device_ssp4, 42075540c1aSeric miao &pxa27x_device_pwm0, 42175540c1aSeric miao &pxa27x_device_pwm1, 4222c8086a5Seric miao }; 4232c8086a5Seric miao 4242c8086a5Seric miao static int __init pxa3xx_init(void) 4252c8086a5Seric miao { 4262eaa03b5SRafael J. Wysocki int ret = 0; 4272c8086a5Seric miao 4282c8086a5Seric miao if (cpu_is_pxa3xx()) { 42904fef228SEric Miao 43004fef228SEric Miao reset_status = ARSR; 43104fef228SEric Miao 43286260f98SDmitry Krivoschekov /* 43386260f98SDmitry Krivoschekov * clear RDH bit every time after reset 43486260f98SDmitry Krivoschekov * 43586260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 43686260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 43786260f98SDmitry Krivoschekov */ 43886260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 43986260f98SDmitry Krivoschekov 440adf3442cSRobert Jarzmik /* 441adf3442cSRobert Jarzmik * Disable DFI bus arbitration, to prevent a system bus lock if 442adf3442cSRobert Jarzmik * somebody disables the NAND clock (unused clock) while this 443adf3442cSRobert Jarzmik * bit remains set. 444adf3442cSRobert Jarzmik */ 445adf3442cSRobert Jarzmik NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL; 446adf3442cSRobert Jarzmik 4477b5dea12SRussell King pxa3xx_init_pm(); 4487b5dea12SRussell King 4492eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa_irq_syscore_ops); 4502eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa3xx_mfp_syscore_ops); 451c0165504Seric miao 4522cab0292SHaojian Zhuang if (of_have_populated_dt()) 4532cab0292SHaojian Zhuang return 0; 4542cab0292SHaojian Zhuang 45572b195cbSRobert Jarzmik pxa2xx_set_dmac_info(32, 100); 456c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 4572cab0292SHaojian Zhuang if (ret) 4582cab0292SHaojian Zhuang return ret; 459b8f649f1SHaojian Zhuang if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) { 460b8f649f1SHaojian Zhuang platform_device_add_data(&pxa3xx_device_gpio, 461b8f649f1SHaojian Zhuang &pxa3xx_gpio_pdata, 462b8f649f1SHaojian Zhuang sizeof(pxa3xx_gpio_pdata)); 4632cab0292SHaojian Zhuang ret = platform_device_register(&pxa3xx_device_gpio); 464c0165504Seric miao } 465b8f649f1SHaojian Zhuang } 466c0165504Seric miao 467c0165504Seric miao return ret; 4682c8086a5Seric miao } 4692c8086a5Seric miao 4701c104e0eSRussell King postcore_initcall(pxa3xx_init); 471