1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22c8086a5Seric miao /* 32c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 42c8086a5Seric miao * 52c8086a5Seric miao * code specific to pxa3xx aka Monahans 62c8086a5Seric miao * 72c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 82c8086a5Seric miao * 9e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 102c8086a5Seric miao * initial version 112c8086a5Seric miao */ 121da10c17SRobert Jarzmik #include <linux/dmaengine.h> 131da10c17SRobert Jarzmik #include <linux/dma/pxa-dma.h> 142c8086a5Seric miao #include <linux/module.h> 152c8086a5Seric miao #include <linux/kernel.h> 162c8086a5Seric miao #include <linux/init.h> 17b8f649f1SHaojian Zhuang #include <linux/gpio-pxa.h> 182c8086a5Seric miao #include <linux/pm.h> 192c8086a5Seric miao #include <linux/platform_device.h> 202c8086a5Seric miao #include <linux/irq.h> 2132f17997SRobert Jarzmik #include <linux/irqchip.h> 227b5dea12SRussell King #include <linux/io.h> 2382ce44d1SDaniel Mack #include <linux/of.h> 242eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 25f15fc9b1SWolfram Sang #include <linux/platform_data/i2c-pxa.h> 261da10c17SRobert Jarzmik #include <linux/platform_data/mmp_dma.h> 2708d3df8cSArnd Bergmann #include <linux/soc/pxa/cpu.h> 28*5c6603e7SArnd Bergmann #include <linux/clk/pxa.h> 292c8086a5Seric miao 30851982c1SMarek Vasut #include <asm/mach/map.h> 312c74a0ceSRussell King #include <asm/suspend.h> 32a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 33afd2fc02SRussell King #include <mach/reset.h> 34293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h> 354c25c5d2SArnd Bergmann #include "pm.h" 36225b5d37SArnd Bergmann #include "addr-map.h" 37ad68bb9fSMarek Vasut #include <mach/smemc.h> 384e611091SRob Herring #include <mach/irqs.h> 392c8086a5Seric miao 402c8086a5Seric miao #include "generic.h" 412c8086a5Seric miao #include "devices.h" 422c8086a5Seric miao 43bf293aecSMike Rapoport #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 44bf293aecSMike Rapoport #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 45bf293aecSMike Rapoport 46089d0362SDaniel Mack extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); 477b5dea12SRussell King 48adf3442cSRobert Jarzmik /* 49adf3442cSRobert Jarzmik * NAND NFC: DFI bus arbitration subset 50adf3442cSRobert Jarzmik */ 51adf3442cSRobert Jarzmik #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0)) 52adf3442cSRobert Jarzmik #define NDCR_ND_ARB_EN (1 << 12) 53adf3442cSRobert Jarzmik #define NDCR_ND_ARB_CNTL (1 << 19) 54adf3442cSRobert Jarzmik 5563910745SArnd Bergmann #ifdef CONFIG_PM 5663910745SArnd Bergmann 5763910745SArnd Bergmann #define ISRAM_START 0x5c000000 5863910745SArnd Bergmann #define ISRAM_SIZE SZ_256K 5963910745SArnd Bergmann 607b5dea12SRussell King static void __iomem *sram; 617b5dea12SRussell King static unsigned long wakeup_src; 627b5dea12SRussell King 637b5dea12SRussell King /* 647b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 657b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 667b5dea12SRussell King * in the SRAM to perform this function. 677b5dea12SRussell King * 687b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 697b5dea12SRussell King * FIQ while the SDRAM is unavailable. 707b5dea12SRussell King */ 717b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 727b5dea12SRussell King { 737b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 747b5dea12SRussell King 757b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 767b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 777b5dea12SRussell King 787b5dea12SRussell King AD2D0SR = ~0; 797b5dea12SRussell King AD2D1SR = ~0; 807b5dea12SRussell King AD2D0ER = wakeup_src; 817b5dea12SRussell King AD2D1ER = 0; 827b5dea12SRussell King ASCR = ASCR; 837b5dea12SRussell King ARSR = ARSR; 847b5dea12SRussell King 857b5dea12SRussell King local_fiq_disable(); 867b5dea12SRussell King fn(pwrmode); 877b5dea12SRussell King local_fiq_enable(); 887b5dea12SRussell King 897b5dea12SRussell King AD2D0ER = 0; 907b5dea12SRussell King AD2D1ER = 0; 917b5dea12SRussell King } 927b5dea12SRussell King 93c4d1fb62Seric miao /* 94c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 95c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 96c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 97c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 98c4d1fb62Seric miao * 0x5c014000 for the moment. 99c4d1fb62Seric miao */ 100c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 101c4d1fb62Seric miao { 102c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 103c4d1fb62Seric miao unsigned long saved_data = *p; 104a9503d21SRussell King #ifndef CONFIG_IWMMXT 105a9503d21SRussell King u64 acc0; 106c4d1fb62Seric miao 107343c1cdbSArnd Bergmann asm volatile(".arch_extension xscale\n\t" 108343c1cdbSArnd Bergmann "mra %Q0, %R0, acc0" : "=r" (acc0)); 109a9503d21SRussell King #endif 110a9503d21SRussell King 111c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 112c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 113c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 114c4d1fb62Seric miao 115c4d1fb62Seric miao /* clear and setup wakeup source */ 116c4d1fb62Seric miao AD3SR = ~0; 117c4d1fb62Seric miao AD3ER = wakeup_src; 118c4d1fb62Seric miao ASCR = ASCR; 119c4d1fb62Seric miao ARSR = ARSR; 120c4d1fb62Seric miao 121c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 122c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 123c4d1fb62Seric miao 124c4d1fb62Seric miao PSPR = 0x5c014000; 125c4d1fb62Seric miao 126c4d1fb62Seric miao /* overwrite with the resume address */ 12764fc2a94SFlorian Fainelli *p = __pa_symbol(cpu_resume); 128c4d1fb62Seric miao 1292c74a0ceSRussell King cpu_suspend(0, pxa3xx_finish_suspend); 130c4d1fb62Seric miao 131c4d1fb62Seric miao *p = saved_data; 132c4d1fb62Seric miao 133c4d1fb62Seric miao AD3ER = 0; 134a9503d21SRussell King 135a9503d21SRussell King #ifndef CONFIG_IWMMXT 136343c1cdbSArnd Bergmann asm volatile(".arch_extension xscale\n\t" 137343c1cdbSArnd Bergmann "mar acc0, %Q0, %R0" : "=r" (acc0)); 138a9503d21SRussell King #endif 139c4d1fb62Seric miao } 140c4d1fb62Seric miao 1417b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 1427b5dea12SRussell King { 1437b5dea12SRussell King /* 1447b5dea12SRussell King * Don't sleep if no wakeup sources are defined 1457b5dea12SRussell King */ 146b86a5da8SMark Brown if (wakeup_src == 0) { 147b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 1487b5dea12SRussell King return; 149b86a5da8SMark Brown } 1507b5dea12SRussell King 1517b5dea12SRussell King switch (state) { 1527b5dea12SRussell King case PM_SUSPEND_STANDBY: 1537b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 1547b5dea12SRussell King break; 1557b5dea12SRussell King 1567b5dea12SRussell King case PM_SUSPEND_MEM: 157c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 1587b5dea12SRussell King break; 1597b5dea12SRussell King } 1607b5dea12SRussell King } 1617b5dea12SRussell King 1627b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 1637b5dea12SRussell King { 1647b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 1657b5dea12SRussell King } 1667b5dea12SRussell King 1677b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 1687b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 1697b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 1707b5dea12SRussell King }; 1717b5dea12SRussell King 1727b5dea12SRussell King static void __init pxa3xx_init_pm(void) 1737b5dea12SRussell King { 1747b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 1757b5dea12SRussell King if (!sram) { 1767b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 1777b5dea12SRussell King return; 1787b5dea12SRussell King } 1797b5dea12SRussell King 1807b5dea12SRussell King /* 1817b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 1827b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 1837b5dea12SRussell King * is undocumented in the developer manual, but must be set. 1847b5dea12SRussell King */ 1857b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 1867b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 1877b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 1887b5dea12SRussell King 1897b5dea12SRussell King /* 1907b5dea12SRussell King * Clear the resume enable registers. 1917b5dea12SRussell King */ 1927b5dea12SRussell King AD1D0ER = 0; 1937b5dea12SRussell King AD2D0ER = 0; 1947b5dea12SRussell King AD2D1ER = 0; 1957b5dea12SRussell King AD3ER = 0; 1967b5dea12SRussell King 1977b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 1987b5dea12SRussell King } 1997b5dea12SRussell King 200a3f4c927SLennert Buytenhek static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 2017b5dea12SRussell King { 2027b5dea12SRussell King unsigned long flags, mask = 0; 2037b5dea12SRussell King 204a3f4c927SLennert Buytenhek switch (d->irq) { 2057b5dea12SRussell King case IRQ_SSP3: 2067b5dea12SRussell King mask = ADXER_MFP_WSSP3; 2077b5dea12SRussell King break; 2087b5dea12SRussell King case IRQ_MSL: 2097b5dea12SRussell King mask = ADXER_WMSL0; 2107b5dea12SRussell King break; 2117b5dea12SRussell King case IRQ_USBH2: 2127b5dea12SRussell King case IRQ_USBH1: 2137b5dea12SRussell King mask = ADXER_WUSBH; 2147b5dea12SRussell King break; 2157b5dea12SRussell King case IRQ_KEYPAD: 2167b5dea12SRussell King mask = ADXER_WKP; 2177b5dea12SRussell King break; 2187b5dea12SRussell King case IRQ_AC97: 2197b5dea12SRussell King mask = ADXER_MFP_WAC97; 2207b5dea12SRussell King break; 2217b5dea12SRussell King case IRQ_USIM: 2227b5dea12SRussell King mask = ADXER_WUSIM0; 2237b5dea12SRussell King break; 2247b5dea12SRussell King case IRQ_SSP2: 2257b5dea12SRussell King mask = ADXER_MFP_WSSP2; 2267b5dea12SRussell King break; 2277b5dea12SRussell King case IRQ_I2C: 2287b5dea12SRussell King mask = ADXER_MFP_WI2C; 2297b5dea12SRussell King break; 2307b5dea12SRussell King case IRQ_STUART: 2317b5dea12SRussell King mask = ADXER_MFP_WUART3; 2327b5dea12SRussell King break; 2337b5dea12SRussell King case IRQ_BTUART: 2347b5dea12SRussell King mask = ADXER_MFP_WUART2; 2357b5dea12SRussell King break; 2367b5dea12SRussell King case IRQ_FFUART: 2377b5dea12SRussell King mask = ADXER_MFP_WUART1; 2387b5dea12SRussell King break; 2397b5dea12SRussell King case IRQ_MMC: 2407b5dea12SRussell King mask = ADXER_MFP_WMMC1; 2417b5dea12SRussell King break; 2427b5dea12SRussell King case IRQ_SSP: 2437b5dea12SRussell King mask = ADXER_MFP_WSSP1; 2447b5dea12SRussell King break; 2457b5dea12SRussell King case IRQ_RTCAlrm: 2467b5dea12SRussell King mask = ADXER_WRTC; 2477b5dea12SRussell King break; 2487b5dea12SRussell King case IRQ_SSP4: 2497b5dea12SRussell King mask = ADXER_MFP_WSSP4; 2507b5dea12SRussell King break; 2517b5dea12SRussell King case IRQ_TSI: 2527b5dea12SRussell King mask = ADXER_WTSI; 2537b5dea12SRussell King break; 2547b5dea12SRussell King case IRQ_USIM2: 2557b5dea12SRussell King mask = ADXER_WUSIM1; 2567b5dea12SRussell King break; 2577b5dea12SRussell King case IRQ_MMC2: 2587b5dea12SRussell King mask = ADXER_MFP_WMMC2; 2597b5dea12SRussell King break; 2607b5dea12SRussell King case IRQ_NAND: 2617b5dea12SRussell King mask = ADXER_MFP_WFLASH; 2627b5dea12SRussell King break; 2637b5dea12SRussell King case IRQ_USB2: 2647b5dea12SRussell King mask = ADXER_WUSB2; 2657b5dea12SRussell King break; 2667b5dea12SRussell King case IRQ_WAKEUP0: 2677b5dea12SRussell King mask = ADXER_WEXTWAKE0; 2687b5dea12SRussell King break; 2697b5dea12SRussell King case IRQ_WAKEUP1: 2707b5dea12SRussell King mask = ADXER_WEXTWAKE1; 2717b5dea12SRussell King break; 2727b5dea12SRussell King case IRQ_MMC3: 2737b5dea12SRussell King mask = ADXER_MFP_GEN12; 2747b5dea12SRussell King break; 275e1217707SMark Brown default: 276e1217707SMark Brown return -EINVAL; 2777b5dea12SRussell King } 2787b5dea12SRussell King 2797b5dea12SRussell King local_irq_save(flags); 2807b5dea12SRussell King if (on) 2817b5dea12SRussell King wakeup_src |= mask; 2827b5dea12SRussell King else 2837b5dea12SRussell King wakeup_src &= ~mask; 2847b5dea12SRussell King local_irq_restore(flags); 2857b5dea12SRussell King 2867b5dea12SRussell King return 0; 2877b5dea12SRussell King } 2887b5dea12SRussell King #else 2897b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 290b9e25aceSeric miao #define pxa3xx_set_wake NULL 2917b5dea12SRussell King #endif 2927b5dea12SRussell King 293a3f4c927SLennert Buytenhek static void pxa_ack_ext_wakeup(struct irq_data *d) 294bf293aecSMike Rapoport { 295a3f4c927SLennert Buytenhek PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 296bf293aecSMike Rapoport } 297bf293aecSMike Rapoport 298a3f4c927SLennert Buytenhek static void pxa_mask_ext_wakeup(struct irq_data *d) 299bf293aecSMike Rapoport { 3005d284e35SEric Miao pxa_mask_irq(d); 301a3f4c927SLennert Buytenhek PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 302bf293aecSMike Rapoport } 303bf293aecSMike Rapoport 304a3f4c927SLennert Buytenhek static void pxa_unmask_ext_wakeup(struct irq_data *d) 305bf293aecSMike Rapoport { 3065d284e35SEric Miao pxa_unmask_irq(d); 307a3f4c927SLennert Buytenhek PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 308bf293aecSMike Rapoport } 309bf293aecSMike Rapoport 310a3f4c927SLennert Buytenhek static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 31112882096SIgor Grinberg { 31212882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_RISING) 313a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0); 31412882096SIgor Grinberg 31512882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_FALLING) 316a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 31712882096SIgor Grinberg 31812882096SIgor Grinberg return 0; 31912882096SIgor Grinberg } 32012882096SIgor Grinberg 321bf293aecSMike Rapoport static struct irq_chip pxa_ext_wakeup_chip = { 322bf293aecSMike Rapoport .name = "WAKEUP", 323a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_ext_wakeup, 324a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_ext_wakeup, 325a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_ext_wakeup, 326a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_ext_wakeup_type, 327bf293aecSMike Rapoport }; 328bf293aecSMike Rapoport 329157d2644SHaojian Zhuang static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, 330157d2644SHaojian Zhuang unsigned int)) 331bf293aecSMike Rapoport { 332bf293aecSMike Rapoport int irq; 333bf293aecSMike Rapoport 334bf293aecSMike Rapoport for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 335f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 336f38c02f3SThomas Gleixner handle_edge_irq); 337e8d36d5dSRob Herring irq_clear_status_flags(irq, IRQ_NOREQUEST); 338bf293aecSMike Rapoport } 339bf293aecSMike Rapoport 340a3f4c927SLennert Buytenhek pxa_ext_wakeup_chip.irq_set_wake = fn; 341bf293aecSMike Rapoport } 342bf293aecSMike Rapoport 343089d0362SDaniel Mack static void __init __pxa3xx_init_irq(void) 3442c8086a5Seric miao { 3452c8086a5Seric miao /* enable CP6 access */ 3462c8086a5Seric miao u32 value; 3472c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 3482c8086a5Seric miao value |= (1 << 6); 3492c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 3502c8086a5Seric miao 351bf293aecSMike Rapoport pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 3522c8086a5Seric miao } 3532c8086a5Seric miao 354089d0362SDaniel Mack void __init pxa3xx_init_irq(void) 355089d0362SDaniel Mack { 356089d0362SDaniel Mack __pxa3xx_init_irq(); 357089d0362SDaniel Mack pxa_init_irq(56, pxa3xx_set_wake); 358089d0362SDaniel Mack } 359089d0362SDaniel Mack 360e6c509c8SHaojian Zhuang #ifdef CONFIG_OF 36132f17997SRobert Jarzmik static int __init __init 36232f17997SRobert Jarzmik pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent) 363089d0362SDaniel Mack { 364089d0362SDaniel Mack __pxa3xx_init_irq(); 365089d0362SDaniel Mack pxa_dt_irq_init(pxa3xx_set_wake); 36632f17997SRobert Jarzmik set_handle_irq(ichp_handle_irq); 36732f17997SRobert Jarzmik 36832f17997SRobert Jarzmik return 0; 369089d0362SDaniel Mack } 37032f17997SRobert Jarzmik IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq); 371e6c509c8SHaojian Zhuang #endif /* CONFIG_OF */ 372089d0362SDaniel Mack 373851982c1SMarek Vasut static struct map_desc pxa3xx_io_desc[] __initdata = { 374851982c1SMarek Vasut { /* Mem Ctl */ 37597b09da4SArnd Bergmann .virtual = (unsigned long)SMEMC_VIRT, 376ad68bb9fSMarek Vasut .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 3770e32986cSLaurent Pinchart .length = SMEMC_SIZE, 378851982c1SMarek Vasut .type = MT_DEVICE 379adf3442cSRobert Jarzmik }, { 380adf3442cSRobert Jarzmik .virtual = (unsigned long)NAND_VIRT, 381adf3442cSRobert Jarzmik .pfn = __phys_to_pfn(NAND_PHYS), 382adf3442cSRobert Jarzmik .length = NAND_SIZE, 383adf3442cSRobert Jarzmik .type = MT_DEVICE 384adf3442cSRobert Jarzmik }, 385851982c1SMarek Vasut }; 386851982c1SMarek Vasut 387851982c1SMarek Vasut void __init pxa3xx_map_io(void) 388851982c1SMarek Vasut { 389851982c1SMarek Vasut pxa_map_io(); 390851982c1SMarek Vasut iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 391851982c1SMarek Vasut pxa3xx_get_clk_frequency_khz(1); 392851982c1SMarek Vasut } 393851982c1SMarek Vasut 3942c8086a5Seric miao /* 3952c8086a5Seric miao * device registration specific to PXA3xx. 3962c8086a5Seric miao */ 3972c8086a5Seric miao 3989ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 3999ba63c4fSMike Rapoport { 40014758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 4019ba63c4fSMike Rapoport } 4029ba63c4fSMike Rapoport 403b8f649f1SHaojian Zhuang static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = { 404b8f649f1SHaojian Zhuang .irq_base = PXA_GPIO_TO_IRQ(0), 405b8f649f1SHaojian Zhuang }; 406b8f649f1SHaojian Zhuang 4072c8086a5Seric miao static struct platform_device *devices[] __initdata = { 40894c35a6bSRobert Jarzmik &pxa27x_device_udc, 40909a5358dSEric Miao &pxa_device_pmu, 4102c8086a5Seric miao &pxa_device_i2s, 411f0fba2adSLiam Girdwood &pxa_device_asoc_ssp1, 412f0fba2adSLiam Girdwood &pxa_device_asoc_ssp2, 413f0fba2adSLiam Girdwood &pxa_device_asoc_ssp3, 414f0fba2adSLiam Girdwood &pxa_device_asoc_ssp4, 415f0fba2adSLiam Girdwood &pxa_device_asoc_platform, 4162c8086a5Seric miao &pxa_device_rtc, 4170da0e227SDaniel Mack &pxa3xx_device_ssp1, 4180da0e227SDaniel Mack &pxa3xx_device_ssp2, 4190da0e227SDaniel Mack &pxa3xx_device_ssp3, 420d8e0db11Seric miao &pxa3xx_device_ssp4, 42175540c1aSeric miao &pxa27x_device_pwm0, 42275540c1aSeric miao &pxa27x_device_pwm1, 4232c8086a5Seric miao }; 4242c8086a5Seric miao 4251da10c17SRobert Jarzmik static const struct dma_slave_map pxa3xx_slave_map[] = { 4261da10c17SRobert Jarzmik /* PXA25x, PXA27x and PXA3xx common entries */ 4271da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) }, 4281da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) }, 4291da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_aux_mono_out", 4301da10c17SRobert Jarzmik PDMA_FILTER_PARAM(LOWEST, 10) }, 4311da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) }, 4321da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) }, 4331da10c17SRobert Jarzmik { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) }, 4341da10c17SRobert Jarzmik { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) }, 4351da10c17SRobert Jarzmik { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) }, 4361da10c17SRobert Jarzmik { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) }, 4371da10c17SRobert Jarzmik { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) }, 4381da10c17SRobert Jarzmik { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) }, 4391da10c17SRobert Jarzmik { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) }, 4401da10c17SRobert Jarzmik { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) }, 4411da10c17SRobert Jarzmik { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) }, 4421da10c17SRobert Jarzmik { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) }, 4431da10c17SRobert Jarzmik 4441da10c17SRobert Jarzmik /* PXA3xx specific map */ 4451da10c17SRobert Jarzmik { "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) }, 4461da10c17SRobert Jarzmik { "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) }, 4471da10c17SRobert Jarzmik { "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) }, 4481da10c17SRobert Jarzmik { "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) }, 4491da10c17SRobert Jarzmik { "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) }, 4501da10c17SRobert Jarzmik { "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) }, 4511da10c17SRobert Jarzmik { "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) }, 4521da10c17SRobert Jarzmik }; 4531da10c17SRobert Jarzmik 4541da10c17SRobert Jarzmik static struct mmp_dma_platdata pxa3xx_dma_pdata = { 4551da10c17SRobert Jarzmik .dma_channels = 32, 4561da10c17SRobert Jarzmik .nb_requestors = 100, 4571da10c17SRobert Jarzmik .slave_map = pxa3xx_slave_map, 4581da10c17SRobert Jarzmik .slave_map_cnt = ARRAY_SIZE(pxa3xx_slave_map), 4591da10c17SRobert Jarzmik }; 4601da10c17SRobert Jarzmik 4612c8086a5Seric miao static int __init pxa3xx_init(void) 4622c8086a5Seric miao { 4632eaa03b5SRafael J. Wysocki int ret = 0; 4642c8086a5Seric miao 4652c8086a5Seric miao if (cpu_is_pxa3xx()) { 46604fef228SEric Miao 467e86bd43bSArnd Bergmann pxa_register_wdt(ARSR); 46804fef228SEric Miao 46986260f98SDmitry Krivoschekov /* 47086260f98SDmitry Krivoschekov * clear RDH bit every time after reset 47186260f98SDmitry Krivoschekov * 47286260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 47386260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 47486260f98SDmitry Krivoschekov */ 47586260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 47686260f98SDmitry Krivoschekov 477adf3442cSRobert Jarzmik /* 478adf3442cSRobert Jarzmik * Disable DFI bus arbitration, to prevent a system bus lock if 479adf3442cSRobert Jarzmik * somebody disables the NAND clock (unused clock) while this 480adf3442cSRobert Jarzmik * bit remains set. 481adf3442cSRobert Jarzmik */ 482adf3442cSRobert Jarzmik NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL; 483adf3442cSRobert Jarzmik 4847b5dea12SRussell King pxa3xx_init_pm(); 4857b5dea12SRussell King 486c1c14f89SDaniel Mack enable_irq_wake(IRQ_WAKEUP0); 487c1c14f89SDaniel Mack if (cpu_is_pxa320()) 488c1c14f89SDaniel Mack enable_irq_wake(IRQ_WAKEUP1); 489c1c14f89SDaniel Mack 4902eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa_irq_syscore_ops); 4912eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa3xx_mfp_syscore_ops); 492c0165504Seric miao 4932cab0292SHaojian Zhuang if (of_have_populated_dt()) 4942cab0292SHaojian Zhuang return 0; 4952cab0292SHaojian Zhuang 4961da10c17SRobert Jarzmik pxa2xx_set_dmac_info(&pxa3xx_dma_pdata); 497c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 4982cab0292SHaojian Zhuang if (ret) 4992cab0292SHaojian Zhuang return ret; 500b8f649f1SHaojian Zhuang if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) { 501b8f649f1SHaojian Zhuang platform_device_add_data(&pxa3xx_device_gpio, 502b8f649f1SHaojian Zhuang &pxa3xx_gpio_pdata, 503b8f649f1SHaojian Zhuang sizeof(pxa3xx_gpio_pdata)); 5042cab0292SHaojian Zhuang ret = platform_device_register(&pxa3xx_device_gpio); 505c0165504Seric miao } 506b8f649f1SHaojian Zhuang } 507c0165504Seric miao 508c0165504Seric miao return ret; 5092c8086a5Seric miao } 5102c8086a5Seric miao 5111c104e0eSRussell King postcore_initcall(pxa3xx_init); 512