12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao 162c8086a5Seric miao #include <linux/module.h> 172c8086a5Seric miao #include <linux/kernel.h> 182c8086a5Seric miao #include <linux/init.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 227b5dea12SRussell King #include <linux/io.h> 23c0165504Seric miao #include <linux/sysdev.h> 242c8086a5Seric miao 252c8086a5Seric miao #include <asm/hardware.h> 262c8086a5Seric miao #include <asm/arch/pxa3xx-regs.h> 272c8086a5Seric miao #include <asm/arch/ohci.h> 282c8086a5Seric miao #include <asm/arch/pm.h> 292c8086a5Seric miao #include <asm/arch/dma.h> 302c8086a5Seric miao #include <asm/arch/ssp.h> 312c8086a5Seric miao 322c8086a5Seric miao #include "generic.h" 332c8086a5Seric miao #include "devices.h" 342c8086a5Seric miao #include "clock.h" 352c8086a5Seric miao 362c8086a5Seric miao /* Crystal clock: 13MHz */ 372c8086a5Seric miao #define BASE_CLK 13000000 382c8086a5Seric miao 392c8086a5Seric miao /* Ring Oscillator Clock: 60MHz */ 402c8086a5Seric miao #define RO_CLK 60000000 412c8086a5Seric miao 422c8086a5Seric miao #define ACCR_D0CS (1 << 26) 43c4d1fb62Seric miao #define ACCR_PCCE (1 << 11) 442c8086a5Seric miao 452c8086a5Seric miao /* crystal frequency to static memory controller multiplier (SMCFS) */ 462c8086a5Seric miao static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 472c8086a5Seric miao 482c8086a5Seric miao /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 492c8086a5Seric miao static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 502c8086a5Seric miao 512c8086a5Seric miao /* 522c8086a5Seric miao * Get the clock frequency as reflected by CCSR and the turbo flag. 532c8086a5Seric miao * We assume these values have been applied via a fcs. 542c8086a5Seric miao * If info is not 0 we also display the current settings. 552c8086a5Seric miao */ 562c8086a5Seric miao unsigned int pxa3xx_get_clk_frequency_khz(int info) 572c8086a5Seric miao { 582c8086a5Seric miao unsigned long acsr, xclkcfg; 592c8086a5Seric miao unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 602c8086a5Seric miao 612c8086a5Seric miao /* Read XCLKCFG register turbo bit */ 622c8086a5Seric miao __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 632c8086a5Seric miao t = xclkcfg & 0x1; 642c8086a5Seric miao 652c8086a5Seric miao acsr = ACSR; 662c8086a5Seric miao 672c8086a5Seric miao xl = acsr & 0x1f; 682c8086a5Seric miao xn = (acsr >> 8) & 0x7; 692c8086a5Seric miao hss = (acsr >> 14) & 0x3; 702c8086a5Seric miao 712c8086a5Seric miao XL = xl * BASE_CLK; 722c8086a5Seric miao XN = xn * XL; 732c8086a5Seric miao 742c8086a5Seric miao ro = acsr & ACCR_D0CS; 752c8086a5Seric miao 762c8086a5Seric miao CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 772c8086a5Seric miao HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 782c8086a5Seric miao 792c8086a5Seric miao if (info) { 802c8086a5Seric miao pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 812c8086a5Seric miao RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 822c8086a5Seric miao (ro) ? "" : "in"); 832c8086a5Seric miao pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 842c8086a5Seric miao XL / 1000000, (XL % 1000000) / 10000, xl); 852c8086a5Seric miao pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 862c8086a5Seric miao XN / 1000000, (XN % 1000000) / 10000, xn, 872c8086a5Seric miao (t) ? "" : "in"); 882c8086a5Seric miao pr_info("HSIO bus clock: %d.%02dMHz\n", 892c8086a5Seric miao HSS / 1000000, (HSS % 1000000) / 10000); 902c8086a5Seric miao } 912c8086a5Seric miao 926232be32Seric miao return CLK / 1000; 932c8086a5Seric miao } 942c8086a5Seric miao 952c8086a5Seric miao /* 962c8086a5Seric miao * Return the current static memory controller clock frequency 972c8086a5Seric miao * in units of 10kHz 982c8086a5Seric miao */ 992c8086a5Seric miao unsigned int pxa3xx_get_memclk_frequency_10khz(void) 1002c8086a5Seric miao { 1012c8086a5Seric miao unsigned long acsr; 1022c8086a5Seric miao unsigned int smcfs, clk = 0; 1032c8086a5Seric miao 1042c8086a5Seric miao acsr = ACSR; 1052c8086a5Seric miao 1062c8086a5Seric miao smcfs = (acsr >> 23) & 0x7; 1072c8086a5Seric miao clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 1082c8086a5Seric miao 1092c8086a5Seric miao return (clk / 10000); 1102c8086a5Seric miao } 1112c8086a5Seric miao 1122c8086a5Seric miao /* 11360bfe7faSMark Brown * Return the current AC97 clock frequency. 11460bfe7faSMark Brown */ 11560bfe7faSMark Brown static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 11660bfe7faSMark Brown { 11760bfe7faSMark Brown unsigned long rate = 312000000; 11860bfe7faSMark Brown unsigned long ac97_div; 11960bfe7faSMark Brown 12060bfe7faSMark Brown ac97_div = AC97_DIV; 12160bfe7faSMark Brown 12260bfe7faSMark Brown /* This may loose precision for some rates but won't for the 12360bfe7faSMark Brown * standard 24.576MHz. 12460bfe7faSMark Brown */ 12560bfe7faSMark Brown rate /= (ac97_div >> 12) & 0x7fff; 12660bfe7faSMark Brown rate *= (ac97_div & 0xfff); 12760bfe7faSMark Brown 12860bfe7faSMark Brown return rate; 12960bfe7faSMark Brown } 13060bfe7faSMark Brown 13160bfe7faSMark Brown /* 1322c8086a5Seric miao * Return the current HSIO bus clock frequency 1332c8086a5Seric miao */ 1342c8086a5Seric miao static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 1352c8086a5Seric miao { 1362c8086a5Seric miao unsigned long acsr; 1372c8086a5Seric miao unsigned int hss, hsio_clk; 1382c8086a5Seric miao 1392c8086a5Seric miao acsr = ACSR; 1402c8086a5Seric miao 1412c8086a5Seric miao hss = (acsr >> 14) & 0x3; 1422c8086a5Seric miao hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 1432c8086a5Seric miao 1442c8086a5Seric miao return hsio_clk; 1452c8086a5Seric miao } 1462c8086a5Seric miao 1472c8086a5Seric miao static void clk_pxa3xx_cken_enable(struct clk *clk) 1482c8086a5Seric miao { 1492c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1502c8086a5Seric miao 1512c8086a5Seric miao if (clk->cken < 32) 1522c8086a5Seric miao CKENA |= mask; 1532c8086a5Seric miao else 1542c8086a5Seric miao CKENB |= mask; 1552c8086a5Seric miao } 1562c8086a5Seric miao 1572c8086a5Seric miao static void clk_pxa3xx_cken_disable(struct clk *clk) 1582c8086a5Seric miao { 1592c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1602c8086a5Seric miao 1612c8086a5Seric miao if (clk->cken < 32) 1622c8086a5Seric miao CKENA &= ~mask; 1632c8086a5Seric miao else 1642c8086a5Seric miao CKENB &= ~mask; 1652c8086a5Seric miao } 1662c8086a5Seric miao 1672a0d7187Seric miao static const struct clkops clk_pxa3xx_cken_ops = { 1682a0d7187Seric miao .enable = clk_pxa3xx_cken_enable, 1692a0d7187Seric miao .disable = clk_pxa3xx_cken_disable, 1702a0d7187Seric miao }; 1712a0d7187Seric miao 1722c8086a5Seric miao static const struct clkops clk_pxa3xx_hsio_ops = { 1732c8086a5Seric miao .enable = clk_pxa3xx_cken_enable, 1742c8086a5Seric miao .disable = clk_pxa3xx_cken_disable, 1752c8086a5Seric miao .getrate = clk_pxa3xx_hsio_getrate, 1762c8086a5Seric miao }; 1772c8086a5Seric miao 17860bfe7faSMark Brown static const struct clkops clk_pxa3xx_ac97_ops = { 17960bfe7faSMark Brown .enable = clk_pxa3xx_cken_enable, 18060bfe7faSMark Brown .disable = clk_pxa3xx_cken_disable, 18160bfe7faSMark Brown .getrate = clk_pxa3xx_ac97_getrate, 18260bfe7faSMark Brown }; 18360bfe7faSMark Brown 184dcc88a17SMark Brown static void clk_pout_enable(struct clk *clk) 185dcc88a17SMark Brown { 186dcc88a17SMark Brown OSCC |= OSCC_PEN; 187dcc88a17SMark Brown } 188dcc88a17SMark Brown 189dcc88a17SMark Brown static void clk_pout_disable(struct clk *clk) 190dcc88a17SMark Brown { 191dcc88a17SMark Brown OSCC &= ~OSCC_PEN; 192dcc88a17SMark Brown } 193dcc88a17SMark Brown 194dcc88a17SMark Brown static const struct clkops clk_pout_ops = { 195dcc88a17SMark Brown .enable = clk_pout_enable, 196dcc88a17SMark Brown .disable = clk_pout_disable, 197dcc88a17SMark Brown }; 198dcc88a17SMark Brown 1992a0d7187Seric miao #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ 2002a0d7187Seric miao { \ 2012a0d7187Seric miao .name = _name, \ 2022a0d7187Seric miao .dev = _dev, \ 2032a0d7187Seric miao .ops = &clk_pxa3xx_cken_ops, \ 2042a0d7187Seric miao .rate = _rate, \ 2052a0d7187Seric miao .cken = CKEN_##_cken, \ 2062a0d7187Seric miao .delay = _delay, \ 2072a0d7187Seric miao } 2082a0d7187Seric miao 2092a0d7187Seric miao #define PXA3xx_CK(_name, _cken, _ops, _dev) \ 2102a0d7187Seric miao { \ 2112a0d7187Seric miao .name = _name, \ 2122a0d7187Seric miao .dev = _dev, \ 2132a0d7187Seric miao .ops = _ops, \ 2142a0d7187Seric miao .cken = CKEN_##_cken, \ 2152a0d7187Seric miao } 2162a0d7187Seric miao 2172c8086a5Seric miao static struct clk pxa3xx_clks[] = { 218dcc88a17SMark Brown { 219dcc88a17SMark Brown .name = "CLK_POUT", 220dcc88a17SMark Brown .ops = &clk_pout_ops, 221dcc88a17SMark Brown .rate = 13000000, 222dcc88a17SMark Brown .delay = 70, 223dcc88a17SMark Brown }, 224dcc88a17SMark Brown 2252a0d7187Seric miao PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 2262a0d7187Seric miao PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 22760bfe7faSMark Brown PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), 2282c8086a5Seric miao 2292a0d7187Seric miao PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 2302a0d7187Seric miao PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 2312a0d7187Seric miao PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 2322c8086a5Seric miao 2332a0d7187Seric miao PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 2342a0d7187Seric miao PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), 235f92a629cSeric miao PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 236d8e0db11Seric miao 237d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 238d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 239d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 240d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 241fafc9d3fSBridge Wu 242fafc9d3fSBridge Wu PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 2438d33b055SBridge Wu PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 2445a1f21b1SBridge Wu PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), 2452c8086a5Seric miao }; 2462c8086a5Seric miao 2477b5dea12SRussell King #ifdef CONFIG_PM 2487b5dea12SRussell King 2497b5dea12SRussell King #define ISRAM_START 0x5c000000 2507b5dea12SRussell King #define ISRAM_SIZE SZ_256K 2517b5dea12SRussell King 2527b5dea12SRussell King static void __iomem *sram; 2537b5dea12SRussell King static unsigned long wakeup_src; 2547b5dea12SRussell King 255c4d1fb62Seric miao #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 256c4d1fb62Seric miao #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 257c4d1fb62Seric miao 258c4d1fb62Seric miao enum { SLEEP_SAVE_START = 0, 259c4d1fb62Seric miao SLEEP_SAVE_CKENA, 260c4d1fb62Seric miao SLEEP_SAVE_CKENB, 261c4d1fb62Seric miao SLEEP_SAVE_ACCR, 262c4d1fb62Seric miao 263c4d1fb62Seric miao SLEEP_SAVE_SIZE, 264c4d1fb62Seric miao }; 265c4d1fb62Seric miao 2667b5dea12SRussell King static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 2677b5dea12SRussell King { 268c4d1fb62Seric miao SAVE(CKENA); 269c4d1fb62Seric miao SAVE(CKENB); 270c4d1fb62Seric miao SAVE(ACCR); 2717b5dea12SRussell King } 2727b5dea12SRussell King 2737b5dea12SRussell King static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 2747b5dea12SRussell King { 275c4d1fb62Seric miao RESTORE(ACCR); 276c4d1fb62Seric miao RESTORE(CKENA); 277c4d1fb62Seric miao RESTORE(CKENB); 2787b5dea12SRussell King } 2797b5dea12SRussell King 2807b5dea12SRussell King /* 2817b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 2827b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 2837b5dea12SRussell King * in the SRAM to perform this function. 2847b5dea12SRussell King * 2857b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 2867b5dea12SRussell King * FIQ while the SDRAM is unavailable. 2877b5dea12SRussell King */ 2887b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 2897b5dea12SRussell King { 2907b5dea12SRussell King extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 2917b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 2927b5dea12SRussell King 2937b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 2947b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 2957b5dea12SRussell King 2967b5dea12SRussell King AD2D0SR = ~0; 2977b5dea12SRussell King AD2D1SR = ~0; 2987b5dea12SRussell King AD2D0ER = wakeup_src; 2997b5dea12SRussell King AD2D1ER = 0; 3007b5dea12SRussell King ASCR = ASCR; 3017b5dea12SRussell King ARSR = ARSR; 3027b5dea12SRussell King 3037b5dea12SRussell King local_fiq_disable(); 3047b5dea12SRussell King fn(pwrmode); 3057b5dea12SRussell King local_fiq_enable(); 3067b5dea12SRussell King 3077b5dea12SRussell King AD2D0ER = 0; 3087b5dea12SRussell King AD2D1ER = 0; 3097b5dea12SRussell King } 3107b5dea12SRussell King 311c4d1fb62Seric miao /* 312c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 313c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 314c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 315c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 316c4d1fb62Seric miao * 0x5c014000 for the moment. 317c4d1fb62Seric miao */ 318c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 319c4d1fb62Seric miao { 320c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 321c4d1fb62Seric miao unsigned long saved_data = *p; 322c4d1fb62Seric miao 323c4d1fb62Seric miao extern void pxa3xx_cpu_suspend(void); 324c4d1fb62Seric miao extern void pxa3xx_cpu_resume(void); 325c4d1fb62Seric miao 326c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 327c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 328c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 329c4d1fb62Seric miao 330c4d1fb62Seric miao /* clear and setup wakeup source */ 331c4d1fb62Seric miao AD3SR = ~0; 332c4d1fb62Seric miao AD3ER = wakeup_src; 333c4d1fb62Seric miao ASCR = ASCR; 334c4d1fb62Seric miao ARSR = ARSR; 335c4d1fb62Seric miao 336c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 337c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 338c4d1fb62Seric miao 339c4d1fb62Seric miao PSPR = 0x5c014000; 340c4d1fb62Seric miao 341c4d1fb62Seric miao /* overwrite with the resume address */ 342c4d1fb62Seric miao *p = virt_to_phys(pxa3xx_cpu_resume); 343c4d1fb62Seric miao 344c4d1fb62Seric miao pxa3xx_cpu_suspend(); 345c4d1fb62Seric miao 346c4d1fb62Seric miao *p = saved_data; 347c4d1fb62Seric miao 348c4d1fb62Seric miao AD3ER = 0; 349c4d1fb62Seric miao } 350c4d1fb62Seric miao 3517b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 3527b5dea12SRussell King { 3537b5dea12SRussell King /* 3547b5dea12SRussell King * Don't sleep if no wakeup sources are defined 3557b5dea12SRussell King */ 3567b5dea12SRussell King if (wakeup_src == 0) 3577b5dea12SRussell King return; 3587b5dea12SRussell King 3597b5dea12SRussell King switch (state) { 3607b5dea12SRussell King case PM_SUSPEND_STANDBY: 3617b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 3627b5dea12SRussell King break; 3637b5dea12SRussell King 3647b5dea12SRussell King case PM_SUSPEND_MEM: 365c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 3667b5dea12SRussell King break; 3677b5dea12SRussell King } 3687b5dea12SRussell King } 3697b5dea12SRussell King 3707b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 3717b5dea12SRussell King { 3727b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 3737b5dea12SRussell King } 3747b5dea12SRussell King 3757b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 3767b5dea12SRussell King .save_size = SLEEP_SAVE_SIZE, 3777b5dea12SRussell King .save = pxa3xx_cpu_pm_save, 3787b5dea12SRussell King .restore = pxa3xx_cpu_pm_restore, 3797b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 3807b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 3817b5dea12SRussell King }; 3827b5dea12SRussell King 3837b5dea12SRussell King static void __init pxa3xx_init_pm(void) 3847b5dea12SRussell King { 3857b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 3867b5dea12SRussell King if (!sram) { 3877b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 3887b5dea12SRussell King return; 3897b5dea12SRussell King } 3907b5dea12SRussell King 3917b5dea12SRussell King /* 3927b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 3937b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 3947b5dea12SRussell King * is undocumented in the developer manual, but must be set. 3957b5dea12SRussell King */ 3967b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 3977b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 3987b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 3997b5dea12SRussell King 4007b5dea12SRussell King /* 4017b5dea12SRussell King * Clear the resume enable registers. 4027b5dea12SRussell King */ 4037b5dea12SRussell King AD1D0ER = 0; 4047b5dea12SRussell King AD2D0ER = 0; 4057b5dea12SRussell King AD2D1ER = 0; 4067b5dea12SRussell King AD3ER = 0; 4077b5dea12SRussell King 4087b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 4097b5dea12SRussell King } 4107b5dea12SRussell King 4117b5dea12SRussell King static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 4127b5dea12SRussell King { 4137b5dea12SRussell King unsigned long flags, mask = 0; 4147b5dea12SRussell King 4157b5dea12SRussell King switch (irq) { 4167b5dea12SRussell King case IRQ_SSP3: 4177b5dea12SRussell King mask = ADXER_MFP_WSSP3; 4187b5dea12SRussell King break; 4197b5dea12SRussell King case IRQ_MSL: 4207b5dea12SRussell King mask = ADXER_WMSL0; 4217b5dea12SRussell King break; 4227b5dea12SRussell King case IRQ_USBH2: 4237b5dea12SRussell King case IRQ_USBH1: 4247b5dea12SRussell King mask = ADXER_WUSBH; 4257b5dea12SRussell King break; 4267b5dea12SRussell King case IRQ_KEYPAD: 4277b5dea12SRussell King mask = ADXER_WKP; 4287b5dea12SRussell King break; 4297b5dea12SRussell King case IRQ_AC97: 4307b5dea12SRussell King mask = ADXER_MFP_WAC97; 4317b5dea12SRussell King break; 4327b5dea12SRussell King case IRQ_USIM: 4337b5dea12SRussell King mask = ADXER_WUSIM0; 4347b5dea12SRussell King break; 4357b5dea12SRussell King case IRQ_SSP2: 4367b5dea12SRussell King mask = ADXER_MFP_WSSP2; 4377b5dea12SRussell King break; 4387b5dea12SRussell King case IRQ_I2C: 4397b5dea12SRussell King mask = ADXER_MFP_WI2C; 4407b5dea12SRussell King break; 4417b5dea12SRussell King case IRQ_STUART: 4427b5dea12SRussell King mask = ADXER_MFP_WUART3; 4437b5dea12SRussell King break; 4447b5dea12SRussell King case IRQ_BTUART: 4457b5dea12SRussell King mask = ADXER_MFP_WUART2; 4467b5dea12SRussell King break; 4477b5dea12SRussell King case IRQ_FFUART: 4487b5dea12SRussell King mask = ADXER_MFP_WUART1; 4497b5dea12SRussell King break; 4507b5dea12SRussell King case IRQ_MMC: 4517b5dea12SRussell King mask = ADXER_MFP_WMMC1; 4527b5dea12SRussell King break; 4537b5dea12SRussell King case IRQ_SSP: 4547b5dea12SRussell King mask = ADXER_MFP_WSSP1; 4557b5dea12SRussell King break; 4567b5dea12SRussell King case IRQ_RTCAlrm: 4577b5dea12SRussell King mask = ADXER_WRTC; 4587b5dea12SRussell King break; 4597b5dea12SRussell King case IRQ_SSP4: 4607b5dea12SRussell King mask = ADXER_MFP_WSSP4; 4617b5dea12SRussell King break; 4627b5dea12SRussell King case IRQ_TSI: 4637b5dea12SRussell King mask = ADXER_WTSI; 4647b5dea12SRussell King break; 4657b5dea12SRussell King case IRQ_USIM2: 4667b5dea12SRussell King mask = ADXER_WUSIM1; 4677b5dea12SRussell King break; 4687b5dea12SRussell King case IRQ_MMC2: 4697b5dea12SRussell King mask = ADXER_MFP_WMMC2; 4707b5dea12SRussell King break; 4717b5dea12SRussell King case IRQ_NAND: 4727b5dea12SRussell King mask = ADXER_MFP_WFLASH; 4737b5dea12SRussell King break; 4747b5dea12SRussell King case IRQ_USB2: 4757b5dea12SRussell King mask = ADXER_WUSB2; 4767b5dea12SRussell King break; 4777b5dea12SRussell King case IRQ_WAKEUP0: 4787b5dea12SRussell King mask = ADXER_WEXTWAKE0; 4797b5dea12SRussell King break; 4807b5dea12SRussell King case IRQ_WAKEUP1: 4817b5dea12SRussell King mask = ADXER_WEXTWAKE1; 4827b5dea12SRussell King break; 4837b5dea12SRussell King case IRQ_MMC3: 4847b5dea12SRussell King mask = ADXER_MFP_GEN12; 4857b5dea12SRussell King break; 4867b5dea12SRussell King } 4877b5dea12SRussell King 4887b5dea12SRussell King local_irq_save(flags); 4897b5dea12SRussell King if (on) 4907b5dea12SRussell King wakeup_src |= mask; 4917b5dea12SRussell King else 4927b5dea12SRussell King wakeup_src &= ~mask; 4937b5dea12SRussell King local_irq_restore(flags); 4947b5dea12SRussell King 4957b5dea12SRussell King return 0; 4967b5dea12SRussell King } 4977b5dea12SRussell King #else 4987b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 499b9e25aceSeric miao #define pxa3xx_set_wake NULL 5007b5dea12SRussell King #endif 5017b5dea12SRussell King 5022c8086a5Seric miao void __init pxa3xx_init_irq(void) 5032c8086a5Seric miao { 5042c8086a5Seric miao /* enable CP6 access */ 5052c8086a5Seric miao u32 value; 5062c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 5072c8086a5Seric miao value |= (1 << 6); 5082c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 5092c8086a5Seric miao 510b9e25aceSeric miao pxa_init_irq(56, pxa3xx_set_wake); 511b9e25aceSeric miao pxa_init_gpio(128, NULL); 5122c8086a5Seric miao } 5132c8086a5Seric miao 5142c8086a5Seric miao /* 5152c8086a5Seric miao * device registration specific to PXA3xx. 5162c8086a5Seric miao */ 5172c8086a5Seric miao 5182c8086a5Seric miao static struct platform_device *devices[] __initdata = { 5192c8086a5Seric miao &pxa_device_udc, 5202c8086a5Seric miao &pxa_device_ffuart, 5212c8086a5Seric miao &pxa_device_btuart, 5222c8086a5Seric miao &pxa_device_stuart, 5232c8086a5Seric miao &pxa_device_i2s, 5242c8086a5Seric miao &pxa_device_rtc, 525d8e0db11Seric miao &pxa27x_device_ssp1, 526d8e0db11Seric miao &pxa27x_device_ssp2, 527d8e0db11Seric miao &pxa27x_device_ssp3, 528d8e0db11Seric miao &pxa3xx_device_ssp4, 5292c8086a5Seric miao }; 5302c8086a5Seric miao 531c0165504Seric miao static struct sys_device pxa3xx_sysdev[] = { 532c0165504Seric miao { 533c0165504Seric miao .cls = &pxa_irq_sysclass, 53416dfdbf0Seric miao }, { 5354be35e23Seric miao .cls = &pxa3xx_mfp_sysclass, 5364be35e23Seric miao }, { 53716dfdbf0Seric miao .cls = &pxa_gpio_sysclass, 538c0165504Seric miao }, 539c0165504Seric miao }; 540c0165504Seric miao 5412c8086a5Seric miao static int __init pxa3xx_init(void) 5422c8086a5Seric miao { 543c0165504Seric miao int i, ret = 0; 5442c8086a5Seric miao 5452c8086a5Seric miao if (cpu_is_pxa3xx()) { 54686260f98SDmitry Krivoschekov /* 54786260f98SDmitry Krivoschekov * clear RDH bit every time after reset 54886260f98SDmitry Krivoschekov * 54986260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 55086260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 55186260f98SDmitry Krivoschekov */ 55286260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 55386260f98SDmitry Krivoschekov 5542c8086a5Seric miao clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 5552c8086a5Seric miao 5562c8086a5Seric miao if ((ret = pxa_init_dma(32))) 5572c8086a5Seric miao return ret; 5582c8086a5Seric miao 5597b5dea12SRussell King pxa3xx_init_pm(); 5607b5dea12SRussell King 561c0165504Seric miao for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 562c0165504Seric miao ret = sysdev_register(&pxa3xx_sysdev[i]); 563c0165504Seric miao if (ret) 564c0165504Seric miao pr_err("failed to register sysdev[%d]\n", i); 5652c8086a5Seric miao } 566c0165504Seric miao 567c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 568c0165504Seric miao } 569c0165504Seric miao 570c0165504Seric miao return ret; 5712c8086a5Seric miao } 5722c8086a5Seric miao 5732c8086a5Seric miao subsys_initcall(pxa3xx_init); 574