1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22c8086a5Seric miao /* 32c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 42c8086a5Seric miao * 52c8086a5Seric miao * code specific to pxa3xx aka Monahans 62c8086a5Seric miao * 72c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 82c8086a5Seric miao * 9e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 102c8086a5Seric miao * initial version 112c8086a5Seric miao */ 121da10c17SRobert Jarzmik #include <linux/dmaengine.h> 131da10c17SRobert Jarzmik #include <linux/dma/pxa-dma.h> 142c8086a5Seric miao #include <linux/module.h> 152c8086a5Seric miao #include <linux/kernel.h> 162c8086a5Seric miao #include <linux/init.h> 17b8f649f1SHaojian Zhuang #include <linux/gpio-pxa.h> 182c8086a5Seric miao #include <linux/pm.h> 192c8086a5Seric miao #include <linux/platform_device.h> 202c8086a5Seric miao #include <linux/irq.h> 2132f17997SRobert Jarzmik #include <linux/irqchip.h> 227b5dea12SRussell King #include <linux/io.h> 2382ce44d1SDaniel Mack #include <linux/of.h> 242eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 25f15fc9b1SWolfram Sang #include <linux/platform_data/i2c-pxa.h> 261da10c17SRobert Jarzmik #include <linux/platform_data/mmp_dma.h> 2708d3df8cSArnd Bergmann #include <linux/soc/pxa/cpu.h> 285c6603e7SArnd Bergmann #include <linux/clk/pxa.h> 292c8086a5Seric miao 30851982c1SMarek Vasut #include <asm/mach/map.h> 312c74a0ceSRussell King #include <asm/suspend.h> 32e6acc406SArnd Bergmann #include "pxa3xx-regs.h" 33e6acc406SArnd Bergmann #include "reset.h" 34293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h> 354c25c5d2SArnd Bergmann #include "pm.h" 36225b5d37SArnd Bergmann #include "addr-map.h" 37e6acc406SArnd Bergmann #include "smemc.h" 38e6acc406SArnd Bergmann #include "irqs.h" 392c8086a5Seric miao 402c8086a5Seric miao #include "generic.h" 412c8086a5Seric miao #include "devices.h" 422c8086a5Seric miao 43bf293aecSMike Rapoport #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 44bf293aecSMike Rapoport #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 45bf293aecSMike Rapoport 46089d0362SDaniel Mack extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); 477b5dea12SRussell King 48adf3442cSRobert Jarzmik /* 49adf3442cSRobert Jarzmik * NAND NFC: DFI bus arbitration subset 50adf3442cSRobert Jarzmik */ 51adf3442cSRobert Jarzmik #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0)) 52adf3442cSRobert Jarzmik #define NDCR_ND_ARB_EN (1 << 12) 53adf3442cSRobert Jarzmik #define NDCR_ND_ARB_CNTL (1 << 19) 54adf3442cSRobert Jarzmik 55fd13f811SArnd Bergmann #define CKEN_BOOT 11 /* < Boot rom clock enable */ 56fd13f811SArnd Bergmann #define CKEN_TPM 19 /* < TPM clock enable */ 57fd13f811SArnd Bergmann #define CKEN_HSIO2 41 /* < HSIO2 clock enable */ 58fd13f811SArnd Bergmann 5963910745SArnd Bergmann #ifdef CONFIG_PM 6063910745SArnd Bergmann 6163910745SArnd Bergmann #define ISRAM_START 0x5c000000 6263910745SArnd Bergmann #define ISRAM_SIZE SZ_256K 6363910745SArnd Bergmann 647b5dea12SRussell King static void __iomem *sram; 657b5dea12SRussell King static unsigned long wakeup_src; 667b5dea12SRussell King 677b5dea12SRussell King /* 687b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 697b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 707b5dea12SRussell King * in the SRAM to perform this function. 717b5dea12SRussell King * 727b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 737b5dea12SRussell King * FIQ while the SDRAM is unavailable. 747b5dea12SRussell King */ 757b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 767b5dea12SRussell King { 777b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 787b5dea12SRussell King 797b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 807b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 817b5dea12SRussell King 827b5dea12SRussell King AD2D0SR = ~0; 837b5dea12SRussell King AD2D1SR = ~0; 847b5dea12SRussell King AD2D0ER = wakeup_src; 857b5dea12SRussell King AD2D1ER = 0; 867b5dea12SRussell King ASCR = ASCR; 877b5dea12SRussell King ARSR = ARSR; 887b5dea12SRussell King 897b5dea12SRussell King local_fiq_disable(); 907b5dea12SRussell King fn(pwrmode); 917b5dea12SRussell King local_fiq_enable(); 927b5dea12SRussell King 937b5dea12SRussell King AD2D0ER = 0; 947b5dea12SRussell King AD2D1ER = 0; 957b5dea12SRussell King } 967b5dea12SRussell King 97c4d1fb62Seric miao /* 98c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 99c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 100c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 101c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 102c4d1fb62Seric miao * 0x5c014000 for the moment. 103c4d1fb62Seric miao */ 104c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 105c4d1fb62Seric miao { 106c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 107c4d1fb62Seric miao unsigned long saved_data = *p; 108a9503d21SRussell King #ifndef CONFIG_IWMMXT 109a9503d21SRussell King u64 acc0; 110c4d1fb62Seric miao 111*4b886159SArnd Bergmann #ifdef CONFIG_CC_IS_GCC 112343c1cdbSArnd Bergmann asm volatile(".arch_extension xscale\n\t" 113343c1cdbSArnd Bergmann "mra %Q0, %R0, acc0" : "=r" (acc0)); 114*4b886159SArnd Bergmann #else 115*4b886159SArnd Bergmann asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0)); 116*4b886159SArnd Bergmann #endif 117a9503d21SRussell King #endif 118a9503d21SRussell King 119c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 120c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 121c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 122c4d1fb62Seric miao 123c4d1fb62Seric miao /* clear and setup wakeup source */ 124c4d1fb62Seric miao AD3SR = ~0; 125c4d1fb62Seric miao AD3ER = wakeup_src; 126c4d1fb62Seric miao ASCR = ASCR; 127c4d1fb62Seric miao ARSR = ARSR; 128c4d1fb62Seric miao 129c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 130c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 131c4d1fb62Seric miao 132c4d1fb62Seric miao PSPR = 0x5c014000; 133c4d1fb62Seric miao 134c4d1fb62Seric miao /* overwrite with the resume address */ 13564fc2a94SFlorian Fainelli *p = __pa_symbol(cpu_resume); 136c4d1fb62Seric miao 1372c74a0ceSRussell King cpu_suspend(0, pxa3xx_finish_suspend); 138c4d1fb62Seric miao 139c4d1fb62Seric miao *p = saved_data; 140c4d1fb62Seric miao 141c4d1fb62Seric miao AD3ER = 0; 142a9503d21SRussell King 143a9503d21SRussell King #ifndef CONFIG_IWMMXT 144*4b886159SArnd Bergmann #ifndef CONFIG_AS_IS_LLVM 145343c1cdbSArnd Bergmann asm volatile(".arch_extension xscale\n\t" 146343c1cdbSArnd Bergmann "mar acc0, %Q0, %R0" : "=r" (acc0)); 147*4b886159SArnd Bergmann #else 148*4b886159SArnd Bergmann asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0)); 149*4b886159SArnd Bergmann #endif 150a9503d21SRussell King #endif 151c4d1fb62Seric miao } 152c4d1fb62Seric miao 1537b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 1547b5dea12SRussell King { 1557b5dea12SRussell King /* 1567b5dea12SRussell King * Don't sleep if no wakeup sources are defined 1577b5dea12SRussell King */ 158b86a5da8SMark Brown if (wakeup_src == 0) { 159b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 1607b5dea12SRussell King return; 161b86a5da8SMark Brown } 1627b5dea12SRussell King 1637b5dea12SRussell King switch (state) { 1647b5dea12SRussell King case PM_SUSPEND_STANDBY: 1657b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 1667b5dea12SRussell King break; 1677b5dea12SRussell King 1687b5dea12SRussell King case PM_SUSPEND_MEM: 169c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 1707b5dea12SRussell King break; 1717b5dea12SRussell King } 1727b5dea12SRussell King } 1737b5dea12SRussell King 1747b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 1757b5dea12SRussell King { 1767b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 1777b5dea12SRussell King } 1787b5dea12SRussell King 1797b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 1807b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 1817b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 1827b5dea12SRussell King }; 1837b5dea12SRussell King 1847b5dea12SRussell King static void __init pxa3xx_init_pm(void) 1857b5dea12SRussell King { 1867b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 1877b5dea12SRussell King if (!sram) { 1887b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 1897b5dea12SRussell King return; 1907b5dea12SRussell King } 1917b5dea12SRussell King 1927b5dea12SRussell King /* 1937b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 1947b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 1957b5dea12SRussell King * is undocumented in the developer manual, but must be set. 1967b5dea12SRussell King */ 1977b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 1987b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 1997b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 2007b5dea12SRussell King 2017b5dea12SRussell King /* 2027b5dea12SRussell King * Clear the resume enable registers. 2037b5dea12SRussell King */ 2047b5dea12SRussell King AD1D0ER = 0; 2057b5dea12SRussell King AD2D0ER = 0; 2067b5dea12SRussell King AD2D1ER = 0; 2077b5dea12SRussell King AD3ER = 0; 2087b5dea12SRussell King 2097b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 2107b5dea12SRussell King } 2117b5dea12SRussell King 212a3f4c927SLennert Buytenhek static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 2137b5dea12SRussell King { 2147b5dea12SRussell King unsigned long flags, mask = 0; 2157b5dea12SRussell King 216a3f4c927SLennert Buytenhek switch (d->irq) { 2177b5dea12SRussell King case IRQ_SSP3: 2187b5dea12SRussell King mask = ADXER_MFP_WSSP3; 2197b5dea12SRussell King break; 2207b5dea12SRussell King case IRQ_MSL: 2217b5dea12SRussell King mask = ADXER_WMSL0; 2227b5dea12SRussell King break; 2237b5dea12SRussell King case IRQ_USBH2: 2247b5dea12SRussell King case IRQ_USBH1: 2257b5dea12SRussell King mask = ADXER_WUSBH; 2267b5dea12SRussell King break; 2277b5dea12SRussell King case IRQ_KEYPAD: 2287b5dea12SRussell King mask = ADXER_WKP; 2297b5dea12SRussell King break; 2307b5dea12SRussell King case IRQ_AC97: 2317b5dea12SRussell King mask = ADXER_MFP_WAC97; 2327b5dea12SRussell King break; 2337b5dea12SRussell King case IRQ_USIM: 2347b5dea12SRussell King mask = ADXER_WUSIM0; 2357b5dea12SRussell King break; 2367b5dea12SRussell King case IRQ_SSP2: 2377b5dea12SRussell King mask = ADXER_MFP_WSSP2; 2387b5dea12SRussell King break; 2397b5dea12SRussell King case IRQ_I2C: 2407b5dea12SRussell King mask = ADXER_MFP_WI2C; 2417b5dea12SRussell King break; 2427b5dea12SRussell King case IRQ_STUART: 2437b5dea12SRussell King mask = ADXER_MFP_WUART3; 2447b5dea12SRussell King break; 2457b5dea12SRussell King case IRQ_BTUART: 2467b5dea12SRussell King mask = ADXER_MFP_WUART2; 2477b5dea12SRussell King break; 2487b5dea12SRussell King case IRQ_FFUART: 2497b5dea12SRussell King mask = ADXER_MFP_WUART1; 2507b5dea12SRussell King break; 2517b5dea12SRussell King case IRQ_MMC: 2527b5dea12SRussell King mask = ADXER_MFP_WMMC1; 2537b5dea12SRussell King break; 2547b5dea12SRussell King case IRQ_SSP: 2557b5dea12SRussell King mask = ADXER_MFP_WSSP1; 2567b5dea12SRussell King break; 2577b5dea12SRussell King case IRQ_RTCAlrm: 2587b5dea12SRussell King mask = ADXER_WRTC; 2597b5dea12SRussell King break; 2607b5dea12SRussell King case IRQ_SSP4: 2617b5dea12SRussell King mask = ADXER_MFP_WSSP4; 2627b5dea12SRussell King break; 2637b5dea12SRussell King case IRQ_TSI: 2647b5dea12SRussell King mask = ADXER_WTSI; 2657b5dea12SRussell King break; 2667b5dea12SRussell King case IRQ_USIM2: 2677b5dea12SRussell King mask = ADXER_WUSIM1; 2687b5dea12SRussell King break; 2697b5dea12SRussell King case IRQ_MMC2: 2707b5dea12SRussell King mask = ADXER_MFP_WMMC2; 2717b5dea12SRussell King break; 2727b5dea12SRussell King case IRQ_NAND: 2737b5dea12SRussell King mask = ADXER_MFP_WFLASH; 2747b5dea12SRussell King break; 2757b5dea12SRussell King case IRQ_USB2: 2767b5dea12SRussell King mask = ADXER_WUSB2; 2777b5dea12SRussell King break; 2787b5dea12SRussell King case IRQ_WAKEUP0: 2797b5dea12SRussell King mask = ADXER_WEXTWAKE0; 2807b5dea12SRussell King break; 2817b5dea12SRussell King case IRQ_WAKEUP1: 2827b5dea12SRussell King mask = ADXER_WEXTWAKE1; 2837b5dea12SRussell King break; 2847b5dea12SRussell King case IRQ_MMC3: 2857b5dea12SRussell King mask = ADXER_MFP_GEN12; 2867b5dea12SRussell King break; 287e1217707SMark Brown default: 288e1217707SMark Brown return -EINVAL; 2897b5dea12SRussell King } 2907b5dea12SRussell King 2917b5dea12SRussell King local_irq_save(flags); 2927b5dea12SRussell King if (on) 2937b5dea12SRussell King wakeup_src |= mask; 2947b5dea12SRussell King else 2957b5dea12SRussell King wakeup_src &= ~mask; 2967b5dea12SRussell King local_irq_restore(flags); 2977b5dea12SRussell King 2987b5dea12SRussell King return 0; 2997b5dea12SRussell King } 3007b5dea12SRussell King #else 3017b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 302b9e25aceSeric miao #define pxa3xx_set_wake NULL 3037b5dea12SRussell King #endif 3047b5dea12SRussell King 305a3f4c927SLennert Buytenhek static void pxa_ack_ext_wakeup(struct irq_data *d) 306bf293aecSMike Rapoport { 307a3f4c927SLennert Buytenhek PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 308bf293aecSMike Rapoport } 309bf293aecSMike Rapoport 310a3f4c927SLennert Buytenhek static void pxa_mask_ext_wakeup(struct irq_data *d) 311bf293aecSMike Rapoport { 3125d284e35SEric Miao pxa_mask_irq(d); 313a3f4c927SLennert Buytenhek PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 314bf293aecSMike Rapoport } 315bf293aecSMike Rapoport 316a3f4c927SLennert Buytenhek static void pxa_unmask_ext_wakeup(struct irq_data *d) 317bf293aecSMike Rapoport { 3185d284e35SEric Miao pxa_unmask_irq(d); 319a3f4c927SLennert Buytenhek PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 320bf293aecSMike Rapoport } 321bf293aecSMike Rapoport 322a3f4c927SLennert Buytenhek static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 32312882096SIgor Grinberg { 32412882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_RISING) 325a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0); 32612882096SIgor Grinberg 32712882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_FALLING) 328a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 32912882096SIgor Grinberg 33012882096SIgor Grinberg return 0; 33112882096SIgor Grinberg } 33212882096SIgor Grinberg 333bf293aecSMike Rapoport static struct irq_chip pxa_ext_wakeup_chip = { 334bf293aecSMike Rapoport .name = "WAKEUP", 335a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_ext_wakeup, 336a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_ext_wakeup, 337a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_ext_wakeup, 338a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_ext_wakeup_type, 339bf293aecSMike Rapoport }; 340bf293aecSMike Rapoport 341157d2644SHaojian Zhuang static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, 342157d2644SHaojian Zhuang unsigned int)) 343bf293aecSMike Rapoport { 344bf293aecSMike Rapoport int irq; 345bf293aecSMike Rapoport 346bf293aecSMike Rapoport for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 347f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 348f38c02f3SThomas Gleixner handle_edge_irq); 349e8d36d5dSRob Herring irq_clear_status_flags(irq, IRQ_NOREQUEST); 350bf293aecSMike Rapoport } 351bf293aecSMike Rapoport 352a3f4c927SLennert Buytenhek pxa_ext_wakeup_chip.irq_set_wake = fn; 353bf293aecSMike Rapoport } 354bf293aecSMike Rapoport 355089d0362SDaniel Mack static void __init __pxa3xx_init_irq(void) 3562c8086a5Seric miao { 3572c8086a5Seric miao /* enable CP6 access */ 3582c8086a5Seric miao u32 value; 3592c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 3602c8086a5Seric miao value |= (1 << 6); 3612c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 3622c8086a5Seric miao 363bf293aecSMike Rapoport pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 3642c8086a5Seric miao } 3652c8086a5Seric miao 366089d0362SDaniel Mack void __init pxa3xx_init_irq(void) 367089d0362SDaniel Mack { 368089d0362SDaniel Mack __pxa3xx_init_irq(); 369089d0362SDaniel Mack pxa_init_irq(56, pxa3xx_set_wake); 370089d0362SDaniel Mack } 371089d0362SDaniel Mack 372e6c509c8SHaojian Zhuang #ifdef CONFIG_OF 37332f17997SRobert Jarzmik static int __init __init 37432f17997SRobert Jarzmik pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent) 375089d0362SDaniel Mack { 376089d0362SDaniel Mack __pxa3xx_init_irq(); 377089d0362SDaniel Mack pxa_dt_irq_init(pxa3xx_set_wake); 37832f17997SRobert Jarzmik set_handle_irq(ichp_handle_irq); 37932f17997SRobert Jarzmik 38032f17997SRobert Jarzmik return 0; 381089d0362SDaniel Mack } 38232f17997SRobert Jarzmik IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq); 383e6c509c8SHaojian Zhuang #endif /* CONFIG_OF */ 384089d0362SDaniel Mack 385851982c1SMarek Vasut static struct map_desc pxa3xx_io_desc[] __initdata = { 386851982c1SMarek Vasut { /* Mem Ctl */ 38797b09da4SArnd Bergmann .virtual = (unsigned long)SMEMC_VIRT, 388ad68bb9fSMarek Vasut .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 3890e32986cSLaurent Pinchart .length = SMEMC_SIZE, 390851982c1SMarek Vasut .type = MT_DEVICE 391adf3442cSRobert Jarzmik }, { 392adf3442cSRobert Jarzmik .virtual = (unsigned long)NAND_VIRT, 393adf3442cSRobert Jarzmik .pfn = __phys_to_pfn(NAND_PHYS), 394adf3442cSRobert Jarzmik .length = NAND_SIZE, 395adf3442cSRobert Jarzmik .type = MT_DEVICE 396adf3442cSRobert Jarzmik }, 397851982c1SMarek Vasut }; 398851982c1SMarek Vasut 399851982c1SMarek Vasut void __init pxa3xx_map_io(void) 400851982c1SMarek Vasut { 401851982c1SMarek Vasut pxa_map_io(); 402851982c1SMarek Vasut iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 403851982c1SMarek Vasut pxa3xx_get_clk_frequency_khz(1); 404851982c1SMarek Vasut } 405851982c1SMarek Vasut 4062c8086a5Seric miao /* 4072c8086a5Seric miao * device registration specific to PXA3xx. 4082c8086a5Seric miao */ 4092c8086a5Seric miao 4109ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 4119ba63c4fSMike Rapoport { 41214758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 4139ba63c4fSMike Rapoport } 4149ba63c4fSMike Rapoport 415b8f649f1SHaojian Zhuang static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = { 416b8f649f1SHaojian Zhuang .irq_base = PXA_GPIO_TO_IRQ(0), 417b8f649f1SHaojian Zhuang }; 418b8f649f1SHaojian Zhuang 4192c8086a5Seric miao static struct platform_device *devices[] __initdata = { 42094c35a6bSRobert Jarzmik &pxa27x_device_udc, 42109a5358dSEric Miao &pxa_device_pmu, 4222c8086a5Seric miao &pxa_device_i2s, 423f0fba2adSLiam Girdwood &pxa_device_asoc_ssp1, 424f0fba2adSLiam Girdwood &pxa_device_asoc_ssp2, 425f0fba2adSLiam Girdwood &pxa_device_asoc_ssp3, 426f0fba2adSLiam Girdwood &pxa_device_asoc_ssp4, 427f0fba2adSLiam Girdwood &pxa_device_asoc_platform, 4282c8086a5Seric miao &pxa_device_rtc, 4290da0e227SDaniel Mack &pxa3xx_device_ssp1, 4300da0e227SDaniel Mack &pxa3xx_device_ssp2, 4310da0e227SDaniel Mack &pxa3xx_device_ssp3, 432d8e0db11Seric miao &pxa3xx_device_ssp4, 43375540c1aSeric miao &pxa27x_device_pwm0, 43475540c1aSeric miao &pxa27x_device_pwm1, 4352c8086a5Seric miao }; 4362c8086a5Seric miao 4371da10c17SRobert Jarzmik static const struct dma_slave_map pxa3xx_slave_map[] = { 4381da10c17SRobert Jarzmik /* PXA25x, PXA27x and PXA3xx common entries */ 4391da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) }, 4401da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) }, 4411da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_aux_mono_out", 4421da10c17SRobert Jarzmik PDMA_FILTER_PARAM(LOWEST, 10) }, 4431da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) }, 4441da10c17SRobert Jarzmik { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) }, 4451da10c17SRobert Jarzmik { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) }, 4461da10c17SRobert Jarzmik { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) }, 4471da10c17SRobert Jarzmik { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) }, 4481da10c17SRobert Jarzmik { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) }, 4491da10c17SRobert Jarzmik { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) }, 4501da10c17SRobert Jarzmik { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) }, 4511da10c17SRobert Jarzmik { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) }, 4521da10c17SRobert Jarzmik { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) }, 4531da10c17SRobert Jarzmik { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) }, 4541da10c17SRobert Jarzmik { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) }, 4551da10c17SRobert Jarzmik 4561da10c17SRobert Jarzmik /* PXA3xx specific map */ 4571da10c17SRobert Jarzmik { "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) }, 4581da10c17SRobert Jarzmik { "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) }, 4591da10c17SRobert Jarzmik { "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) }, 4601da10c17SRobert Jarzmik { "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) }, 4611da10c17SRobert Jarzmik { "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) }, 4621da10c17SRobert Jarzmik { "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) }, 4631da10c17SRobert Jarzmik { "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) }, 4641da10c17SRobert Jarzmik }; 4651da10c17SRobert Jarzmik 4661da10c17SRobert Jarzmik static struct mmp_dma_platdata pxa3xx_dma_pdata = { 4671da10c17SRobert Jarzmik .dma_channels = 32, 4681da10c17SRobert Jarzmik .nb_requestors = 100, 4691da10c17SRobert Jarzmik .slave_map = pxa3xx_slave_map, 4701da10c17SRobert Jarzmik .slave_map_cnt = ARRAY_SIZE(pxa3xx_slave_map), 4711da10c17SRobert Jarzmik }; 4721da10c17SRobert Jarzmik 4732c8086a5Seric miao static int __init pxa3xx_init(void) 4742c8086a5Seric miao { 4752eaa03b5SRafael J. Wysocki int ret = 0; 4762c8086a5Seric miao 4772c8086a5Seric miao if (cpu_is_pxa3xx()) { 47804fef228SEric Miao 479e86bd43bSArnd Bergmann pxa_register_wdt(ARSR); 48004fef228SEric Miao 48186260f98SDmitry Krivoschekov /* 48286260f98SDmitry Krivoschekov * clear RDH bit every time after reset 48386260f98SDmitry Krivoschekov * 48486260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 48586260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 48686260f98SDmitry Krivoschekov */ 48786260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 48886260f98SDmitry Krivoschekov 489adf3442cSRobert Jarzmik /* 490adf3442cSRobert Jarzmik * Disable DFI bus arbitration, to prevent a system bus lock if 491adf3442cSRobert Jarzmik * somebody disables the NAND clock (unused clock) while this 492adf3442cSRobert Jarzmik * bit remains set. 493adf3442cSRobert Jarzmik */ 494adf3442cSRobert Jarzmik NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL; 495adf3442cSRobert Jarzmik 4967b5dea12SRussell King pxa3xx_init_pm(); 4977b5dea12SRussell King 498c1c14f89SDaniel Mack enable_irq_wake(IRQ_WAKEUP0); 499c1c14f89SDaniel Mack if (cpu_is_pxa320()) 500c1c14f89SDaniel Mack enable_irq_wake(IRQ_WAKEUP1); 501c1c14f89SDaniel Mack 5022eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa_irq_syscore_ops); 5032eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa3xx_mfp_syscore_ops); 504c0165504Seric miao 5052cab0292SHaojian Zhuang if (of_have_populated_dt()) 5062cab0292SHaojian Zhuang return 0; 5072cab0292SHaojian Zhuang 5081da10c17SRobert Jarzmik pxa2xx_set_dmac_info(&pxa3xx_dma_pdata); 509c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 5102cab0292SHaojian Zhuang if (ret) 5112cab0292SHaojian Zhuang return ret; 512b8f649f1SHaojian Zhuang if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) { 513b8f649f1SHaojian Zhuang platform_device_add_data(&pxa3xx_device_gpio, 514b8f649f1SHaojian Zhuang &pxa3xx_gpio_pdata, 515b8f649f1SHaojian Zhuang sizeof(pxa3xx_gpio_pdata)); 5162cab0292SHaojian Zhuang ret = platform_device_register(&pxa3xx_device_gpio); 517c0165504Seric miao } 518b8f649f1SHaojian Zhuang } 519c0165504Seric miao 520c0165504Seric miao return ret; 5212c8086a5Seric miao } 5222c8086a5Seric miao 5231c104e0eSRussell King postcore_initcall(pxa3xx_init); 524