12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao #include <linux/module.h> 162c8086a5Seric miao #include <linux/kernel.h> 172c8086a5Seric miao #include <linux/init.h> 182c8086a5Seric miao #include <linux/pm.h> 192c8086a5Seric miao #include <linux/platform_device.h> 202c8086a5Seric miao #include <linux/irq.h> 217b5dea12SRussell King #include <linux/io.h> 222eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 23b459396eSSebastian Andrzej Siewior #include <linux/i2c/pxa-i2c.h> 242c8086a5Seric miao 25851982c1SMarek Vasut #include <asm/mach/map.h> 262c74a0ceSRussell King #include <asm/suspend.h> 27a09e64fbSRussell King #include <mach/hardware.h> 28a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 29afd2fc02SRussell King #include <mach/reset.h> 30293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h> 31a09e64fbSRussell King #include <mach/pm.h> 32a09e64fbSRussell King #include <mach/dma.h> 33ad68bb9fSMarek Vasut #include <mach/smemc.h> 344e611091SRob Herring #include <mach/irqs.h> 352c8086a5Seric miao 362c8086a5Seric miao #include "generic.h" 372c8086a5Seric miao #include "devices.h" 382c8086a5Seric miao #include "clock.h" 392c8086a5Seric miao 40bf293aecSMike Rapoport #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 41bf293aecSMike Rapoport #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 42bf293aecSMike Rapoport 438c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 448c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 458c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 468c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 478c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 488c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 49e68750aeSIgor Grinberg static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 508c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 518c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 528c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 538c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 548c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 558c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 568c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 578c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 588c3abc7dSRussell King static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 59389eda15SHaojian Zhuang static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0); 602c8086a5Seric miao 612e8581e7SEric Miao static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 62c085052bSEric Miao static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); 632e8581e7SEric Miao static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 642e8581e7SEric Miao static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 654029813cSEric Miao static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); 662e8581e7SEric Miao 678c3abc7dSRussell King static struct clk_lookup pxa3xx_clkregs[] = { 688c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 698c3abc7dSRussell King /* Power I2C clock is always on */ 705c68b099SDaniel Mack INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 718c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 728c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 738c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 748c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 758c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 768c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 778c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 788c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 798c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 808c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 8169f22be7SIgor Grinberg INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 828c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 838c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 848c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 858c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 868c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 878c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 888c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 898c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 908c3abc7dSRussell King INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 91c085052bSEric Miao INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), 92389eda15SHaojian Zhuang INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL), 933e12ec77SHaojian Zhuang INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), 942c8086a5Seric miao }; 952c8086a5Seric miao 967b5dea12SRussell King #ifdef CONFIG_PM 977b5dea12SRussell King 987b5dea12SRussell King #define ISRAM_START 0x5c000000 997b5dea12SRussell King #define ISRAM_SIZE SZ_256K 1007b5dea12SRussell King 1017b5dea12SRussell King static void __iomem *sram; 1027b5dea12SRussell King static unsigned long wakeup_src; 1037b5dea12SRussell King 1047b5dea12SRussell King /* 1057b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 1067b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 1077b5dea12SRussell King * in the SRAM to perform this function. 1087b5dea12SRussell King * 1097b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 1107b5dea12SRussell King * FIQ while the SDRAM is unavailable. 1117b5dea12SRussell King */ 1127b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 1137b5dea12SRussell King { 1147b5dea12SRussell King extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 1157b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 1167b5dea12SRussell King 1177b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 1187b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 1197b5dea12SRussell King 1207b5dea12SRussell King AD2D0SR = ~0; 1217b5dea12SRussell King AD2D1SR = ~0; 1227b5dea12SRussell King AD2D0ER = wakeup_src; 1237b5dea12SRussell King AD2D1ER = 0; 1247b5dea12SRussell King ASCR = ASCR; 1257b5dea12SRussell King ARSR = ARSR; 1267b5dea12SRussell King 1277b5dea12SRussell King local_fiq_disable(); 1287b5dea12SRussell King fn(pwrmode); 1297b5dea12SRussell King local_fiq_enable(); 1307b5dea12SRussell King 1317b5dea12SRussell King AD2D0ER = 0; 1327b5dea12SRussell King AD2D1ER = 0; 1337b5dea12SRussell King } 1347b5dea12SRussell King 135c4d1fb62Seric miao /* 136c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 137c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 138c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 139c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 140c4d1fb62Seric miao * 0x5c014000 for the moment. 141c4d1fb62Seric miao */ 142c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 143c4d1fb62Seric miao { 144c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 145c4d1fb62Seric miao unsigned long saved_data = *p; 146a9503d21SRussell King #ifndef CONFIG_IWMMXT 147a9503d21SRussell King u64 acc0; 148c4d1fb62Seric miao 149a9503d21SRussell King asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); 150a9503d21SRussell King #endif 151a9503d21SRussell King 15229cb3cd2SRussell King extern int pxa3xx_finish_suspend(unsigned long); 153c4d1fb62Seric miao 154c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 155c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 156c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 157c4d1fb62Seric miao 158c4d1fb62Seric miao /* clear and setup wakeup source */ 159c4d1fb62Seric miao AD3SR = ~0; 160c4d1fb62Seric miao AD3ER = wakeup_src; 161c4d1fb62Seric miao ASCR = ASCR; 162c4d1fb62Seric miao ARSR = ARSR; 163c4d1fb62Seric miao 164c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 165c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 166c4d1fb62Seric miao 167c4d1fb62Seric miao PSPR = 0x5c014000; 168c4d1fb62Seric miao 169c4d1fb62Seric miao /* overwrite with the resume address */ 1704f5ad99bSRussell King *p = virt_to_phys(cpu_resume); 171c4d1fb62Seric miao 1722c74a0ceSRussell King cpu_suspend(0, pxa3xx_finish_suspend); 173c4d1fb62Seric miao 174c4d1fb62Seric miao *p = saved_data; 175c4d1fb62Seric miao 176c4d1fb62Seric miao AD3ER = 0; 177a9503d21SRussell King 178a9503d21SRussell King #ifndef CONFIG_IWMMXT 179a9503d21SRussell King asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); 180a9503d21SRussell King #endif 181c4d1fb62Seric miao } 182c4d1fb62Seric miao 1837b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 1847b5dea12SRussell King { 1857b5dea12SRussell King /* 1867b5dea12SRussell King * Don't sleep if no wakeup sources are defined 1877b5dea12SRussell King */ 188b86a5da8SMark Brown if (wakeup_src == 0) { 189b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 1907b5dea12SRussell King return; 191b86a5da8SMark Brown } 1927b5dea12SRussell King 1937b5dea12SRussell King switch (state) { 1947b5dea12SRussell King case PM_SUSPEND_STANDBY: 1957b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 1967b5dea12SRussell King break; 1977b5dea12SRussell King 1987b5dea12SRussell King case PM_SUSPEND_MEM: 199c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 2007b5dea12SRussell King break; 2017b5dea12SRussell King } 2027b5dea12SRussell King } 2037b5dea12SRussell King 2047b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 2057b5dea12SRussell King { 2067b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 2077b5dea12SRussell King } 2087b5dea12SRussell King 2097b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 2107b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 2117b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 2127b5dea12SRussell King }; 2137b5dea12SRussell King 2147b5dea12SRussell King static void __init pxa3xx_init_pm(void) 2157b5dea12SRussell King { 2167b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 2177b5dea12SRussell King if (!sram) { 2187b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 2197b5dea12SRussell King return; 2207b5dea12SRussell King } 2217b5dea12SRussell King 2227b5dea12SRussell King /* 2237b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 2247b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 2257b5dea12SRussell King * is undocumented in the developer manual, but must be set. 2267b5dea12SRussell King */ 2277b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 2287b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 2297b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 2307b5dea12SRussell King 2317b5dea12SRussell King /* 2327b5dea12SRussell King * Clear the resume enable registers. 2337b5dea12SRussell King */ 2347b5dea12SRussell King AD1D0ER = 0; 2357b5dea12SRussell King AD2D0ER = 0; 2367b5dea12SRussell King AD2D1ER = 0; 2377b5dea12SRussell King AD3ER = 0; 2387b5dea12SRussell King 2397b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 2407b5dea12SRussell King } 2417b5dea12SRussell King 242a3f4c927SLennert Buytenhek static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 2437b5dea12SRussell King { 2447b5dea12SRussell King unsigned long flags, mask = 0; 2457b5dea12SRussell King 246a3f4c927SLennert Buytenhek switch (d->irq) { 2477b5dea12SRussell King case IRQ_SSP3: 2487b5dea12SRussell King mask = ADXER_MFP_WSSP3; 2497b5dea12SRussell King break; 2507b5dea12SRussell King case IRQ_MSL: 2517b5dea12SRussell King mask = ADXER_WMSL0; 2527b5dea12SRussell King break; 2537b5dea12SRussell King case IRQ_USBH2: 2547b5dea12SRussell King case IRQ_USBH1: 2557b5dea12SRussell King mask = ADXER_WUSBH; 2567b5dea12SRussell King break; 2577b5dea12SRussell King case IRQ_KEYPAD: 2587b5dea12SRussell King mask = ADXER_WKP; 2597b5dea12SRussell King break; 2607b5dea12SRussell King case IRQ_AC97: 2617b5dea12SRussell King mask = ADXER_MFP_WAC97; 2627b5dea12SRussell King break; 2637b5dea12SRussell King case IRQ_USIM: 2647b5dea12SRussell King mask = ADXER_WUSIM0; 2657b5dea12SRussell King break; 2667b5dea12SRussell King case IRQ_SSP2: 2677b5dea12SRussell King mask = ADXER_MFP_WSSP2; 2687b5dea12SRussell King break; 2697b5dea12SRussell King case IRQ_I2C: 2707b5dea12SRussell King mask = ADXER_MFP_WI2C; 2717b5dea12SRussell King break; 2727b5dea12SRussell King case IRQ_STUART: 2737b5dea12SRussell King mask = ADXER_MFP_WUART3; 2747b5dea12SRussell King break; 2757b5dea12SRussell King case IRQ_BTUART: 2767b5dea12SRussell King mask = ADXER_MFP_WUART2; 2777b5dea12SRussell King break; 2787b5dea12SRussell King case IRQ_FFUART: 2797b5dea12SRussell King mask = ADXER_MFP_WUART1; 2807b5dea12SRussell King break; 2817b5dea12SRussell King case IRQ_MMC: 2827b5dea12SRussell King mask = ADXER_MFP_WMMC1; 2837b5dea12SRussell King break; 2847b5dea12SRussell King case IRQ_SSP: 2857b5dea12SRussell King mask = ADXER_MFP_WSSP1; 2867b5dea12SRussell King break; 2877b5dea12SRussell King case IRQ_RTCAlrm: 2887b5dea12SRussell King mask = ADXER_WRTC; 2897b5dea12SRussell King break; 2907b5dea12SRussell King case IRQ_SSP4: 2917b5dea12SRussell King mask = ADXER_MFP_WSSP4; 2927b5dea12SRussell King break; 2937b5dea12SRussell King case IRQ_TSI: 2947b5dea12SRussell King mask = ADXER_WTSI; 2957b5dea12SRussell King break; 2967b5dea12SRussell King case IRQ_USIM2: 2977b5dea12SRussell King mask = ADXER_WUSIM1; 2987b5dea12SRussell King break; 2997b5dea12SRussell King case IRQ_MMC2: 3007b5dea12SRussell King mask = ADXER_MFP_WMMC2; 3017b5dea12SRussell King break; 3027b5dea12SRussell King case IRQ_NAND: 3037b5dea12SRussell King mask = ADXER_MFP_WFLASH; 3047b5dea12SRussell King break; 3057b5dea12SRussell King case IRQ_USB2: 3067b5dea12SRussell King mask = ADXER_WUSB2; 3077b5dea12SRussell King break; 3087b5dea12SRussell King case IRQ_WAKEUP0: 3097b5dea12SRussell King mask = ADXER_WEXTWAKE0; 3107b5dea12SRussell King break; 3117b5dea12SRussell King case IRQ_WAKEUP1: 3127b5dea12SRussell King mask = ADXER_WEXTWAKE1; 3137b5dea12SRussell King break; 3147b5dea12SRussell King case IRQ_MMC3: 3157b5dea12SRussell King mask = ADXER_MFP_GEN12; 3167b5dea12SRussell King break; 317e1217707SMark Brown default: 318e1217707SMark Brown return -EINVAL; 3197b5dea12SRussell King } 3207b5dea12SRussell King 3217b5dea12SRussell King local_irq_save(flags); 3227b5dea12SRussell King if (on) 3237b5dea12SRussell King wakeup_src |= mask; 3247b5dea12SRussell King else 3257b5dea12SRussell King wakeup_src &= ~mask; 3267b5dea12SRussell King local_irq_restore(flags); 3277b5dea12SRussell King 3287b5dea12SRussell King return 0; 3297b5dea12SRussell King } 3307b5dea12SRussell King #else 3317b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 332b9e25aceSeric miao #define pxa3xx_set_wake NULL 3337b5dea12SRussell King #endif 3347b5dea12SRussell King 335a3f4c927SLennert Buytenhek static void pxa_ack_ext_wakeup(struct irq_data *d) 336bf293aecSMike Rapoport { 337a3f4c927SLennert Buytenhek PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 338bf293aecSMike Rapoport } 339bf293aecSMike Rapoport 340a3f4c927SLennert Buytenhek static void pxa_mask_ext_wakeup(struct irq_data *d) 341bf293aecSMike Rapoport { 3425d284e35SEric Miao pxa_mask_irq(d); 343a3f4c927SLennert Buytenhek PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 344bf293aecSMike Rapoport } 345bf293aecSMike Rapoport 346a3f4c927SLennert Buytenhek static void pxa_unmask_ext_wakeup(struct irq_data *d) 347bf293aecSMike Rapoport { 3485d284e35SEric Miao pxa_unmask_irq(d); 349a3f4c927SLennert Buytenhek PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 350bf293aecSMike Rapoport } 351bf293aecSMike Rapoport 352a3f4c927SLennert Buytenhek static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 35312882096SIgor Grinberg { 35412882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_RISING) 355a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0); 35612882096SIgor Grinberg 35712882096SIgor Grinberg if (flow_type & IRQ_TYPE_EDGE_FALLING) 358a3f4c927SLennert Buytenhek PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 35912882096SIgor Grinberg 36012882096SIgor Grinberg return 0; 36112882096SIgor Grinberg } 36212882096SIgor Grinberg 363bf293aecSMike Rapoport static struct irq_chip pxa_ext_wakeup_chip = { 364bf293aecSMike Rapoport .name = "WAKEUP", 365a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_ext_wakeup, 366a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_ext_wakeup, 367a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_ext_wakeup, 368a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_ext_wakeup_type, 369bf293aecSMike Rapoport }; 370bf293aecSMike Rapoport 371157d2644SHaojian Zhuang static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, 372157d2644SHaojian Zhuang unsigned int)) 373bf293aecSMike Rapoport { 374bf293aecSMike Rapoport int irq; 375bf293aecSMike Rapoport 376bf293aecSMike Rapoport for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 377f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 378f38c02f3SThomas Gleixner handle_edge_irq); 379bf293aecSMike Rapoport set_irq_flags(irq, IRQF_VALID); 380bf293aecSMike Rapoport } 381bf293aecSMike Rapoport 382a3f4c927SLennert Buytenhek pxa_ext_wakeup_chip.irq_set_wake = fn; 383bf293aecSMike Rapoport } 384bf293aecSMike Rapoport 3852c8086a5Seric miao void __init pxa3xx_init_irq(void) 3862c8086a5Seric miao { 3872c8086a5Seric miao /* enable CP6 access */ 3882c8086a5Seric miao u32 value; 3892c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 3902c8086a5Seric miao value |= (1 << 6); 3912c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 3922c8086a5Seric miao 393b9e25aceSeric miao pxa_init_irq(56, pxa3xx_set_wake); 394bf293aecSMike Rapoport pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 3952c8086a5Seric miao } 3962c8086a5Seric miao 397851982c1SMarek Vasut static struct map_desc pxa3xx_io_desc[] __initdata = { 398851982c1SMarek Vasut { /* Mem Ctl */ 39997b09da4SArnd Bergmann .virtual = (unsigned long)SMEMC_VIRT, 400ad68bb9fSMarek Vasut .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 401851982c1SMarek Vasut .length = 0x00200000, 402851982c1SMarek Vasut .type = MT_DEVICE 403851982c1SMarek Vasut } 404851982c1SMarek Vasut }; 405851982c1SMarek Vasut 406851982c1SMarek Vasut void __init pxa3xx_map_io(void) 407851982c1SMarek Vasut { 408851982c1SMarek Vasut pxa_map_io(); 409851982c1SMarek Vasut iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 410851982c1SMarek Vasut pxa3xx_get_clk_frequency_khz(1); 411851982c1SMarek Vasut } 412851982c1SMarek Vasut 4132c8086a5Seric miao /* 4142c8086a5Seric miao * device registration specific to PXA3xx. 4152c8086a5Seric miao */ 4162c8086a5Seric miao 4179ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 4189ba63c4fSMike Rapoport { 41914758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 4209ba63c4fSMike Rapoport } 4219ba63c4fSMike Rapoport 4222c8086a5Seric miao static struct platform_device *devices[] __initdata = { 423157d2644SHaojian Zhuang &pxa_device_gpio, 42494c35a6bSRobert Jarzmik &pxa27x_device_udc, 42509a5358dSEric Miao &pxa_device_pmu, 4262c8086a5Seric miao &pxa_device_i2s, 427f0fba2adSLiam Girdwood &pxa_device_asoc_ssp1, 428f0fba2adSLiam Girdwood &pxa_device_asoc_ssp2, 429f0fba2adSLiam Girdwood &pxa_device_asoc_ssp3, 430f0fba2adSLiam Girdwood &pxa_device_asoc_ssp4, 431f0fba2adSLiam Girdwood &pxa_device_asoc_platform, 43272493146SRobert Jarzmik &sa1100_device_rtc, 4332c8086a5Seric miao &pxa_device_rtc, 434d8e0db11Seric miao &pxa27x_device_ssp1, 435d8e0db11Seric miao &pxa27x_device_ssp2, 436d8e0db11Seric miao &pxa27x_device_ssp3, 437d8e0db11Seric miao &pxa3xx_device_ssp4, 43875540c1aSeric miao &pxa27x_device_pwm0, 43975540c1aSeric miao &pxa27x_device_pwm1, 4402c8086a5Seric miao }; 4412c8086a5Seric miao 4422c8086a5Seric miao static int __init pxa3xx_init(void) 4432c8086a5Seric miao { 4442eaa03b5SRafael J. Wysocki int ret = 0; 4452c8086a5Seric miao 4462c8086a5Seric miao if (cpu_is_pxa3xx()) { 44704fef228SEric Miao 44804fef228SEric Miao reset_status = ARSR; 44904fef228SEric Miao 45086260f98SDmitry Krivoschekov /* 45186260f98SDmitry Krivoschekov * clear RDH bit every time after reset 45286260f98SDmitry Krivoschekov * 45386260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 45486260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 45586260f98SDmitry Krivoschekov */ 45686260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 45786260f98SDmitry Krivoschekov 4580a0300dcSRussell King clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 4592c8086a5Seric miao 460fef1f99aSEric Miao if ((ret = pxa_init_dma(IRQ_DMA, 32))) 4612c8086a5Seric miao return ret; 4622c8086a5Seric miao 4637b5dea12SRussell King pxa3xx_init_pm(); 4647b5dea12SRussell King 4652eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa_irq_syscore_ops); 4662eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa3xx_mfp_syscore_ops); 4672eaa03b5SRafael J. Wysocki register_syscore_ops(&pxa3xx_clock_syscore_ops); 468c0165504Seric miao 469c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 470c0165504Seric miao } 471c0165504Seric miao 472c0165504Seric miao return ret; 4732c8086a5Seric miao } 4742c8086a5Seric miao 4751c104e0eSRussell King postcore_initcall(pxa3xx_init); 476