12c8086a5Seric miao /* 22c8086a5Seric miao * linux/arch/arm/mach-pxa/pxa3xx.c 32c8086a5Seric miao * 42c8086a5Seric miao * code specific to pxa3xx aka Monahans 52c8086a5Seric miao * 62c8086a5Seric miao * Copyright (C) 2006 Marvell International Ltd. 72c8086a5Seric miao * 8e9bba8eeSeric miao * 2007-09-02: eric miao <eric.miao@marvell.com> 92c8086a5Seric miao * initial version 102c8086a5Seric miao * 112c8086a5Seric miao * This program is free software; you can redistribute it and/or modify 122c8086a5Seric miao * it under the terms of the GNU General Public License version 2 as 132c8086a5Seric miao * published by the Free Software Foundation. 142c8086a5Seric miao */ 152c8086a5Seric miao 162c8086a5Seric miao #include <linux/module.h> 172c8086a5Seric miao #include <linux/kernel.h> 182c8086a5Seric miao #include <linux/init.h> 192c8086a5Seric miao #include <linux/pm.h> 202c8086a5Seric miao #include <linux/platform_device.h> 212c8086a5Seric miao #include <linux/irq.h> 227b5dea12SRussell King #include <linux/io.h> 23c0165504Seric miao #include <linux/sysdev.h> 242c8086a5Seric miao 25a09e64fbSRussell King #include <mach/hardware.h> 26a09e64fbSRussell King #include <mach/pxa3xx-regs.h> 27afd2fc02SRussell King #include <mach/reset.h> 28a09e64fbSRussell King #include <mach/ohci.h> 29a09e64fbSRussell King #include <mach/pm.h> 30a09e64fbSRussell King #include <mach/dma.h> 31a09e64fbSRussell King #include <mach/ssp.h> 3214758220SEric Miao #include <mach/i2c.h> 332c8086a5Seric miao 342c8086a5Seric miao #include "generic.h" 352c8086a5Seric miao #include "devices.h" 362c8086a5Seric miao #include "clock.h" 372c8086a5Seric miao 382c8086a5Seric miao /* Crystal clock: 13MHz */ 392c8086a5Seric miao #define BASE_CLK 13000000 402c8086a5Seric miao 412c8086a5Seric miao /* Ring Oscillator Clock: 60MHz */ 422c8086a5Seric miao #define RO_CLK 60000000 432c8086a5Seric miao 442c8086a5Seric miao #define ACCR_D0CS (1 << 26) 45c4d1fb62Seric miao #define ACCR_PCCE (1 << 11) 462c8086a5Seric miao 472c8086a5Seric miao /* crystal frequency to static memory controller multiplier (SMCFS) */ 482c8086a5Seric miao static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 492c8086a5Seric miao 502c8086a5Seric miao /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 512c8086a5Seric miao static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 522c8086a5Seric miao 532c8086a5Seric miao /* 542c8086a5Seric miao * Get the clock frequency as reflected by CCSR and the turbo flag. 552c8086a5Seric miao * We assume these values have been applied via a fcs. 562c8086a5Seric miao * If info is not 0 we also display the current settings. 572c8086a5Seric miao */ 582c8086a5Seric miao unsigned int pxa3xx_get_clk_frequency_khz(int info) 592c8086a5Seric miao { 602c8086a5Seric miao unsigned long acsr, xclkcfg; 612c8086a5Seric miao unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 622c8086a5Seric miao 632c8086a5Seric miao /* Read XCLKCFG register turbo bit */ 642c8086a5Seric miao __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 652c8086a5Seric miao t = xclkcfg & 0x1; 662c8086a5Seric miao 672c8086a5Seric miao acsr = ACSR; 682c8086a5Seric miao 692c8086a5Seric miao xl = acsr & 0x1f; 702c8086a5Seric miao xn = (acsr >> 8) & 0x7; 712c8086a5Seric miao hss = (acsr >> 14) & 0x3; 722c8086a5Seric miao 732c8086a5Seric miao XL = xl * BASE_CLK; 742c8086a5Seric miao XN = xn * XL; 752c8086a5Seric miao 762c8086a5Seric miao ro = acsr & ACCR_D0CS; 772c8086a5Seric miao 782c8086a5Seric miao CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 792c8086a5Seric miao HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 802c8086a5Seric miao 812c8086a5Seric miao if (info) { 822c8086a5Seric miao pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 832c8086a5Seric miao RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 842c8086a5Seric miao (ro) ? "" : "in"); 852c8086a5Seric miao pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 862c8086a5Seric miao XL / 1000000, (XL % 1000000) / 10000, xl); 872c8086a5Seric miao pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 882c8086a5Seric miao XN / 1000000, (XN % 1000000) / 10000, xn, 892c8086a5Seric miao (t) ? "" : "in"); 902c8086a5Seric miao pr_info("HSIO bus clock: %d.%02dMHz\n", 912c8086a5Seric miao HSS / 1000000, (HSS % 1000000) / 10000); 922c8086a5Seric miao } 932c8086a5Seric miao 946232be32Seric miao return CLK / 1000; 952c8086a5Seric miao } 962c8086a5Seric miao 972c8086a5Seric miao /* 982c8086a5Seric miao * Return the current static memory controller clock frequency 992c8086a5Seric miao * in units of 10kHz 1002c8086a5Seric miao */ 1012c8086a5Seric miao unsigned int pxa3xx_get_memclk_frequency_10khz(void) 1022c8086a5Seric miao { 1032c8086a5Seric miao unsigned long acsr; 1042c8086a5Seric miao unsigned int smcfs, clk = 0; 1052c8086a5Seric miao 1062c8086a5Seric miao acsr = ACSR; 1072c8086a5Seric miao 1082c8086a5Seric miao smcfs = (acsr >> 23) & 0x7; 1092c8086a5Seric miao clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 1102c8086a5Seric miao 1112c8086a5Seric miao return (clk / 10000); 1122c8086a5Seric miao } 1132c8086a5Seric miao 11404fef228SEric Miao void pxa3xx_clear_reset_status(unsigned int mask) 11504fef228SEric Miao { 11604fef228SEric Miao /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 11704fef228SEric Miao ARSR = mask; 11804fef228SEric Miao } 11904fef228SEric Miao 1202c8086a5Seric miao /* 12160bfe7faSMark Brown * Return the current AC97 clock frequency. 12260bfe7faSMark Brown */ 12360bfe7faSMark Brown static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 12460bfe7faSMark Brown { 12560bfe7faSMark Brown unsigned long rate = 312000000; 12660bfe7faSMark Brown unsigned long ac97_div; 12760bfe7faSMark Brown 12860bfe7faSMark Brown ac97_div = AC97_DIV; 12960bfe7faSMark Brown 13060bfe7faSMark Brown /* This may loose precision for some rates but won't for the 13160bfe7faSMark Brown * standard 24.576MHz. 13260bfe7faSMark Brown */ 13360bfe7faSMark Brown rate /= (ac97_div >> 12) & 0x7fff; 13460bfe7faSMark Brown rate *= (ac97_div & 0xfff); 13560bfe7faSMark Brown 13660bfe7faSMark Brown return rate; 13760bfe7faSMark Brown } 13860bfe7faSMark Brown 13960bfe7faSMark Brown /* 1402c8086a5Seric miao * Return the current HSIO bus clock frequency 1412c8086a5Seric miao */ 1422c8086a5Seric miao static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 1432c8086a5Seric miao { 1442c8086a5Seric miao unsigned long acsr; 1452c8086a5Seric miao unsigned int hss, hsio_clk; 1462c8086a5Seric miao 1472c8086a5Seric miao acsr = ACSR; 1482c8086a5Seric miao 1492c8086a5Seric miao hss = (acsr >> 14) & 0x3; 1502c8086a5Seric miao hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 1512c8086a5Seric miao 1522c8086a5Seric miao return hsio_clk; 1532c8086a5Seric miao } 1542c8086a5Seric miao 1557a2c5cb0Seric miao void clk_pxa3xx_cken_enable(struct clk *clk) 1562c8086a5Seric miao { 1572c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1582c8086a5Seric miao 1592c8086a5Seric miao if (clk->cken < 32) 1602c8086a5Seric miao CKENA |= mask; 1612c8086a5Seric miao else 1622c8086a5Seric miao CKENB |= mask; 1632c8086a5Seric miao } 1642c8086a5Seric miao 1657a2c5cb0Seric miao void clk_pxa3xx_cken_disable(struct clk *clk) 1662c8086a5Seric miao { 1672c8086a5Seric miao unsigned long mask = 1ul << (clk->cken & 0x1f); 1682c8086a5Seric miao 1692c8086a5Seric miao if (clk->cken < 32) 1702c8086a5Seric miao CKENA &= ~mask; 1712c8086a5Seric miao else 1722c8086a5Seric miao CKENB &= ~mask; 1732c8086a5Seric miao } 1742c8086a5Seric miao 1757a2c5cb0Seric miao const struct clkops clk_pxa3xx_cken_ops = { 1762a0d7187Seric miao .enable = clk_pxa3xx_cken_enable, 1772a0d7187Seric miao .disable = clk_pxa3xx_cken_disable, 1782a0d7187Seric miao }; 1792a0d7187Seric miao 1802c8086a5Seric miao static const struct clkops clk_pxa3xx_hsio_ops = { 1812c8086a5Seric miao .enable = clk_pxa3xx_cken_enable, 1822c8086a5Seric miao .disable = clk_pxa3xx_cken_disable, 1832c8086a5Seric miao .getrate = clk_pxa3xx_hsio_getrate, 1842c8086a5Seric miao }; 1852c8086a5Seric miao 18660bfe7faSMark Brown static const struct clkops clk_pxa3xx_ac97_ops = { 18760bfe7faSMark Brown .enable = clk_pxa3xx_cken_enable, 18860bfe7faSMark Brown .disable = clk_pxa3xx_cken_disable, 18960bfe7faSMark Brown .getrate = clk_pxa3xx_ac97_getrate, 19060bfe7faSMark Brown }; 19160bfe7faSMark Brown 192dcc88a17SMark Brown static void clk_pout_enable(struct clk *clk) 193dcc88a17SMark Brown { 194dcc88a17SMark Brown OSCC |= OSCC_PEN; 195dcc88a17SMark Brown } 196dcc88a17SMark Brown 197dcc88a17SMark Brown static void clk_pout_disable(struct clk *clk) 198dcc88a17SMark Brown { 199dcc88a17SMark Brown OSCC &= ~OSCC_PEN; 200dcc88a17SMark Brown } 201dcc88a17SMark Brown 202dcc88a17SMark Brown static const struct clkops clk_pout_ops = { 203dcc88a17SMark Brown .enable = clk_pout_enable, 204dcc88a17SMark Brown .disable = clk_pout_disable, 205dcc88a17SMark Brown }; 206dcc88a17SMark Brown 2079ba63c4fSMike Rapoport static void clk_dummy_enable(struct clk *clk) 2089ba63c4fSMike Rapoport { 2099ba63c4fSMike Rapoport } 2109ba63c4fSMike Rapoport 2119ba63c4fSMike Rapoport static void clk_dummy_disable(struct clk *clk) 2129ba63c4fSMike Rapoport { 2139ba63c4fSMike Rapoport } 2149ba63c4fSMike Rapoport 2159ba63c4fSMike Rapoport static const struct clkops clk_dummy_ops = { 2169ba63c4fSMike Rapoport .enable = clk_dummy_enable, 2179ba63c4fSMike Rapoport .disable = clk_dummy_disable, 2189ba63c4fSMike Rapoport }; 2199ba63c4fSMike Rapoport 2202c8086a5Seric miao static struct clk pxa3xx_clks[] = { 221dcc88a17SMark Brown { 222dcc88a17SMark Brown .name = "CLK_POUT", 223dcc88a17SMark Brown .ops = &clk_pout_ops, 224dcc88a17SMark Brown .rate = 13000000, 225dcc88a17SMark Brown .delay = 70, 226dcc88a17SMark Brown }, 227dcc88a17SMark Brown 2289ba63c4fSMike Rapoport /* Power I2C clock is always on */ 2299ba63c4fSMike Rapoport { 2309ba63c4fSMike Rapoport .name = "I2CCLK", 2319ba63c4fSMike Rapoport .ops = &clk_dummy_ops, 2329ba63c4fSMike Rapoport .dev = &pxa3xx_device_i2c_power.dev, 2339ba63c4fSMike Rapoport }, 2349ba63c4fSMike Rapoport 2352a0d7187Seric miao PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 2362a0d7187Seric miao PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 23760bfe7faSMark Brown PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), 2382c8086a5Seric miao 2392a0d7187Seric miao PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 2402a0d7187Seric miao PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 2412a0d7187Seric miao PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 2422c8086a5Seric miao 2432a0d7187Seric miao PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 2447a857620SPhilipp Zabel PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa27x_device_udc.dev), 245f92a629cSeric miao PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 24637320980Seric miao PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), 247d8e0db11Seric miao 248d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 249d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 250d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 251d8e0db11Seric miao PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 25275540c1aSeric miao PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), 25375540c1aSeric miao PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), 254fafc9d3fSBridge Wu 255fafc9d3fSBridge Wu PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 2568d33b055SBridge Wu PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 2572c8086a5Seric miao }; 2582c8086a5Seric miao 2597b5dea12SRussell King #ifdef CONFIG_PM 2607b5dea12SRussell King 2617b5dea12SRussell King #define ISRAM_START 0x5c000000 2627b5dea12SRussell King #define ISRAM_SIZE SZ_256K 2637b5dea12SRussell King 2647b5dea12SRussell King static void __iomem *sram; 2657b5dea12SRussell King static unsigned long wakeup_src; 2667b5dea12SRussell King 267c4d1fb62Seric miao #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 268c4d1fb62Seric miao #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 269c4d1fb62Seric miao 270649de51bSRobert Jarzmik enum { SLEEP_SAVE_CKENA, 271c4d1fb62Seric miao SLEEP_SAVE_CKENB, 272c4d1fb62Seric miao SLEEP_SAVE_ACCR, 273c4d1fb62Seric miao 274649de51bSRobert Jarzmik SLEEP_SAVE_COUNT, 275c4d1fb62Seric miao }; 276c4d1fb62Seric miao 2777b5dea12SRussell King static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 2787b5dea12SRussell King { 279c4d1fb62Seric miao SAVE(CKENA); 280c4d1fb62Seric miao SAVE(CKENB); 281c4d1fb62Seric miao SAVE(ACCR); 2827b5dea12SRussell King } 2837b5dea12SRussell King 2847b5dea12SRussell King static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 2857b5dea12SRussell King { 286c4d1fb62Seric miao RESTORE(ACCR); 287c4d1fb62Seric miao RESTORE(CKENA); 288c4d1fb62Seric miao RESTORE(CKENB); 2897b5dea12SRussell King } 2907b5dea12SRussell King 2917b5dea12SRussell King /* 2927b5dea12SRussell King * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 2937b5dea12SRussell King * memory controller has to be reinitialised, so we place some code 2947b5dea12SRussell King * in the SRAM to perform this function. 2957b5dea12SRussell King * 2967b5dea12SRussell King * We disable FIQs across the standby - otherwise, we might receive a 2977b5dea12SRussell King * FIQ while the SDRAM is unavailable. 2987b5dea12SRussell King */ 2997b5dea12SRussell King static void pxa3xx_cpu_standby(unsigned int pwrmode) 3007b5dea12SRussell King { 3017b5dea12SRussell King extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 3027b5dea12SRussell King void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 3037b5dea12SRussell King 3047b5dea12SRussell King memcpy_toio(sram + 0x8000, pm_enter_standby_start, 3057b5dea12SRussell King pm_enter_standby_end - pm_enter_standby_start); 3067b5dea12SRussell King 3077b5dea12SRussell King AD2D0SR = ~0; 3087b5dea12SRussell King AD2D1SR = ~0; 3097b5dea12SRussell King AD2D0ER = wakeup_src; 3107b5dea12SRussell King AD2D1ER = 0; 3117b5dea12SRussell King ASCR = ASCR; 3127b5dea12SRussell King ARSR = ARSR; 3137b5dea12SRussell King 3147b5dea12SRussell King local_fiq_disable(); 3157b5dea12SRussell King fn(pwrmode); 3167b5dea12SRussell King local_fiq_enable(); 3177b5dea12SRussell King 3187b5dea12SRussell King AD2D0ER = 0; 3197b5dea12SRussell King AD2D1ER = 0; 3207b5dea12SRussell King } 3217b5dea12SRussell King 322c4d1fb62Seric miao /* 323c4d1fb62Seric miao * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 324c4d1fb62Seric miao * PXA3xx development kits assumes that the resuming process continues 325c4d1fb62Seric miao * with the address stored within the first 4 bytes of SDRAM. The PSPR 326c4d1fb62Seric miao * register is used privately by BootROM and OBM, and _must_ be set to 327c4d1fb62Seric miao * 0x5c014000 for the moment. 328c4d1fb62Seric miao */ 329c4d1fb62Seric miao static void pxa3xx_cpu_pm_suspend(void) 330c4d1fb62Seric miao { 331c4d1fb62Seric miao volatile unsigned long *p = (volatile void *)0xc0000000; 332c4d1fb62Seric miao unsigned long saved_data = *p; 333c4d1fb62Seric miao 334c4d1fb62Seric miao extern void pxa3xx_cpu_suspend(void); 335c4d1fb62Seric miao extern void pxa3xx_cpu_resume(void); 336c4d1fb62Seric miao 337c4d1fb62Seric miao /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 338c4d1fb62Seric miao CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 339c4d1fb62Seric miao CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 340c4d1fb62Seric miao 341c4d1fb62Seric miao /* clear and setup wakeup source */ 342c4d1fb62Seric miao AD3SR = ~0; 343c4d1fb62Seric miao AD3ER = wakeup_src; 344c4d1fb62Seric miao ASCR = ASCR; 345c4d1fb62Seric miao ARSR = ARSR; 346c4d1fb62Seric miao 347c4d1fb62Seric miao PCFR |= (1u << 13); /* L1_DIS */ 348c4d1fb62Seric miao PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 349c4d1fb62Seric miao 350c4d1fb62Seric miao PSPR = 0x5c014000; 351c4d1fb62Seric miao 352c4d1fb62Seric miao /* overwrite with the resume address */ 353c4d1fb62Seric miao *p = virt_to_phys(pxa3xx_cpu_resume); 354c4d1fb62Seric miao 355c4d1fb62Seric miao pxa3xx_cpu_suspend(); 356c4d1fb62Seric miao 357c4d1fb62Seric miao *p = saved_data; 358c4d1fb62Seric miao 359c4d1fb62Seric miao AD3ER = 0; 360c4d1fb62Seric miao } 361c4d1fb62Seric miao 3627b5dea12SRussell King static void pxa3xx_cpu_pm_enter(suspend_state_t state) 3637b5dea12SRussell King { 3647b5dea12SRussell King /* 3657b5dea12SRussell King * Don't sleep if no wakeup sources are defined 3667b5dea12SRussell King */ 367b86a5da8SMark Brown if (wakeup_src == 0) { 368b86a5da8SMark Brown printk(KERN_ERR "Not suspending: no wakeup sources\n"); 3697b5dea12SRussell King return; 370b86a5da8SMark Brown } 3717b5dea12SRussell King 3727b5dea12SRussell King switch (state) { 3737b5dea12SRussell King case PM_SUSPEND_STANDBY: 3747b5dea12SRussell King pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 3757b5dea12SRussell King break; 3767b5dea12SRussell King 3777b5dea12SRussell King case PM_SUSPEND_MEM: 378c4d1fb62Seric miao pxa3xx_cpu_pm_suspend(); 3797b5dea12SRussell King break; 3807b5dea12SRussell King } 3817b5dea12SRussell King } 3827b5dea12SRussell King 3837b5dea12SRussell King static int pxa3xx_cpu_pm_valid(suspend_state_t state) 3847b5dea12SRussell King { 3857b5dea12SRussell King return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 3867b5dea12SRussell King } 3877b5dea12SRussell King 3887b5dea12SRussell King static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 389649de51bSRobert Jarzmik .save_count = SLEEP_SAVE_COUNT, 3907b5dea12SRussell King .save = pxa3xx_cpu_pm_save, 3917b5dea12SRussell King .restore = pxa3xx_cpu_pm_restore, 3927b5dea12SRussell King .valid = pxa3xx_cpu_pm_valid, 3937b5dea12SRussell King .enter = pxa3xx_cpu_pm_enter, 3947b5dea12SRussell King }; 3957b5dea12SRussell King 3967b5dea12SRussell King static void __init pxa3xx_init_pm(void) 3977b5dea12SRussell King { 3987b5dea12SRussell King sram = ioremap(ISRAM_START, ISRAM_SIZE); 3997b5dea12SRussell King if (!sram) { 4007b5dea12SRussell King printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 4017b5dea12SRussell King return; 4027b5dea12SRussell King } 4037b5dea12SRussell King 4047b5dea12SRussell King /* 4057b5dea12SRussell King * Since we copy wakeup code into the SRAM, we need to ensure 4067b5dea12SRussell King * that it is preserved over the low power modes. Note: bit 8 4077b5dea12SRussell King * is undocumented in the developer manual, but must be set. 4087b5dea12SRussell King */ 4097b5dea12SRussell King AD1R |= ADXR_L2 | ADXR_R0; 4107b5dea12SRussell King AD2R |= ADXR_L2 | ADXR_R0; 4117b5dea12SRussell King AD3R |= ADXR_L2 | ADXR_R0; 4127b5dea12SRussell King 4137b5dea12SRussell King /* 4147b5dea12SRussell King * Clear the resume enable registers. 4157b5dea12SRussell King */ 4167b5dea12SRussell King AD1D0ER = 0; 4177b5dea12SRussell King AD2D0ER = 0; 4187b5dea12SRussell King AD2D1ER = 0; 4197b5dea12SRussell King AD3ER = 0; 4207b5dea12SRussell King 4217b5dea12SRussell King pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 4227b5dea12SRussell King } 4237b5dea12SRussell King 4247b5dea12SRussell King static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 4257b5dea12SRussell King { 4267b5dea12SRussell King unsigned long flags, mask = 0; 4277b5dea12SRussell King 4287b5dea12SRussell King switch (irq) { 4297b5dea12SRussell King case IRQ_SSP3: 4307b5dea12SRussell King mask = ADXER_MFP_WSSP3; 4317b5dea12SRussell King break; 4327b5dea12SRussell King case IRQ_MSL: 4337b5dea12SRussell King mask = ADXER_WMSL0; 4347b5dea12SRussell King break; 4357b5dea12SRussell King case IRQ_USBH2: 4367b5dea12SRussell King case IRQ_USBH1: 4377b5dea12SRussell King mask = ADXER_WUSBH; 4387b5dea12SRussell King break; 4397b5dea12SRussell King case IRQ_KEYPAD: 4407b5dea12SRussell King mask = ADXER_WKP; 4417b5dea12SRussell King break; 4427b5dea12SRussell King case IRQ_AC97: 4437b5dea12SRussell King mask = ADXER_MFP_WAC97; 4447b5dea12SRussell King break; 4457b5dea12SRussell King case IRQ_USIM: 4467b5dea12SRussell King mask = ADXER_WUSIM0; 4477b5dea12SRussell King break; 4487b5dea12SRussell King case IRQ_SSP2: 4497b5dea12SRussell King mask = ADXER_MFP_WSSP2; 4507b5dea12SRussell King break; 4517b5dea12SRussell King case IRQ_I2C: 4527b5dea12SRussell King mask = ADXER_MFP_WI2C; 4537b5dea12SRussell King break; 4547b5dea12SRussell King case IRQ_STUART: 4557b5dea12SRussell King mask = ADXER_MFP_WUART3; 4567b5dea12SRussell King break; 4577b5dea12SRussell King case IRQ_BTUART: 4587b5dea12SRussell King mask = ADXER_MFP_WUART2; 4597b5dea12SRussell King break; 4607b5dea12SRussell King case IRQ_FFUART: 4617b5dea12SRussell King mask = ADXER_MFP_WUART1; 4627b5dea12SRussell King break; 4637b5dea12SRussell King case IRQ_MMC: 4647b5dea12SRussell King mask = ADXER_MFP_WMMC1; 4657b5dea12SRussell King break; 4667b5dea12SRussell King case IRQ_SSP: 4677b5dea12SRussell King mask = ADXER_MFP_WSSP1; 4687b5dea12SRussell King break; 4697b5dea12SRussell King case IRQ_RTCAlrm: 4707b5dea12SRussell King mask = ADXER_WRTC; 4717b5dea12SRussell King break; 4727b5dea12SRussell King case IRQ_SSP4: 4737b5dea12SRussell King mask = ADXER_MFP_WSSP4; 4747b5dea12SRussell King break; 4757b5dea12SRussell King case IRQ_TSI: 4767b5dea12SRussell King mask = ADXER_WTSI; 4777b5dea12SRussell King break; 4787b5dea12SRussell King case IRQ_USIM2: 4797b5dea12SRussell King mask = ADXER_WUSIM1; 4807b5dea12SRussell King break; 4817b5dea12SRussell King case IRQ_MMC2: 4827b5dea12SRussell King mask = ADXER_MFP_WMMC2; 4837b5dea12SRussell King break; 4847b5dea12SRussell King case IRQ_NAND: 4857b5dea12SRussell King mask = ADXER_MFP_WFLASH; 4867b5dea12SRussell King break; 4877b5dea12SRussell King case IRQ_USB2: 4887b5dea12SRussell King mask = ADXER_WUSB2; 4897b5dea12SRussell King break; 4907b5dea12SRussell King case IRQ_WAKEUP0: 4917b5dea12SRussell King mask = ADXER_WEXTWAKE0; 4927b5dea12SRussell King break; 4937b5dea12SRussell King case IRQ_WAKEUP1: 4947b5dea12SRussell King mask = ADXER_WEXTWAKE1; 4957b5dea12SRussell King break; 4967b5dea12SRussell King case IRQ_MMC3: 4977b5dea12SRussell King mask = ADXER_MFP_GEN12; 4987b5dea12SRussell King break; 499e1217707SMark Brown default: 500e1217707SMark Brown return -EINVAL; 5017b5dea12SRussell King } 5027b5dea12SRussell King 5037b5dea12SRussell King local_irq_save(flags); 5047b5dea12SRussell King if (on) 5057b5dea12SRussell King wakeup_src |= mask; 5067b5dea12SRussell King else 5077b5dea12SRussell King wakeup_src &= ~mask; 5087b5dea12SRussell King local_irq_restore(flags); 5097b5dea12SRussell King 5107b5dea12SRussell King return 0; 5117b5dea12SRussell King } 5127b5dea12SRussell King #else 5137b5dea12SRussell King static inline void pxa3xx_init_pm(void) {} 514b9e25aceSeric miao #define pxa3xx_set_wake NULL 5157b5dea12SRussell King #endif 5167b5dea12SRussell King 5172c8086a5Seric miao void __init pxa3xx_init_irq(void) 5182c8086a5Seric miao { 5192c8086a5Seric miao /* enable CP6 access */ 5202c8086a5Seric miao u32 value; 5212c8086a5Seric miao __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 5222c8086a5Seric miao value |= (1 << 6); 5232c8086a5Seric miao __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 5242c8086a5Seric miao 525b9e25aceSeric miao pxa_init_irq(56, pxa3xx_set_wake); 526b9e25aceSeric miao pxa_init_gpio(128, NULL); 5272c8086a5Seric miao } 5282c8086a5Seric miao 5292c8086a5Seric miao /* 5302c8086a5Seric miao * device registration specific to PXA3xx. 5312c8086a5Seric miao */ 5322c8086a5Seric miao 5339ba63c4fSMike Rapoport void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 5349ba63c4fSMike Rapoport { 53514758220SEric Miao pxa_register_device(&pxa3xx_device_i2c_power, info); 5369ba63c4fSMike Rapoport } 5379ba63c4fSMike Rapoport 5382c8086a5Seric miao static struct platform_device *devices[] __initdata = { 539284d115eSRussell King /* &pxa_device_udc, The UDC driver is PXA25x only */ 5402c8086a5Seric miao &pxa_device_ffuart, 5412c8086a5Seric miao &pxa_device_btuart, 5422c8086a5Seric miao &pxa_device_stuart, 5432c8086a5Seric miao &pxa_device_i2s, 5442c8086a5Seric miao &pxa_device_rtc, 545d8e0db11Seric miao &pxa27x_device_ssp1, 546d8e0db11Seric miao &pxa27x_device_ssp2, 547d8e0db11Seric miao &pxa27x_device_ssp3, 548d8e0db11Seric miao &pxa3xx_device_ssp4, 54975540c1aSeric miao &pxa27x_device_pwm0, 55075540c1aSeric miao &pxa27x_device_pwm1, 5512c8086a5Seric miao }; 5522c8086a5Seric miao 553c0165504Seric miao static struct sys_device pxa3xx_sysdev[] = { 554c0165504Seric miao { 555c0165504Seric miao .cls = &pxa_irq_sysclass, 55616dfdbf0Seric miao }, { 5574be35e23Seric miao .cls = &pxa3xx_mfp_sysclass, 5584be35e23Seric miao }, { 55916dfdbf0Seric miao .cls = &pxa_gpio_sysclass, 560c0165504Seric miao }, 561c0165504Seric miao }; 562c0165504Seric miao 5632c8086a5Seric miao static int __init pxa3xx_init(void) 5642c8086a5Seric miao { 565c0165504Seric miao int i, ret = 0; 5662c8086a5Seric miao 5672c8086a5Seric miao if (cpu_is_pxa3xx()) { 56804fef228SEric Miao 56904fef228SEric Miao reset_status = ARSR; 57004fef228SEric Miao 57186260f98SDmitry Krivoschekov /* 57286260f98SDmitry Krivoschekov * clear RDH bit every time after reset 57386260f98SDmitry Krivoschekov * 57486260f98SDmitry Krivoschekov * Note: the last 3 bits DxS are write-1-to-clear so carefully 57586260f98SDmitry Krivoschekov * preserve them here in case they will be referenced later 57686260f98SDmitry Krivoschekov */ 57786260f98SDmitry Krivoschekov ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 57886260f98SDmitry Krivoschekov 5792c8086a5Seric miao clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 5802c8086a5Seric miao 5812c8086a5Seric miao if ((ret = pxa_init_dma(32))) 5822c8086a5Seric miao return ret; 5832c8086a5Seric miao 5847b5dea12SRussell King pxa3xx_init_pm(); 5857b5dea12SRussell King 586c0165504Seric miao for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 587c0165504Seric miao ret = sysdev_register(&pxa3xx_sysdev[i]); 588c0165504Seric miao if (ret) 589c0165504Seric miao pr_err("failed to register sysdev[%d]\n", i); 5902c8086a5Seric miao } 591c0165504Seric miao 592c0165504Seric miao ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 593c0165504Seric miao } 594c0165504Seric miao 595c0165504Seric miao return ret; 5962c8086a5Seric miao } 5972c8086a5Seric miao 5981c104e0eSRussell King postcore_initcall(pxa3xx_init); 599