1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-pxa/pxa27x.c 4 * 5 * Author: Nicolas Pitre 6 * Created: Nov 05, 2002 7 * Copyright: MontaVista Software Inc. 8 * 9 * Code specific to PXA27x aka Bulverde. 10 */ 11 #include <linux/dmaengine.h> 12 #include <linux/dma/pxa-dma.h> 13 #include <linux/gpio.h> 14 #include <linux/gpio-pxa.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/irqchip.h> 19 #include <linux/suspend.h> 20 #include <linux/platform_device.h> 21 #include <linux/syscore_ops.h> 22 #include <linux/io.h> 23 #include <linux/irq.h> 24 #include <linux/platform_data/i2c-pxa.h> 25 #include <linux/platform_data/mmp_dma.h> 26 #include <linux/soc/pxa/cpu.h> 27 28 #include <asm/mach/map.h> 29 #include <asm/irq.h> 30 #include <asm/suspend.h> 31 #include "irqs.h" 32 #include "pxa27x.h" 33 #include "reset.h" 34 #include <linux/platform_data/usb-ohci-pxa27x.h> 35 #include "pm.h" 36 #include "addr-map.h" 37 #include "smemc.h" 38 39 #include "generic.h" 40 #include "devices.h" 41 #include <linux/clk-provider.h> 42 #include <linux/clkdev.h> 43 44 void pxa27x_clear_otgph(void) 45 { 46 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) 47 PSSR |= PSSR_OTGPH; 48 } 49 EXPORT_SYMBOL(pxa27x_clear_otgph); 50 51 static unsigned long ac97_reset_config[] = { 52 GPIO113_AC97_nRESET_GPIO_HIGH, 53 GPIO113_AC97_nRESET, 54 GPIO95_AC97_nRESET_GPIO_HIGH, 55 GPIO95_AC97_nRESET, 56 }; 57 58 void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio) 59 { 60 /* 61 * This helper function is used to work around a bug in the pxa27x's 62 * ac97 controller during a warm reset. The configuration of the 63 * reset_gpio is changed as follows: 64 * to_gpio == true: configured to generic output gpio and driven high 65 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET 66 */ 67 68 if (reset_gpio == 113) 69 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] : 70 &ac97_reset_config[1], 1); 71 72 if (reset_gpio == 95) 73 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] : 74 &ac97_reset_config[3], 1); 75 } 76 EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset); 77 78 #ifdef CONFIG_PM 79 80 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 81 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 82 83 /* 84 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM 85 */ 86 static unsigned int pwrmode = PWRMODE_SLEEP; 87 88 int pxa27x_set_pwrmode(unsigned int mode) 89 { 90 switch (mode) { 91 case PWRMODE_SLEEP: 92 case PWRMODE_DEEPSLEEP: 93 pwrmode = mode; 94 return 0; 95 } 96 97 return -EINVAL; 98 } 99 100 /* 101 * List of global PXA peripheral registers to preserve. 102 * More ones like CP and general purpose register values are preserved 103 * with the stack pointer in sleep.S. 104 */ 105 enum { 106 SLEEP_SAVE_PSTR, 107 SLEEP_SAVE_MDREFR, 108 SLEEP_SAVE_PCFR, 109 SLEEP_SAVE_COUNT 110 }; 111 112 void pxa27x_cpu_pm_save(unsigned long *sleep_save) 113 { 114 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); 115 SAVE(PCFR); 116 117 SAVE(PSTR); 118 } 119 120 void pxa27x_cpu_pm_restore(unsigned long *sleep_save) 121 { 122 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); 123 RESTORE(PCFR); 124 125 PSSR = PSSR_RDH | PSSR_PH; 126 127 RESTORE(PSTR); 128 } 129 130 void pxa27x_cpu_pm_enter(suspend_state_t state) 131 { 132 extern void pxa_cpu_standby(void); 133 #ifndef CONFIG_IWMMXT 134 u64 acc0; 135 136 #ifndef CONFIG_AS_IS_LLVM 137 asm volatile(".arch_extension xscale\n\t" 138 "mra %Q0, %R0, acc0" : "=r" (acc0)); 139 #else 140 asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0)); 141 #endif 142 #endif 143 144 /* ensure voltage-change sequencer not initiated, which hangs */ 145 PCFR &= ~PCFR_FVC; 146 147 /* Clear edge-detect status register. */ 148 PEDR = 0xDF12FE1B; 149 150 /* Clear reset status */ 151 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 152 153 switch (state) { 154 case PM_SUSPEND_STANDBY: 155 pxa_cpu_standby(); 156 break; 157 case PM_SUSPEND_MEM: 158 cpu_suspend(pwrmode, pxa27x_finish_suspend); 159 #ifndef CONFIG_IWMMXT 160 #ifndef CONFIG_AS_IS_LLVM 161 asm volatile(".arch_extension xscale\n\t" 162 "mar acc0, %Q0, %R0" : "=r" (acc0)); 163 #else 164 asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0)); 165 #endif 166 #endif 167 break; 168 } 169 } 170 171 static int pxa27x_cpu_pm_valid(suspend_state_t state) 172 { 173 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 174 } 175 176 static int pxa27x_cpu_pm_prepare(void) 177 { 178 /* set resume return address */ 179 PSPR = __pa_symbol(cpu_resume); 180 return 0; 181 } 182 183 static void pxa27x_cpu_pm_finish(void) 184 { 185 /* ensure not to come back here if it wasn't intended */ 186 PSPR = 0; 187 } 188 189 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { 190 .save_count = SLEEP_SAVE_COUNT, 191 .save = pxa27x_cpu_pm_save, 192 .restore = pxa27x_cpu_pm_restore, 193 .valid = pxa27x_cpu_pm_valid, 194 .enter = pxa27x_cpu_pm_enter, 195 .prepare = pxa27x_cpu_pm_prepare, 196 .finish = pxa27x_cpu_pm_finish, 197 }; 198 199 static void __init pxa27x_init_pm(void) 200 { 201 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; 202 } 203 #else 204 static inline void pxa27x_init_pm(void) {} 205 #endif 206 207 /* PXA27x: Various gpios can issue wakeup events. This logic only 208 * handles the simple cases, not the WEMUX2 and WEMUX3 options 209 */ 210 static int pxa27x_set_wake(struct irq_data *d, unsigned int on) 211 { 212 int gpio = pxa_irq_to_gpio(d->irq); 213 uint32_t mask; 214 215 if (gpio >= 0 && gpio < 128) 216 return gpio_set_wake(gpio, on); 217 218 if (d->irq == IRQ_KEYPAD) 219 return keypad_set_wake(on); 220 221 switch (d->irq) { 222 case IRQ_RTCAlrm: 223 mask = PWER_RTC; 224 break; 225 case IRQ_USB: 226 mask = 1u << 26; 227 break; 228 default: 229 return -EINVAL; 230 } 231 232 if (on) 233 PWER |= mask; 234 else 235 PWER &=~mask; 236 237 return 0; 238 } 239 240 void __init pxa27x_init_irq(void) 241 { 242 pxa_init_irq(34, pxa27x_set_wake); 243 } 244 245 static int __init 246 pxa27x_dt_init_irq(struct device_node *node, struct device_node *parent) 247 { 248 pxa_dt_irq_init(pxa27x_set_wake); 249 set_handle_irq(ichp_handle_irq); 250 251 return 0; 252 } 253 IRQCHIP_DECLARE(pxa27x_intc, "marvell,pxa-intc", pxa27x_dt_init_irq); 254 255 static struct map_desc pxa27x_io_desc[] __initdata = { 256 { /* Mem Ctl */ 257 .virtual = (unsigned long)SMEMC_VIRT, 258 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), 259 .length = SMEMC_SIZE, 260 .type = MT_DEVICE 261 }, { /* UNCACHED_PHYS_0 */ 262 .virtual = UNCACHED_PHYS_0, 263 .pfn = __phys_to_pfn(0x00000000), 264 .length = UNCACHED_PHYS_0_SIZE, 265 .type = MT_DEVICE 266 }, 267 }; 268 269 void __init pxa27x_map_io(void) 270 { 271 pxa_map_io(); 272 iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc)); 273 pxa27x_get_clk_frequency_khz(1); 274 } 275 276 /* 277 * device registration specific to PXA27x. 278 */ 279 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) 280 { 281 local_irq_disable(); 282 PCFR |= PCFR_PI2CEN; 283 local_irq_enable(); 284 pxa_register_device(&pxa27x_device_i2c_power, info); 285 } 286 287 static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { 288 .irq_base = PXA_GPIO_TO_IRQ(0), 289 .gpio_set_wake = gpio_set_wake, 290 }; 291 292 static struct platform_device *devices[] __initdata = { 293 &pxa27x_device_udc, 294 &pxa_device_pmu, 295 &pxa_device_i2s, 296 &pxa_device_asoc_ssp1, 297 &pxa_device_asoc_ssp2, 298 &pxa_device_asoc_ssp3, 299 &pxa_device_asoc_platform, 300 &pxa_device_rtc, 301 &pxa27x_device_ssp1, 302 &pxa27x_device_ssp2, 303 &pxa27x_device_ssp3, 304 &pxa27x_device_pwm0, 305 &pxa27x_device_pwm1, 306 }; 307 308 static const struct dma_slave_map pxa27x_slave_map[] = { 309 /* PXA25x, PXA27x and PXA3xx common entries */ 310 { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) }, 311 { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) }, 312 { "pxa2xx-ac97", "pcm_pcm_aux_mono_out", 313 PDMA_FILTER_PARAM(LOWEST, 10) }, 314 { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) }, 315 { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) }, 316 { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) }, 317 { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) }, 318 { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) }, 319 { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) }, 320 { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) }, 321 { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) }, 322 { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) }, 323 { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) }, 324 { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) }, 325 { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) }, 326 327 /* PXA27x specific map */ 328 { "pxa2xx-i2s", "rx", PDMA_FILTER_PARAM(LOWEST, 2) }, 329 { "pxa2xx-i2s", "tx", PDMA_FILTER_PARAM(LOWEST, 3) }, 330 { "pxa27x-camera.0", "CI_Y", PDMA_FILTER_PARAM(HIGHEST, 68) }, 331 { "pxa27x-camera.0", "CI_U", PDMA_FILTER_PARAM(HIGHEST, 69) }, 332 { "pxa27x-camera.0", "CI_V", PDMA_FILTER_PARAM(HIGHEST, 70) }, 333 }; 334 335 static struct mmp_dma_platdata pxa27x_dma_pdata = { 336 .dma_channels = 32, 337 .nb_requestors = 75, 338 .slave_map = pxa27x_slave_map, 339 .slave_map_cnt = ARRAY_SIZE(pxa27x_slave_map), 340 }; 341 342 static int __init pxa27x_init(void) 343 { 344 int ret = 0; 345 346 if (cpu_is_pxa27x()) { 347 348 pxa_register_wdt(RCSR); 349 350 pxa27x_init_pm(); 351 352 register_syscore_ops(&pxa_irq_syscore_ops); 353 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 354 355 if (!of_have_populated_dt()) { 356 pxa_register_device(&pxa27x_device_gpio, 357 &pxa27x_gpio_info); 358 pxa2xx_set_dmac_info(&pxa27x_dma_pdata); 359 ret = platform_add_devices(devices, 360 ARRAY_SIZE(devices)); 361 } 362 } 363 364 return ret; 365 } 366 367 postcore_initcall(pxa27x_init); 368