xref: /openbmc/linux/arch/arm/mach-pxa/pxa27x.c (revision b6dcefde)
1 /*
2  *  linux/arch/arm/mach-pxa/pxa27x.c
3  *
4  *  Author:	Nicolas Pitre
5  *  Created:	Nov 05, 2002
6  *  Copyright:	MontaVista Software Inc.
7  *
8  * Code specific to PXA27x aka Bulverde.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20 
21 #include <mach/hardware.h>
22 #include <asm/irq.h>
23 #include <mach/irqs.h>
24 #include <mach/gpio.h>
25 #include <mach/pxa27x.h>
26 #include <mach/reset.h>
27 #include <mach/ohci.h>
28 #include <mach/pm.h>
29 #include <mach/dma.h>
30 #include <plat/i2c.h>
31 
32 #include "generic.h"
33 #include "devices.h"
34 #include "clock.h"
35 
36 void pxa27x_clear_otgph(void)
37 {
38 	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
39 		PSSR |= PSSR_OTGPH;
40 }
41 EXPORT_SYMBOL(pxa27x_clear_otgph);
42 
43 /* Crystal clock: 13MHz */
44 #define BASE_CLK	13000000
45 
46 /*
47  * Get the clock frequency as reflected by CCSR and the turbo flag.
48  * We assume these values have been applied via a fcs.
49  * If info is not 0 we also display the current settings.
50  */
51 unsigned int pxa27x_get_clk_frequency_khz(int info)
52 {
53 	unsigned long ccsr, clkcfg;
54 	unsigned int l, L, m, M, n2, N, S;
55        	int cccr_a, t, ht, b;
56 
57 	ccsr = CCSR;
58 	cccr_a = CCCR & (1 << 25);
59 
60 	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
61 	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
62 	t  = clkcfg & (1 << 0);
63 	ht = clkcfg & (1 << 2);
64 	b  = clkcfg & (1 << 3);
65 
66 	l  = ccsr & 0x1f;
67 	n2 = (ccsr>>7) & 0xf;
68 	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
69 
70 	L  = l * BASE_CLK;
71 	N  = (L * n2) / 2;
72 	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
73 	S  = (b) ? L : (L/2);
74 
75 	if (info) {
76 		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
77 			L / 1000000, (L % 1000000) / 10000, l );
78 		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
79 			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
80 			(t) ? "" : "in" );
81 		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
82 			M / 1000000, (M % 1000000) / 10000, m );
83 		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
84 			S / 1000000, (S % 1000000) / 10000 );
85 	}
86 
87 	return (t) ? (N/1000) : (L/1000);
88 }
89 
90 /*
91  * Return the current mem clock frequency in units of 10kHz as
92  * reflected by CCCR[A], B, and L
93  */
94 unsigned int pxa27x_get_memclk_frequency_10khz(void)
95 {
96 	unsigned long ccsr, clkcfg;
97 	unsigned int l, L, m, M;
98        	int cccr_a, b;
99 
100 	ccsr = CCSR;
101 	cccr_a = CCCR & (1 << 25);
102 
103 	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
104 	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
105 	b = clkcfg & (1 << 3);
106 
107 	l = ccsr & 0x1f;
108 	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
109 
110 	L = l * BASE_CLK;
111 	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
112 
113 	return (M / 10000);
114 }
115 
116 /*
117  * Return the current LCD clock frequency in units of 10kHz as
118  */
119 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
120 {
121 	unsigned long ccsr;
122 	unsigned int l, L, k, K;
123 
124 	ccsr = CCSR;
125 
126 	l = ccsr & 0x1f;
127 	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
128 
129 	L = l * BASE_CLK;
130 	K = L / k;
131 
132 	return (K / 10000);
133 }
134 
135 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
136 {
137 	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
138 }
139 
140 static const struct clkops clk_pxa27x_lcd_ops = {
141 	.enable		= clk_cken_enable,
142 	.disable	= clk_cken_disable,
143 	.getrate	= clk_pxa27x_lcd_getrate,
144 };
145 
146 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
147 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
148 static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
149 static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
150 static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
151 static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
152 static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
153 static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
154 static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
155 static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
156 static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
157 static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
158 static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
159 static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
160 static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
161 static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
162 static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
163 static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
164 static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
165 static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
166 static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
167 static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
168 static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
169 static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
170 static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
171 
172 static struct clk_lookup pxa27x_clkregs[] = {
173 	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
174 	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
175 	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
176 	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
177 	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
178 	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
179 	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
180 	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
181 	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
182 	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
183 	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
184 	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
185 	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
186 	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
187 	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
188 	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
189 	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
190 	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
191 	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
192 	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
193 	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
194 	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
195 	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
196 	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
197 	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
198 	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
199 };
200 
201 #ifdef CONFIG_PM
202 
203 #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
204 #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
205 
206 /*
207  * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
208  */
209 static unsigned int pwrmode = PWRMODE_SLEEP;
210 
211 int __init pxa27x_set_pwrmode(unsigned int mode)
212 {
213 	switch (mode) {
214 	case PWRMODE_SLEEP:
215 	case PWRMODE_DEEPSLEEP:
216 		pwrmode = mode;
217 		return 0;
218 	}
219 
220 	return -EINVAL;
221 }
222 
223 /*
224  * List of global PXA peripheral registers to preserve.
225  * More ones like CP and general purpose register values are preserved
226  * with the stack pointer in sleep.S.
227  */
228 enum {
229 	SLEEP_SAVE_PSTR,
230 	SLEEP_SAVE_CKEN,
231 	SLEEP_SAVE_MDREFR,
232 	SLEEP_SAVE_PCFR,
233 	SLEEP_SAVE_COUNT
234 };
235 
236 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
237 {
238 	SAVE(MDREFR);
239 	SAVE(PCFR);
240 
241 	SAVE(CKEN);
242 	SAVE(PSTR);
243 }
244 
245 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
246 {
247 	RESTORE(MDREFR);
248 	RESTORE(PCFR);
249 
250 	PSSR = PSSR_RDH | PSSR_PH;
251 
252 	RESTORE(CKEN);
253 	RESTORE(PSTR);
254 }
255 
256 void pxa27x_cpu_pm_enter(suspend_state_t state)
257 {
258 	extern void pxa_cpu_standby(void);
259 
260 	/* ensure voltage-change sequencer not initiated, which hangs */
261 	PCFR &= ~PCFR_FVC;
262 
263 	/* Clear edge-detect status register. */
264 	PEDR = 0xDF12FE1B;
265 
266 	/* Clear reset status */
267 	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
268 
269 	switch (state) {
270 	case PM_SUSPEND_STANDBY:
271 		pxa_cpu_standby();
272 		break;
273 	case PM_SUSPEND_MEM:
274 		pxa27x_cpu_suspend(pwrmode);
275 		break;
276 	}
277 }
278 
279 static int pxa27x_cpu_pm_valid(suspend_state_t state)
280 {
281 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
282 }
283 
284 static int pxa27x_cpu_pm_prepare(void)
285 {
286 	/* set resume return address */
287 	PSPR = virt_to_phys(pxa_cpu_resume);
288 	return 0;
289 }
290 
291 static void pxa27x_cpu_pm_finish(void)
292 {
293 	/* ensure not to come back here if it wasn't intended */
294 	PSPR = 0;
295 }
296 
297 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
298 	.save_count	= SLEEP_SAVE_COUNT,
299 	.save		= pxa27x_cpu_pm_save,
300 	.restore	= pxa27x_cpu_pm_restore,
301 	.valid		= pxa27x_cpu_pm_valid,
302 	.enter		= pxa27x_cpu_pm_enter,
303 	.prepare	= pxa27x_cpu_pm_prepare,
304 	.finish		= pxa27x_cpu_pm_finish,
305 };
306 
307 static void __init pxa27x_init_pm(void)
308 {
309 	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
310 }
311 #else
312 static inline void pxa27x_init_pm(void) {}
313 #endif
314 
315 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
316  * handles the simple cases, not the WEMUX2 and WEMUX3 options
317  */
318 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
319 {
320 	int gpio = IRQ_TO_GPIO(irq);
321 	uint32_t mask;
322 
323 	if (gpio >= 0 && gpio < 128)
324 		return gpio_set_wake(gpio, on);
325 
326 	if (irq == IRQ_KEYPAD)
327 		return keypad_set_wake(on);
328 
329 	switch (irq) {
330 	case IRQ_RTCAlrm:
331 		mask = PWER_RTC;
332 		break;
333 	case IRQ_USB:
334 		mask = 1u << 26;
335 		break;
336 	default:
337 		return -EINVAL;
338 	}
339 
340 	if (on)
341 		PWER |= mask;
342 	else
343 		PWER &=~mask;
344 
345 	return 0;
346 }
347 
348 void __init pxa27x_init_irq(void)
349 {
350 	pxa_init_irq(34, pxa27x_set_wake);
351 	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
352 }
353 
354 /*
355  * device registration specific to PXA27x.
356  */
357 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
358 {
359 	local_irq_disable();
360 	PCFR |= PCFR_PI2CEN;
361 	local_irq_enable();
362 	pxa_register_device(&pxa27x_device_i2c_power, info);
363 }
364 
365 static struct platform_device *devices[] __initdata = {
366 	&pxa27x_device_udc,
367 	&pxa_device_i2s,
368 	&sa1100_device_rtc,
369 	&pxa_device_rtc,
370 	&pxa27x_device_ssp1,
371 	&pxa27x_device_ssp2,
372 	&pxa27x_device_ssp3,
373 	&pxa27x_device_pwm0,
374 	&pxa27x_device_pwm1,
375 };
376 
377 static struct sys_device pxa27x_sysdev[] = {
378 	{
379 		.cls	= &pxa_irq_sysclass,
380 	}, {
381 		.cls	= &pxa2xx_mfp_sysclass,
382 	}, {
383 		.cls	= &pxa_gpio_sysclass,
384 	},
385 };
386 
387 static int __init pxa27x_init(void)
388 {
389 	int i, ret = 0;
390 
391 	if (cpu_is_pxa27x()) {
392 
393 		reset_status = RCSR;
394 
395 		clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
396 
397 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
398 			return ret;
399 
400 		pxa27x_init_pm();
401 
402 		for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
403 			ret = sysdev_register(&pxa27x_sysdev[i]);
404 			if (ret)
405 				pr_err("failed to register sysdev[%d]\n", i);
406 		}
407 
408 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
409 	}
410 
411 	return ret;
412 }
413 
414 postcore_initcall(pxa27x_init);
415