1 /* 2 * linux/arch/arm/mach-pxa/pxa27x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Nov 05, 2002 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA27x aka Bulverde. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/platform_device.h> 19 #include <linux/sysdev.h> 20 21 #include <mach/hardware.h> 22 #include <asm/irq.h> 23 #include <mach/irqs.h> 24 #include <mach/gpio.h> 25 #include <mach/pxa27x.h> 26 #include <mach/reset.h> 27 #include <mach/ohci.h> 28 #include <mach/pm.h> 29 #include <mach/dma.h> 30 #include <mach/i2c.h> 31 32 #include "generic.h" 33 #include "devices.h" 34 #include "clock.h" 35 36 void pxa27x_clear_otgph(void) 37 { 38 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) 39 PSSR |= PSSR_OTGPH; 40 } 41 EXPORT_SYMBOL(pxa27x_clear_otgph); 42 43 /* Crystal clock: 13MHz */ 44 #define BASE_CLK 13000000 45 46 /* 47 * Get the clock frequency as reflected by CCSR and the turbo flag. 48 * We assume these values have been applied via a fcs. 49 * If info is not 0 we also display the current settings. 50 */ 51 unsigned int pxa27x_get_clk_frequency_khz(int info) 52 { 53 unsigned long ccsr, clkcfg; 54 unsigned int l, L, m, M, n2, N, S; 55 int cccr_a, t, ht, b; 56 57 ccsr = CCSR; 58 cccr_a = CCCR & (1 << 25); 59 60 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ 61 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); 62 t = clkcfg & (1 << 0); 63 ht = clkcfg & (1 << 2); 64 b = clkcfg & (1 << 3); 65 66 l = ccsr & 0x1f; 67 n2 = (ccsr>>7) & 0xf; 68 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; 69 70 L = l * BASE_CLK; 71 N = (L * n2) / 2; 72 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); 73 S = (b) ? L : (L/2); 74 75 if (info) { 76 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 77 L / 1000000, (L % 1000000) / 10000, l ); 78 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 79 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, 80 (t) ? "" : "in" ); 81 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", 82 M / 1000000, (M % 1000000) / 10000, m ); 83 printk( KERN_INFO "System bus clock: %d.%02dMHz \n", 84 S / 1000000, (S % 1000000) / 10000 ); 85 } 86 87 return (t) ? (N/1000) : (L/1000); 88 } 89 90 /* 91 * Return the current mem clock frequency in units of 10kHz as 92 * reflected by CCCR[A], B, and L 93 */ 94 unsigned int pxa27x_get_memclk_frequency_10khz(void) 95 { 96 unsigned long ccsr, clkcfg; 97 unsigned int l, L, m, M; 98 int cccr_a, b; 99 100 ccsr = CCSR; 101 cccr_a = CCCR & (1 << 25); 102 103 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ 104 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); 105 b = clkcfg & (1 << 3); 106 107 l = ccsr & 0x1f; 108 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; 109 110 L = l * BASE_CLK; 111 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); 112 113 return (M / 10000); 114 } 115 116 /* 117 * Return the current LCD clock frequency in units of 10kHz as 118 */ 119 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) 120 { 121 unsigned long ccsr; 122 unsigned int l, L, k, K; 123 124 ccsr = CCSR; 125 126 l = ccsr & 0x1f; 127 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; 128 129 L = l * BASE_CLK; 130 K = L / k; 131 132 return (K / 10000); 133 } 134 135 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) 136 { 137 return pxa27x_get_lcdclk_frequency_10khz() * 10000; 138 } 139 140 static const struct clkops clk_pxa27x_lcd_ops = { 141 .enable = clk_cken_enable, 142 .disable = clk_cken_disable, 143 .getrate = clk_pxa27x_lcd_getrate, 144 }; 145 146 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); 147 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); 148 static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); 149 static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1); 150 static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1); 151 static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0); 152 static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0); 153 static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5); 154 static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0); 155 static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0); 156 static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); 157 static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); 158 static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); 159 static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); 160 static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); 161 static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); 162 static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); 163 static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); 164 static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0); 165 static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); 166 static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0); 167 static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0); 168 static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); 169 static DEFINE_CKEN(pxa27x_im, IM, 0, 0); 170 static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0); 171 172 static struct clk_lookup pxa27x_clkregs[] = { 173 INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), 174 INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL), 175 INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL), 176 INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL), 177 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL), 178 INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL), 179 INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL), 180 INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL), 181 INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL), 182 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"), 183 INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"), 184 INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL), 185 INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL), 186 INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL), 187 INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL), 188 INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL), 189 INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL), 190 INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL), 191 INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL), 192 INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"), 193 INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"), 194 INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"), 195 INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"), 196 INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), 197 INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), 198 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), 199 }; 200 201 #ifdef CONFIG_PM 202 203 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 204 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 205 206 /* 207 * List of global PXA peripheral registers to preserve. 208 * More ones like CP and general purpose register values are preserved 209 * with the stack pointer in sleep.S. 210 */ 211 enum { 212 SLEEP_SAVE_PSTR, 213 SLEEP_SAVE_CKEN, 214 SLEEP_SAVE_MDREFR, 215 SLEEP_SAVE_PCFR, 216 SLEEP_SAVE_COUNT 217 }; 218 219 void pxa27x_cpu_pm_save(unsigned long *sleep_save) 220 { 221 SAVE(MDREFR); 222 SAVE(PCFR); 223 224 SAVE(CKEN); 225 SAVE(PSTR); 226 } 227 228 void pxa27x_cpu_pm_restore(unsigned long *sleep_save) 229 { 230 RESTORE(MDREFR); 231 RESTORE(PCFR); 232 233 PSSR = PSSR_RDH | PSSR_PH; 234 235 RESTORE(CKEN); 236 RESTORE(PSTR); 237 } 238 239 void pxa27x_cpu_pm_enter(suspend_state_t state) 240 { 241 extern void pxa_cpu_standby(void); 242 243 /* ensure voltage-change sequencer not initiated, which hangs */ 244 PCFR &= ~PCFR_FVC; 245 246 /* Clear edge-detect status register. */ 247 PEDR = 0xDF12FE1B; 248 249 /* Clear reset status */ 250 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 251 252 switch (state) { 253 case PM_SUSPEND_STANDBY: 254 pxa_cpu_standby(); 255 break; 256 case PM_SUSPEND_MEM: 257 pxa27x_cpu_suspend(PWRMODE_SLEEP); 258 break; 259 } 260 } 261 262 static int pxa27x_cpu_pm_valid(suspend_state_t state) 263 { 264 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 265 } 266 267 static int pxa27x_cpu_pm_prepare(void) 268 { 269 /* set resume return address */ 270 PSPR = virt_to_phys(pxa_cpu_resume); 271 return 0; 272 } 273 274 static void pxa27x_cpu_pm_finish(void) 275 { 276 /* ensure not to come back here if it wasn't intended */ 277 PSPR = 0; 278 } 279 280 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { 281 .save_count = SLEEP_SAVE_COUNT, 282 .save = pxa27x_cpu_pm_save, 283 .restore = pxa27x_cpu_pm_restore, 284 .valid = pxa27x_cpu_pm_valid, 285 .enter = pxa27x_cpu_pm_enter, 286 .prepare = pxa27x_cpu_pm_prepare, 287 .finish = pxa27x_cpu_pm_finish, 288 }; 289 290 static void __init pxa27x_init_pm(void) 291 { 292 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; 293 } 294 #else 295 static inline void pxa27x_init_pm(void) {} 296 #endif 297 298 /* PXA27x: Various gpios can issue wakeup events. This logic only 299 * handles the simple cases, not the WEMUX2 and WEMUX3 options 300 */ 301 static int pxa27x_set_wake(unsigned int irq, unsigned int on) 302 { 303 int gpio = IRQ_TO_GPIO(irq); 304 uint32_t mask; 305 306 if (gpio >= 0 && gpio < 128) 307 return gpio_set_wake(gpio, on); 308 309 if (irq == IRQ_KEYPAD) 310 return keypad_set_wake(on); 311 312 switch (irq) { 313 case IRQ_RTCAlrm: 314 mask = PWER_RTC; 315 break; 316 case IRQ_USB: 317 mask = 1u << 26; 318 break; 319 default: 320 return -EINVAL; 321 } 322 323 if (on) 324 PWER |= mask; 325 else 326 PWER &=~mask; 327 328 return 0; 329 } 330 331 void __init pxa27x_init_irq(void) 332 { 333 pxa_init_irq(34, pxa27x_set_wake); 334 pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); 335 } 336 337 /* 338 * device registration specific to PXA27x. 339 */ 340 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) 341 { 342 local_irq_disable(); 343 PCFR |= PCFR_PI2CEN; 344 local_irq_enable(); 345 pxa_register_device(&pxa27x_device_i2c_power, info); 346 } 347 348 static struct platform_device *devices[] __initdata = { 349 &pxa27x_device_udc, 350 &pxa_device_ffuart, 351 &pxa_device_btuart, 352 &pxa_device_stuart, 353 &pxa_device_i2s, 354 &sa1100_device_rtc, 355 &pxa_device_rtc, 356 &pxa27x_device_ssp1, 357 &pxa27x_device_ssp2, 358 &pxa27x_device_ssp3, 359 &pxa27x_device_pwm0, 360 &pxa27x_device_pwm1, 361 }; 362 363 static struct sys_device pxa27x_sysdev[] = { 364 { 365 .cls = &pxa_irq_sysclass, 366 }, { 367 .cls = &pxa2xx_mfp_sysclass, 368 }, { 369 .cls = &pxa_gpio_sysclass, 370 }, 371 }; 372 373 static int __init pxa27x_init(void) 374 { 375 int i, ret = 0; 376 377 if (cpu_is_pxa27x()) { 378 379 reset_status = RCSR; 380 381 clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); 382 383 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 384 return ret; 385 386 pxa27x_init_pm(); 387 388 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { 389 ret = sysdev_register(&pxa27x_sysdev[i]); 390 if (ret) 391 pr_err("failed to register sysdev[%d]\n", i); 392 } 393 394 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 395 } 396 397 return ret; 398 } 399 400 postcore_initcall(pxa27x_init); 401