xref: /openbmc/linux/arch/arm/mach-pxa/pxa27x.c (revision a8fe58ce) 
1 /*
2  *  linux/arch/arm/mach-pxa/pxa27x.c
3  *
4  *  Author:	Nicolas Pitre
5  *  Created:	Nov 05, 2002
6  *  Copyright:	MontaVista Software Inc.
7  *
8  * Code specific to PXA27x aka Bulverde.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 #include <linux/gpio.h>
15 #include <linux/gpio-pxa.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/suspend.h>
20 #include <linux/platform_device.h>
21 #include <linux/syscore_ops.h>
22 #include <linux/io.h>
23 #include <linux/irq.h>
24 #include <linux/i2c/pxa-i2c.h>
25 
26 #include <asm/mach/map.h>
27 #include <mach/hardware.h>
28 #include <asm/irq.h>
29 #include <asm/suspend.h>
30 #include <mach/irqs.h>
31 #include "pxa27x.h"
32 #include <mach/reset.h>
33 #include <linux/platform_data/usb-ohci-pxa27x.h>
34 #include "pm.h"
35 #include <mach/dma.h>
36 #include <mach/smemc.h>
37 
38 #include "generic.h"
39 #include "devices.h"
40 #include <linux/clk-provider.h>
41 #include <linux/clkdev.h>
42 
43 void pxa27x_clear_otgph(void)
44 {
45 	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
46 		PSSR |= PSSR_OTGPH;
47 }
48 EXPORT_SYMBOL(pxa27x_clear_otgph);
49 
50 static unsigned long ac97_reset_config[] = {
51 	GPIO113_AC97_nRESET_GPIO_HIGH,
52 	GPIO113_AC97_nRESET,
53 	GPIO95_AC97_nRESET_GPIO_HIGH,
54 	GPIO95_AC97_nRESET,
55 };
56 
57 void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
58 {
59 	/*
60 	 * This helper function is used to work around a bug in the pxa27x's
61 	 * ac97 controller during a warm reset.  The configuration of the
62 	 * reset_gpio is changed as follows:
63 	 * to_gpio == true: configured to generic output gpio and driven high
64 	 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
65 	 */
66 
67 	if (reset_gpio == 113)
68 		pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
69 				  &ac97_reset_config[1], 1);
70 
71 	if (reset_gpio == 95)
72 		pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
73 				  &ac97_reset_config[3], 1);
74 }
75 EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
76 
77 #ifdef CONFIG_PM
78 
79 #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
80 #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
81 
82 /*
83  * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
84  */
85 static unsigned int pwrmode = PWRMODE_SLEEP;
86 
87 int pxa27x_set_pwrmode(unsigned int mode)
88 {
89 	switch (mode) {
90 	case PWRMODE_SLEEP:
91 	case PWRMODE_DEEPSLEEP:
92 		pwrmode = mode;
93 		return 0;
94 	}
95 
96 	return -EINVAL;
97 }
98 
99 /*
100  * List of global PXA peripheral registers to preserve.
101  * More ones like CP and general purpose register values are preserved
102  * with the stack pointer in sleep.S.
103  */
104 enum {
105 	SLEEP_SAVE_PSTR,
106 	SLEEP_SAVE_MDREFR,
107 	SLEEP_SAVE_PCFR,
108 	SLEEP_SAVE_COUNT
109 };
110 
111 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
112 {
113 	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
114 	SAVE(PCFR);
115 
116 	SAVE(PSTR);
117 }
118 
119 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
120 {
121 	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
122 	RESTORE(PCFR);
123 
124 	PSSR = PSSR_RDH | PSSR_PH;
125 
126 	RESTORE(PSTR);
127 }
128 
129 void pxa27x_cpu_pm_enter(suspend_state_t state)
130 {
131 	extern void pxa_cpu_standby(void);
132 #ifndef CONFIG_IWMMXT
133 	u64 acc0;
134 
135 	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
136 #endif
137 
138 	/* ensure voltage-change sequencer not initiated, which hangs */
139 	PCFR &= ~PCFR_FVC;
140 
141 	/* Clear edge-detect status register. */
142 	PEDR = 0xDF12FE1B;
143 
144 	/* Clear reset status */
145 	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
146 
147 	switch (state) {
148 	case PM_SUSPEND_STANDBY:
149 		pxa_cpu_standby();
150 		break;
151 	case PM_SUSPEND_MEM:
152 		cpu_suspend(pwrmode, pxa27x_finish_suspend);
153 #ifndef CONFIG_IWMMXT
154 		asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
155 #endif
156 		break;
157 	}
158 }
159 
160 static int pxa27x_cpu_pm_valid(suspend_state_t state)
161 {
162 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
163 }
164 
165 static int pxa27x_cpu_pm_prepare(void)
166 {
167 	/* set resume return address */
168 	PSPR = virt_to_phys(cpu_resume);
169 	return 0;
170 }
171 
172 static void pxa27x_cpu_pm_finish(void)
173 {
174 	/* ensure not to come back here if it wasn't intended */
175 	PSPR = 0;
176 }
177 
178 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
179 	.save_count	= SLEEP_SAVE_COUNT,
180 	.save		= pxa27x_cpu_pm_save,
181 	.restore	= pxa27x_cpu_pm_restore,
182 	.valid		= pxa27x_cpu_pm_valid,
183 	.enter		= pxa27x_cpu_pm_enter,
184 	.prepare	= pxa27x_cpu_pm_prepare,
185 	.finish		= pxa27x_cpu_pm_finish,
186 };
187 
188 static void __init pxa27x_init_pm(void)
189 {
190 	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
191 }
192 #else
193 static inline void pxa27x_init_pm(void) {}
194 #endif
195 
196 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
197  * handles the simple cases, not the WEMUX2 and WEMUX3 options
198  */
199 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
200 {
201 	int gpio = pxa_irq_to_gpio(d->irq);
202 	uint32_t mask;
203 
204 	if (gpio >= 0 && gpio < 128)
205 		return gpio_set_wake(gpio, on);
206 
207 	if (d->irq == IRQ_KEYPAD)
208 		return keypad_set_wake(on);
209 
210 	switch (d->irq) {
211 	case IRQ_RTCAlrm:
212 		mask = PWER_RTC;
213 		break;
214 	case IRQ_USB:
215 		mask = 1u << 26;
216 		break;
217 	default:
218 		return -EINVAL;
219 	}
220 
221 	if (on)
222 		PWER |= mask;
223 	else
224 		PWER &=~mask;
225 
226 	return 0;
227 }
228 
229 void __init pxa27x_init_irq(void)
230 {
231 	pxa_init_irq(34, pxa27x_set_wake);
232 }
233 
234 void __init pxa27x_dt_init_irq(void)
235 {
236 	if (IS_ENABLED(CONFIG_OF))
237 		pxa_dt_irq_init(pxa27x_set_wake);
238 }
239 
240 static struct map_desc pxa27x_io_desc[] __initdata = {
241 	{	/* Mem Ctl */
242 		.virtual	= (unsigned long)SMEMC_VIRT,
243 		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
244 		.length		= SMEMC_SIZE,
245 		.type		= MT_DEVICE
246 	}, {	/* UNCACHED_PHYS_0 */
247 		.virtual	= UNCACHED_PHYS_0,
248 		.pfn		= __phys_to_pfn(0x00000000),
249 		.length		= UNCACHED_PHYS_0_SIZE,
250 		.type		= MT_DEVICE
251 	},
252 };
253 
254 void __init pxa27x_map_io(void)
255 {
256 	pxa_map_io();
257 	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
258 	pxa27x_get_clk_frequency_khz(1);
259 }
260 
261 /*
262  * device registration specific to PXA27x.
263  */
264 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
265 {
266 	local_irq_disable();
267 	PCFR |= PCFR_PI2CEN;
268 	local_irq_enable();
269 	pxa_register_device(&pxa27x_device_i2c_power, info);
270 }
271 
272 static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
273 	.irq_base	= PXA_GPIO_TO_IRQ(0),
274 	.gpio_set_wake	= gpio_set_wake,
275 };
276 
277 static struct platform_device *devices[] __initdata = {
278 	&pxa27x_device_udc,
279 	&pxa_device_pmu,
280 	&pxa_device_i2s,
281 	&pxa_device_asoc_ssp1,
282 	&pxa_device_asoc_ssp2,
283 	&pxa_device_asoc_ssp3,
284 	&pxa_device_asoc_platform,
285 	&pxa_device_rtc,
286 	&pxa27x_device_ssp1,
287 	&pxa27x_device_ssp2,
288 	&pxa27x_device_ssp3,
289 	&pxa27x_device_pwm0,
290 	&pxa27x_device_pwm1,
291 };
292 
293 static int __init pxa27x_init(void)
294 {
295 	int ret = 0;
296 
297 	if (cpu_is_pxa27x()) {
298 
299 		reset_status = RCSR;
300 
301 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
302 			return ret;
303 
304 		pxa27x_init_pm();
305 
306 		register_syscore_ops(&pxa_irq_syscore_ops);
307 		register_syscore_ops(&pxa2xx_mfp_syscore_ops);
308 
309 		if (!of_have_populated_dt()) {
310 			pxa_register_device(&pxa27x_device_gpio,
311 					    &pxa27x_gpio_info);
312 			pxa2xx_set_dmac_info(32);
313 			ret = platform_add_devices(devices,
314 						   ARRAY_SIZE(devices));
315 		}
316 	}
317 
318 	return ret;
319 }
320 
321 postcore_initcall(pxa27x_init);
322