1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-pxa/pxa27x.c 4 * 5 * Author: Nicolas Pitre 6 * Created: Nov 05, 2002 7 * Copyright: MontaVista Software Inc. 8 * 9 * Code specific to PXA27x aka Bulverde. 10 */ 11 #include <linux/dmaengine.h> 12 #include <linux/dma/pxa-dma.h> 13 #include <linux/gpio.h> 14 #include <linux/gpio-pxa.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/irqchip.h> 19 #include <linux/suspend.h> 20 #include <linux/platform_device.h> 21 #include <linux/syscore_ops.h> 22 #include <linux/io.h> 23 #include <linux/irq.h> 24 #include <linux/platform_data/i2c-pxa.h> 25 #include <linux/platform_data/mmp_dma.h> 26 #include <linux/soc/pxa/cpu.h> 27 28 #include <asm/mach/map.h> 29 #include <asm/irq.h> 30 #include <asm/suspend.h> 31 #include "irqs.h" 32 #include "pxa27x.h" 33 #include "reset.h" 34 #include <linux/platform_data/usb-ohci-pxa27x.h> 35 #include "pm.h" 36 #include "addr-map.h" 37 #include "smemc.h" 38 39 #include "generic.h" 40 #include "devices.h" 41 #include <linux/clk-provider.h> 42 #include <linux/clkdev.h> 43 44 void pxa27x_clear_otgph(void) 45 { 46 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) 47 PSSR |= PSSR_OTGPH; 48 } 49 EXPORT_SYMBOL(pxa27x_clear_otgph); 50 51 static unsigned long ac97_reset_config[] = { 52 GPIO113_AC97_nRESET_GPIO_HIGH, 53 GPIO113_AC97_nRESET, 54 GPIO95_AC97_nRESET_GPIO_HIGH, 55 GPIO95_AC97_nRESET, 56 }; 57 58 void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio) 59 { 60 /* 61 * This helper function is used to work around a bug in the pxa27x's 62 * ac97 controller during a warm reset. The configuration of the 63 * reset_gpio is changed as follows: 64 * to_gpio == true: configured to generic output gpio and driven high 65 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET 66 */ 67 68 if (reset_gpio == 113) 69 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] : 70 &ac97_reset_config[1], 1); 71 72 if (reset_gpio == 95) 73 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] : 74 &ac97_reset_config[3], 1); 75 } 76 EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset); 77 78 #ifdef CONFIG_PM 79 80 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 81 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 82 83 /* 84 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM 85 */ 86 static unsigned int pwrmode = PWRMODE_SLEEP; 87 88 /* 89 * List of global PXA peripheral registers to preserve. 90 * More ones like CP and general purpose register values are preserved 91 * with the stack pointer in sleep.S. 92 */ 93 enum { 94 SLEEP_SAVE_PSTR, 95 SLEEP_SAVE_MDREFR, 96 SLEEP_SAVE_PCFR, 97 SLEEP_SAVE_COUNT 98 }; 99 100 static void pxa27x_cpu_pm_save(unsigned long *sleep_save) 101 { 102 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); 103 SAVE(PCFR); 104 105 SAVE(PSTR); 106 } 107 108 static void pxa27x_cpu_pm_restore(unsigned long *sleep_save) 109 { 110 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); 111 RESTORE(PCFR); 112 113 PSSR = PSSR_RDH | PSSR_PH; 114 115 RESTORE(PSTR); 116 } 117 118 static void pxa27x_cpu_pm_enter(suspend_state_t state) 119 { 120 extern void pxa_cpu_standby(void); 121 #ifndef CONFIG_IWMMXT 122 u64 acc0; 123 124 #ifndef CONFIG_AS_IS_LLVM 125 asm volatile(".arch_extension xscale\n\t" 126 "mra %Q0, %R0, acc0" : "=r" (acc0)); 127 #else 128 asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0)); 129 #endif 130 #endif 131 132 /* ensure voltage-change sequencer not initiated, which hangs */ 133 PCFR &= ~PCFR_FVC; 134 135 /* Clear edge-detect status register. */ 136 PEDR = 0xDF12FE1B; 137 138 /* Clear reset status */ 139 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 140 141 switch (state) { 142 case PM_SUSPEND_STANDBY: 143 pxa_cpu_standby(); 144 break; 145 case PM_SUSPEND_MEM: 146 cpu_suspend(pwrmode, pxa27x_finish_suspend); 147 #ifndef CONFIG_IWMMXT 148 #ifndef CONFIG_AS_IS_LLVM 149 asm volatile(".arch_extension xscale\n\t" 150 "mar acc0, %Q0, %R0" : "=r" (acc0)); 151 #else 152 asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0)); 153 #endif 154 #endif 155 break; 156 } 157 } 158 159 static int pxa27x_cpu_pm_valid(suspend_state_t state) 160 { 161 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 162 } 163 164 static int pxa27x_cpu_pm_prepare(void) 165 { 166 /* set resume return address */ 167 PSPR = __pa_symbol(cpu_resume); 168 return 0; 169 } 170 171 static void pxa27x_cpu_pm_finish(void) 172 { 173 /* ensure not to come back here if it wasn't intended */ 174 PSPR = 0; 175 } 176 177 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { 178 .save_count = SLEEP_SAVE_COUNT, 179 .save = pxa27x_cpu_pm_save, 180 .restore = pxa27x_cpu_pm_restore, 181 .valid = pxa27x_cpu_pm_valid, 182 .enter = pxa27x_cpu_pm_enter, 183 .prepare = pxa27x_cpu_pm_prepare, 184 .finish = pxa27x_cpu_pm_finish, 185 }; 186 187 static void __init pxa27x_init_pm(void) 188 { 189 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; 190 } 191 #else 192 static inline void pxa27x_init_pm(void) {} 193 #endif 194 195 /* PXA27x: Various gpios can issue wakeup events. This logic only 196 * handles the simple cases, not the WEMUX2 and WEMUX3 options 197 */ 198 static int pxa27x_set_wake(struct irq_data *d, unsigned int on) 199 { 200 int gpio = pxa_irq_to_gpio(d->irq); 201 uint32_t mask; 202 203 if (gpio >= 0 && gpio < 128) 204 return gpio_set_wake(gpio, on); 205 206 if (d->irq == IRQ_KEYPAD) 207 return keypad_set_wake(on); 208 209 switch (d->irq) { 210 case IRQ_RTCAlrm: 211 mask = PWER_RTC; 212 break; 213 case IRQ_USB: 214 mask = 1u << 26; 215 break; 216 default: 217 return -EINVAL; 218 } 219 220 if (on) 221 PWER |= mask; 222 else 223 PWER &=~mask; 224 225 return 0; 226 } 227 228 void __init pxa27x_init_irq(void) 229 { 230 pxa_init_irq(34, pxa27x_set_wake); 231 } 232 233 static int __init 234 pxa27x_dt_init_irq(struct device_node *node, struct device_node *parent) 235 { 236 pxa_dt_irq_init(pxa27x_set_wake); 237 set_handle_irq(ichp_handle_irq); 238 239 return 0; 240 } 241 IRQCHIP_DECLARE(pxa27x_intc, "marvell,pxa-intc", pxa27x_dt_init_irq); 242 243 static struct map_desc pxa27x_io_desc[] __initdata = { 244 { /* Mem Ctl */ 245 .virtual = (unsigned long)SMEMC_VIRT, 246 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), 247 .length = SMEMC_SIZE, 248 .type = MT_DEVICE 249 }, { /* UNCACHED_PHYS_0 */ 250 .virtual = UNCACHED_PHYS_0, 251 .pfn = __phys_to_pfn(0x00000000), 252 .length = UNCACHED_PHYS_0_SIZE, 253 .type = MT_DEVICE 254 }, 255 }; 256 257 void __init pxa27x_map_io(void) 258 { 259 pxa_map_io(); 260 iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc)); 261 pxa27x_get_clk_frequency_khz(1); 262 } 263 264 /* 265 * device registration specific to PXA27x. 266 */ 267 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) 268 { 269 local_irq_disable(); 270 PCFR |= PCFR_PI2CEN; 271 local_irq_enable(); 272 pxa_register_device(&pxa27x_device_i2c_power, info); 273 } 274 275 static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { 276 .irq_base = PXA_GPIO_TO_IRQ(0), 277 .gpio_set_wake = gpio_set_wake, 278 }; 279 280 static struct platform_device *devices[] __initdata = { 281 &pxa27x_device_udc, 282 &pxa_device_pmu, 283 &pxa_device_i2s, 284 &pxa_device_asoc_ssp1, 285 &pxa_device_asoc_ssp2, 286 &pxa_device_asoc_ssp3, 287 &pxa_device_asoc_platform, 288 &pxa_device_rtc, 289 &pxa27x_device_ssp1, 290 &pxa27x_device_ssp2, 291 &pxa27x_device_ssp3, 292 &pxa27x_device_pwm0, 293 &pxa27x_device_pwm1, 294 }; 295 296 static const struct dma_slave_map pxa27x_slave_map[] = { 297 /* PXA25x, PXA27x and PXA3xx common entries */ 298 { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) }, 299 { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) }, 300 { "pxa2xx-ac97", "pcm_pcm_aux_mono_out", 301 PDMA_FILTER_PARAM(LOWEST, 10) }, 302 { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) }, 303 { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) }, 304 { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) }, 305 { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) }, 306 { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) }, 307 { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) }, 308 { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) }, 309 { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) }, 310 { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) }, 311 { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) }, 312 { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) }, 313 { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) }, 314 315 /* PXA27x specific map */ 316 { "pxa2xx-i2s", "rx", PDMA_FILTER_PARAM(LOWEST, 2) }, 317 { "pxa2xx-i2s", "tx", PDMA_FILTER_PARAM(LOWEST, 3) }, 318 { "pxa27x-camera.0", "CI_Y", PDMA_FILTER_PARAM(HIGHEST, 68) }, 319 { "pxa27x-camera.0", "CI_U", PDMA_FILTER_PARAM(HIGHEST, 69) }, 320 { "pxa27x-camera.0", "CI_V", PDMA_FILTER_PARAM(HIGHEST, 70) }, 321 }; 322 323 static struct mmp_dma_platdata pxa27x_dma_pdata = { 324 .dma_channels = 32, 325 .nb_requestors = 75, 326 .slave_map = pxa27x_slave_map, 327 .slave_map_cnt = ARRAY_SIZE(pxa27x_slave_map), 328 }; 329 330 static int __init pxa27x_init(void) 331 { 332 int ret = 0; 333 334 if (cpu_is_pxa27x()) { 335 336 pxa_register_wdt(RCSR); 337 338 pxa27x_init_pm(); 339 340 register_syscore_ops(&pxa_irq_syscore_ops); 341 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 342 343 if (!of_have_populated_dt()) { 344 pxa_register_device(&pxa27x_device_gpio, 345 &pxa27x_gpio_info); 346 pxa2xx_set_dmac_info(&pxa27x_dma_pdata); 347 ret = platform_add_devices(devices, 348 ARRAY_SIZE(devices)); 349 } 350 } 351 352 return ret; 353 } 354 355 postcore_initcall(pxa27x_init); 356