1*e6acc406SArnd Bergmann /* SPDX-License-Identifier: GPL-2.0-only */ 2*e6acc406SArnd Bergmann /* 3*e6acc406SArnd Bergmann * arch/arm/mach-pxa/include/mach/irqs.h 4*e6acc406SArnd Bergmann * 5*e6acc406SArnd Bergmann * Author: Nicolas Pitre 6*e6acc406SArnd Bergmann * Created: Jun 15, 2001 7*e6acc406SArnd Bergmann * Copyright: MontaVista Software Inc. 8*e6acc406SArnd Bergmann */ 9*e6acc406SArnd Bergmann #ifndef __ASM_MACH_IRQS_H 10*e6acc406SArnd Bergmann #define __ASM_MACH_IRQS_H 11*e6acc406SArnd Bergmann 12*e6acc406SArnd Bergmann #include <asm/irq.h> 13*e6acc406SArnd Bergmann 14*e6acc406SArnd Bergmann #define PXA_ISA_IRQ(x) (x) 15*e6acc406SArnd Bergmann #define PXA_IRQ(x) (NR_IRQS_LEGACY + (x)) 16*e6acc406SArnd Bergmann 17*e6acc406SArnd Bergmann #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ 18*e6acc406SArnd Bergmann #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ 19*e6acc406SArnd Bergmann #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ 20*e6acc406SArnd Bergmann #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ 21*e6acc406SArnd Bergmann #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ 22*e6acc406SArnd Bergmann #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ 23*e6acc406SArnd Bergmann #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ 24*e6acc406SArnd Bergmann #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ 25*e6acc406SArnd Bergmann #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ 26*e6acc406SArnd Bergmann #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ 27*e6acc406SArnd Bergmann #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ 28*e6acc406SArnd Bergmann #define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ 29*e6acc406SArnd Bergmann #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ 30*e6acc406SArnd Bergmann #define IRQ_USB PXA_IRQ(11) /* USB Service */ 31*e6acc406SArnd Bergmann #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ 32*e6acc406SArnd Bergmann #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ 33*e6acc406SArnd Bergmann #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ 34*e6acc406SArnd Bergmann #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ 35*e6acc406SArnd Bergmann #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ 36*e6acc406SArnd Bergmann #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ 37*e6acc406SArnd Bergmann #define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ 38*e6acc406SArnd Bergmann #define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ 39*e6acc406SArnd Bergmann #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ 40*e6acc406SArnd Bergmann #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ 41*e6acc406SArnd Bergmann #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ 42*e6acc406SArnd Bergmann #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ 43*e6acc406SArnd Bergmann #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ 44*e6acc406SArnd Bergmann #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ 45*e6acc406SArnd Bergmann #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ 46*e6acc406SArnd Bergmann #define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ 47*e6acc406SArnd Bergmann #define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ 48*e6acc406SArnd Bergmann #define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ 49*e6acc406SArnd Bergmann #define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ 50*e6acc406SArnd Bergmann #define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ 51*e6acc406SArnd Bergmann #define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ 52*e6acc406SArnd Bergmann #define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ 53*e6acc406SArnd Bergmann #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ 54*e6acc406SArnd Bergmann #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ 55*e6acc406SArnd Bergmann 56*e6acc406SArnd Bergmann #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ 57*e6acc406SArnd Bergmann #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ 58*e6acc406SArnd Bergmann #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ 59*e6acc406SArnd Bergmann #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ 60*e6acc406SArnd Bergmann #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ 61*e6acc406SArnd Bergmann #define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ 62*e6acc406SArnd Bergmann #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ 63*e6acc406SArnd Bergmann #define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ 64*e6acc406SArnd Bergmann #define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ 65*e6acc406SArnd Bergmann #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ 66*e6acc406SArnd Bergmann #define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ 67*e6acc406SArnd Bergmann #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ 68*e6acc406SArnd Bergmann #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ 69*e6acc406SArnd Bergmann #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ 70*e6acc406SArnd Bergmann #define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */ 71*e6acc406SArnd Bergmann #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ 72*e6acc406SArnd Bergmann #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ 73*e6acc406SArnd Bergmann #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ 74*e6acc406SArnd Bergmann 75*e6acc406SArnd Bergmann #define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ 76*e6acc406SArnd Bergmann #define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ 77*e6acc406SArnd Bergmann #define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ 78*e6acc406SArnd Bergmann #define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ 79*e6acc406SArnd Bergmann #define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ 80*e6acc406SArnd Bergmann #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ 81*e6acc406SArnd Bergmann 82*e6acc406SArnd Bergmann #define PXA_GPIO_IRQ_BASE PXA_IRQ(96) 83*e6acc406SArnd Bergmann #define PXA_NR_BUILTIN_GPIO (192) 84*e6acc406SArnd Bergmann #define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) 85*e6acc406SArnd Bergmann 86*e6acc406SArnd Bergmann /* 87*e6acc406SArnd Bergmann * The following interrupts are for board specific purposes. Since 88*e6acc406SArnd Bergmann * the kernel can only run on one machine at a time, we can re-use 89*e6acc406SArnd Bergmann * these. 90*e6acc406SArnd Bergmann * By default, no board IRQ is reserved. It should be finished in 91*e6acc406SArnd Bergmann * custom board since sparse IRQ is already enabled. 92*e6acc406SArnd Bergmann */ 93*e6acc406SArnd Bergmann #define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO) 94*e6acc406SArnd Bergmann 95*e6acc406SArnd Bergmann #define PXA_NR_IRQS (IRQ_BOARD_START) 96*e6acc406SArnd Bergmann 97*e6acc406SArnd Bergmann #ifndef __ASSEMBLY__ 98*e6acc406SArnd Bergmann struct irq_data; 99*e6acc406SArnd Bergmann struct pt_regs; 100*e6acc406SArnd Bergmann 101*e6acc406SArnd Bergmann void pxa_mask_irq(struct irq_data *); 102*e6acc406SArnd Bergmann void pxa_unmask_irq(struct irq_data *); 103*e6acc406SArnd Bergmann void icip_handle_irq(struct pt_regs *); 104*e6acc406SArnd Bergmann void ichp_handle_irq(struct pt_regs *); 105*e6acc406SArnd Bergmann 106*e6acc406SArnd Bergmann void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int)); 107*e6acc406SArnd Bergmann #endif 108*e6acc406SArnd Bergmann 109*e6acc406SArnd Bergmann #endif /* __ASM_MACH_IRQS_H */ 110