1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/sysdev.h> 19 20 #include <asm/hardware.h> 21 #include <asm/irq.h> 22 #include <asm/mach/irq.h> 23 #include <asm/arch/pxa-regs.h> 24 25 #include "generic.h" 26 27 28 /* 29 * This is for peripheral IRQs internal to the PXA chip. 30 */ 31 32 static void pxa_mask_low_irq(unsigned int irq) 33 { 34 ICMR &= ~(1 << irq); 35 } 36 37 static void pxa_unmask_low_irq(unsigned int irq) 38 { 39 ICMR |= (1 << irq); 40 } 41 42 static struct irq_chip pxa_internal_chip_low = { 43 .name = "SC", 44 .ack = pxa_mask_low_irq, 45 .mask = pxa_mask_low_irq, 46 .unmask = pxa_unmask_low_irq, 47 }; 48 49 void __init pxa_init_irq_low(void) 50 { 51 int irq; 52 53 /* disable all IRQs */ 54 ICMR = 0; 55 56 /* all IRQs are IRQ, not FIQ */ 57 ICLR = 0; 58 59 /* only unmasked interrupts kick us out of idle */ 60 ICCR = 1; 61 62 for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { 63 set_irq_chip(irq, &pxa_internal_chip_low); 64 set_irq_handler(irq, handle_level_irq); 65 set_irq_flags(irq, IRQF_VALID); 66 } 67 } 68 69 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 70 71 /* 72 * This is for the second set of internal IRQs as found on the PXA27x. 73 */ 74 75 static void pxa_mask_high_irq(unsigned int irq) 76 { 77 ICMR2 &= ~(1 << (irq - 32)); 78 } 79 80 static void pxa_unmask_high_irq(unsigned int irq) 81 { 82 ICMR2 |= (1 << (irq - 32)); 83 } 84 85 static struct irq_chip pxa_internal_chip_high = { 86 .name = "SC-hi", 87 .ack = pxa_mask_high_irq, 88 .mask = pxa_mask_high_irq, 89 .unmask = pxa_unmask_high_irq, 90 }; 91 92 void __init pxa_init_irq_high(void) 93 { 94 int irq; 95 96 ICMR2 = 0; 97 ICLR2 = 0; 98 99 for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { 100 set_irq_chip(irq, &pxa_internal_chip_high); 101 set_irq_handler(irq, handle_level_irq); 102 set_irq_flags(irq, IRQF_VALID); 103 } 104 } 105 #endif 106 107 /* 108 * PXA GPIO edge detection for IRQs: 109 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 110 * Use this instead of directly setting GRER/GFER. 111 */ 112 113 static long GPIO_IRQ_rising_edge[4]; 114 static long GPIO_IRQ_falling_edge[4]; 115 static long GPIO_IRQ_mask[4]; 116 117 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 118 { 119 int gpio, idx; 120 121 gpio = IRQ_TO_GPIO(irq); 122 idx = gpio >> 5; 123 124 if (type == IRQ_TYPE_PROBE) { 125 /* Don't mess with enabled GPIOs using preconfigured edges or 126 * GPIOs set to alternate function or to output during probe 127 */ 128 if ((GPIO_IRQ_rising_edge[idx] | 129 GPIO_IRQ_falling_edge[idx] | 130 GPDR(gpio)) & GPIO_bit(gpio)) 131 return 0; 132 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) 133 return 0; 134 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 135 } 136 137 pxa_gpio_mode(gpio | GPIO_IN); 138 139 if (type & IRQ_TYPE_EDGE_RISING) 140 __set_bit(gpio, GPIO_IRQ_rising_edge); 141 else 142 __clear_bit(gpio, GPIO_IRQ_rising_edge); 143 144 if (type & IRQ_TYPE_EDGE_FALLING) 145 __set_bit(gpio, GPIO_IRQ_falling_edge); 146 else 147 __clear_bit(gpio, GPIO_IRQ_falling_edge); 148 149 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 150 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 151 152 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, 153 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 154 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 155 return 0; 156 } 157 158 /* 159 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. 160 */ 161 162 static void pxa_ack_low_gpio(unsigned int irq) 163 { 164 GEDR0 = (1 << (irq - IRQ_GPIO0)); 165 } 166 167 static void pxa_mask_low_gpio(unsigned int irq) 168 { 169 ICMR &= ~(1 << (irq - PXA_IRQ(0))); 170 } 171 172 static void pxa_unmask_low_gpio(unsigned int irq) 173 { 174 ICMR |= 1 << (irq - PXA_IRQ(0)); 175 } 176 177 static struct irq_chip pxa_low_gpio_chip = { 178 .name = "GPIO-l", 179 .ack = pxa_ack_low_gpio, 180 .mask = pxa_mask_low_gpio, 181 .unmask = pxa_unmask_low_gpio, 182 .set_type = pxa_gpio_irq_type, 183 }; 184 185 /* 186 * Demux handler for GPIO>=2 edge detect interrupts 187 */ 188 189 #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) 190 191 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 192 { 193 int loop, bit, n; 194 unsigned long gedr[4]; 195 196 do { 197 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; 198 gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; 199 gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; 200 gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; 201 202 GEDR0 = gedr[0]; GEDR1 = gedr[1]; 203 GEDR2 = gedr[2]; GEDR3 = gedr[3]; 204 205 loop = 0; 206 bit = find_first_bit(gedr, GEDR_BITS); 207 while (bit < GEDR_BITS) { 208 loop = 1; 209 210 n = PXA_GPIO_IRQ_BASE + bit; 211 desc_handle_irq(n, irq_desc + n); 212 213 bit = find_next_bit(gedr, GEDR_BITS, bit + 1); 214 } 215 } while (loop); 216 } 217 218 static void pxa_ack_muxed_gpio(unsigned int irq) 219 { 220 int gpio = irq - IRQ_GPIO(2) + 2; 221 GEDR(gpio) = GPIO_bit(gpio); 222 } 223 224 static void pxa_mask_muxed_gpio(unsigned int irq) 225 { 226 int gpio = irq - IRQ_GPIO(2) + 2; 227 __clear_bit(gpio, GPIO_IRQ_mask); 228 GRER(gpio) &= ~GPIO_bit(gpio); 229 GFER(gpio) &= ~GPIO_bit(gpio); 230 } 231 232 static void pxa_unmask_muxed_gpio(unsigned int irq) 233 { 234 int gpio = irq - IRQ_GPIO(2) + 2; 235 int idx = gpio >> 5; 236 __set_bit(gpio, GPIO_IRQ_mask); 237 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 238 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 239 } 240 241 static struct irq_chip pxa_muxed_gpio_chip = { 242 .name = "GPIO", 243 .ack = pxa_ack_muxed_gpio, 244 .mask = pxa_mask_muxed_gpio, 245 .unmask = pxa_unmask_muxed_gpio, 246 .set_type = pxa_gpio_irq_type, 247 }; 248 249 void __init pxa_init_irq_gpio(int gpio_nr) 250 { 251 int irq, i; 252 253 pxa_last_gpio = gpio_nr - 1; 254 255 /* clear all GPIO edge detects */ 256 for (i = 0; i < gpio_nr; i += 32) { 257 GFER(i) = 0; 258 GRER(i) = 0; 259 GEDR(i) = GEDR(i); 260 } 261 262 /* GPIO 0 and 1 must have their mask bit always set */ 263 GPIO_IRQ_mask[0] = 3; 264 265 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 266 set_irq_chip(irq, &pxa_low_gpio_chip); 267 set_irq_handler(irq, handle_edge_irq); 268 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 269 } 270 271 for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { 272 set_irq_chip(irq, &pxa_muxed_gpio_chip); 273 set_irq_handler(irq, handle_edge_irq); 274 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 275 } 276 277 /* Install handler for GPIO>=2 edge detect interrupts */ 278 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 279 280 pxa_init_gpio(gpio_nr); 281 } 282 283 void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int)) 284 { 285 pxa_low_gpio_chip.set_wake = set_wake; 286 pxa_muxed_gpio_chip.set_wake = set_wake; 287 } 288 289 void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) 290 { 291 pxa_internal_chip_low.set_wake = set_wake; 292 #ifdef CONFIG_PXA27x 293 pxa_internal_chip_high.set_wake = set_wake; 294 #endif 295 pxa_init_gpio_set_wake(set_wake); 296 } 297 298 #ifdef CONFIG_PM 299 static unsigned long saved_icmr[2]; 300 301 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) 302 { 303 switch (dev->id) { 304 case 0: 305 saved_icmr[0] = ICMR; 306 ICMR = 0; 307 break; 308 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 309 case 1: 310 saved_icmr[1] = ICMR2; 311 ICMR2 = 0; 312 break; 313 #endif 314 default: 315 return -EINVAL; 316 } 317 318 return 0; 319 } 320 321 static int pxa_irq_resume(struct sys_device *dev) 322 { 323 switch (dev->id) { 324 case 0: 325 ICMR = saved_icmr[0]; 326 ICLR = 0; 327 ICCR = 1; 328 break; 329 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 330 case 1: 331 ICMR2 = saved_icmr[1]; 332 ICLR2 = 0; 333 break; 334 #endif 335 default: 336 return -EINVAL; 337 } 338 339 return 0; 340 } 341 #else 342 #define pxa_irq_suspend NULL 343 #define pxa_irq_resume NULL 344 #endif 345 346 struct sysdev_class pxa_irq_sysclass = { 347 .name = "irq", 348 .suspend = pxa_irq_suspend, 349 .resume = pxa_irq_resume, 350 }; 351 352 static int __init pxa_irq_init(void) 353 { 354 return sysdev_class_register(&pxa_irq_sysclass); 355 } 356 357 core_initcall(pxa_irq_init); 358