1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 19 #include <asm/hardware.h> 20 #include <asm/irq.h> 21 #include <asm/mach/irq.h> 22 #include <asm/arch/pxa-regs.h> 23 24 #include "generic.h" 25 26 27 /* 28 * This is for peripheral IRQs internal to the PXA chip. 29 */ 30 31 static void pxa_mask_low_irq(unsigned int irq) 32 { 33 ICMR &= ~(1 << irq); 34 } 35 36 static void pxa_unmask_low_irq(unsigned int irq) 37 { 38 ICMR |= (1 << irq); 39 } 40 41 static struct irq_chip pxa_internal_chip_low = { 42 .name = "SC", 43 .ack = pxa_mask_low_irq, 44 .mask = pxa_mask_low_irq, 45 .unmask = pxa_unmask_low_irq, 46 }; 47 48 void __init pxa_init_irq_low(void) 49 { 50 int irq; 51 52 /* disable all IRQs */ 53 ICMR = 0; 54 55 /* all IRQs are IRQ, not FIQ */ 56 ICLR = 0; 57 58 /* only unmasked interrupts kick us out of idle */ 59 ICCR = 1; 60 61 for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { 62 set_irq_chip(irq, &pxa_internal_chip_low); 63 set_irq_handler(irq, handle_level_irq); 64 set_irq_flags(irq, IRQF_VALID); 65 } 66 } 67 68 #ifdef CONFIG_PXA27x 69 70 /* 71 * This is for the second set of internal IRQs as found on the PXA27x. 72 */ 73 74 static void pxa_mask_high_irq(unsigned int irq) 75 { 76 ICMR2 &= ~(1 << (irq - 32)); 77 } 78 79 static void pxa_unmask_high_irq(unsigned int irq) 80 { 81 ICMR2 |= (1 << (irq - 32)); 82 } 83 84 static struct irq_chip pxa_internal_chip_high = { 85 .name = "SC-hi", 86 .ack = pxa_mask_high_irq, 87 .mask = pxa_mask_high_irq, 88 .unmask = pxa_unmask_high_irq, 89 }; 90 91 void __init pxa_init_irq_high(void) 92 { 93 int irq; 94 95 ICMR2 = 0; 96 ICLR2 = 0; 97 98 for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { 99 set_irq_chip(irq, &pxa_internal_chip_high); 100 set_irq_handler(irq, handle_level_irq); 101 set_irq_flags(irq, IRQF_VALID); 102 } 103 } 104 #endif 105 106 /* 107 * PXA GPIO edge detection for IRQs: 108 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 109 * Use this instead of directly setting GRER/GFER. 110 */ 111 112 static long GPIO_IRQ_rising_edge[4]; 113 static long GPIO_IRQ_falling_edge[4]; 114 static long GPIO_IRQ_mask[4]; 115 116 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 117 { 118 int gpio, idx; 119 120 gpio = IRQ_TO_GPIO(irq); 121 idx = gpio >> 5; 122 123 if (type == IRQT_PROBE) { 124 /* Don't mess with enabled GPIOs using preconfigured edges or 125 GPIOs set to alternate function or to output during probe */ 126 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & 127 GPIO_bit(gpio)) 128 return 0; 129 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) 130 return 0; 131 type = __IRQT_RISEDGE | __IRQT_FALEDGE; 132 } 133 134 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ 135 136 pxa_gpio_mode(gpio | GPIO_IN); 137 138 if (type & __IRQT_RISEDGE) { 139 /* printk("rising "); */ 140 __set_bit (gpio, GPIO_IRQ_rising_edge); 141 } else { 142 __clear_bit (gpio, GPIO_IRQ_rising_edge); 143 } 144 145 if (type & __IRQT_FALEDGE) { 146 /* printk("falling "); */ 147 __set_bit (gpio, GPIO_IRQ_falling_edge); 148 } else { 149 __clear_bit (gpio, GPIO_IRQ_falling_edge); 150 } 151 152 /* printk("edges\n"); */ 153 154 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 155 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 156 return 0; 157 } 158 159 /* 160 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. 161 */ 162 163 static void pxa_ack_low_gpio(unsigned int irq) 164 { 165 GEDR0 = (1 << (irq - IRQ_GPIO0)); 166 } 167 168 static struct irq_chip pxa_low_gpio_chip = { 169 .name = "GPIO-l", 170 .ack = pxa_ack_low_gpio, 171 .mask = pxa_mask_low_irq, 172 .unmask = pxa_unmask_low_irq, 173 .set_type = pxa_gpio_irq_type, 174 }; 175 176 /* 177 * Demux handler for GPIO>=2 edge detect interrupts 178 */ 179 180 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 181 { 182 unsigned int mask; 183 int loop; 184 185 do { 186 loop = 0; 187 188 mask = GEDR0 & GPIO_IRQ_mask[0] & ~3; 189 if (mask) { 190 GEDR0 = mask; 191 irq = IRQ_GPIO(2); 192 desc = irq_desc + irq; 193 mask >>= 2; 194 do { 195 if (mask & 1) 196 desc_handle_irq(irq, desc); 197 irq++; 198 desc++; 199 mask >>= 1; 200 } while (mask); 201 loop = 1; 202 } 203 204 mask = GEDR1 & GPIO_IRQ_mask[1]; 205 if (mask) { 206 GEDR1 = mask; 207 irq = IRQ_GPIO(32); 208 desc = irq_desc + irq; 209 do { 210 if (mask & 1) 211 desc_handle_irq(irq, desc); 212 irq++; 213 desc++; 214 mask >>= 1; 215 } while (mask); 216 loop = 1; 217 } 218 219 mask = GEDR2 & GPIO_IRQ_mask[2]; 220 if (mask) { 221 GEDR2 = mask; 222 irq = IRQ_GPIO(64); 223 desc = irq_desc + irq; 224 do { 225 if (mask & 1) 226 desc_handle_irq(irq, desc); 227 irq++; 228 desc++; 229 mask >>= 1; 230 } while (mask); 231 loop = 1; 232 } 233 234 mask = GEDR3 & GPIO_IRQ_mask[3]; 235 if (mask) { 236 GEDR3 = mask; 237 irq = IRQ_GPIO(96); 238 desc = irq_desc + irq; 239 do { 240 if (mask & 1) 241 desc_handle_irq(irq, desc); 242 irq++; 243 desc++; 244 mask >>= 1; 245 } while (mask); 246 loop = 1; 247 } 248 } while (loop); 249 } 250 251 static void pxa_ack_muxed_gpio(unsigned int irq) 252 { 253 int gpio = irq - IRQ_GPIO(2) + 2; 254 GEDR(gpio) = GPIO_bit(gpio); 255 } 256 257 static void pxa_mask_muxed_gpio(unsigned int irq) 258 { 259 int gpio = irq - IRQ_GPIO(2) + 2; 260 __clear_bit(gpio, GPIO_IRQ_mask); 261 GRER(gpio) &= ~GPIO_bit(gpio); 262 GFER(gpio) &= ~GPIO_bit(gpio); 263 } 264 265 static void pxa_unmask_muxed_gpio(unsigned int irq) 266 { 267 int gpio = irq - IRQ_GPIO(2) + 2; 268 int idx = gpio >> 5; 269 __set_bit(gpio, GPIO_IRQ_mask); 270 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 271 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 272 } 273 274 static struct irq_chip pxa_muxed_gpio_chip = { 275 .name = "GPIO", 276 .ack = pxa_ack_muxed_gpio, 277 .mask = pxa_mask_muxed_gpio, 278 .unmask = pxa_unmask_muxed_gpio, 279 .set_type = pxa_gpio_irq_type, 280 }; 281 282 void __init pxa_init_irq_gpio(int gpio_nr) 283 { 284 int irq, i; 285 286 pxa_last_gpio = gpio_nr - 1; 287 288 /* clear all GPIO edge detects */ 289 for (i = 0; i < gpio_nr; i += 32) { 290 GFER(i) = 0; 291 GRER(i) = 0; 292 GEDR(i) = GEDR(i); 293 } 294 295 /* GPIO 0 and 1 must have their mask bit always set */ 296 GPIO_IRQ_mask[0] = 3; 297 298 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 299 set_irq_chip(irq, &pxa_low_gpio_chip); 300 set_irq_handler(irq, handle_edge_irq); 301 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 302 } 303 304 for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { 305 set_irq_chip(irq, &pxa_muxed_gpio_chip); 306 set_irq_handler(irq, handle_edge_irq); 307 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 308 } 309 310 /* Install handler for GPIO>=2 edge detect interrupts */ 311 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 312 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 313 } 314 315 void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) 316 { 317 pxa_internal_chip_low.set_wake = set_wake; 318 #ifdef CONFIG_PXA27x 319 pxa_internal_chip_high.set_wake = set_wake; 320 #endif 321 pxa_low_gpio_chip.set_wake = set_wake; 322 pxa_muxed_gpio_chip.set_wake = set_wake; 323 } 324