1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 19 #include <asm/hardware.h> 20 #include <asm/irq.h> 21 #include <asm/mach/irq.h> 22 #include <asm/arch/pxa-regs.h> 23 24 #include "generic.h" 25 26 27 /* 28 * This is for peripheral IRQs internal to the PXA chip. 29 */ 30 31 static void pxa_mask_low_irq(unsigned int irq) 32 { 33 ICMR &= ~(1 << irq); 34 } 35 36 static void pxa_unmask_low_irq(unsigned int irq) 37 { 38 ICMR |= (1 << irq); 39 } 40 41 static int pxa_set_wake(unsigned int irq, unsigned int on) 42 { 43 u32 mask; 44 45 switch (irq) { 46 case IRQ_RTCAlrm: 47 mask = PWER_RTC; 48 break; 49 #ifdef CONFIG_PXA27x 50 /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */ 51 #endif 52 default: 53 return -EINVAL; 54 } 55 if (on) 56 PWER |= mask; 57 else 58 PWER &= ~mask; 59 return 0; 60 } 61 62 static struct irq_chip pxa_internal_chip_low = { 63 .name = "SC", 64 .ack = pxa_mask_low_irq, 65 .mask = pxa_mask_low_irq, 66 .unmask = pxa_unmask_low_irq, 67 .set_wake = pxa_set_wake, 68 }; 69 70 #ifdef CONFIG_PXA27x 71 72 /* 73 * This is for the second set of internal IRQs as found on the PXA27x. 74 */ 75 76 static void pxa_mask_high_irq(unsigned int irq) 77 { 78 ICMR2 &= ~(1 << (irq - 32)); 79 } 80 81 static void pxa_unmask_high_irq(unsigned int irq) 82 { 83 ICMR2 |= (1 << (irq - 32)); 84 } 85 86 static struct irq_chip pxa_internal_chip_high = { 87 .name = "SC-hi", 88 .ack = pxa_mask_high_irq, 89 .mask = pxa_mask_high_irq, 90 .unmask = pxa_unmask_high_irq, 91 }; 92 93 void __init pxa_init_irq_high(void) 94 { 95 int irq; 96 97 ICMR2 = 0; 98 ICLR2 = 0; 99 100 for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { 101 set_irq_chip(irq, &pxa_internal_chip_high); 102 set_irq_handler(irq, handle_level_irq); 103 set_irq_flags(irq, IRQF_VALID); 104 } 105 } 106 #endif 107 108 /* Note that if an input/irq line ever gets changed to an output during 109 * suspend, the relevant PWER, PRER, and PFER bits should be cleared. 110 */ 111 #ifdef CONFIG_PXA27x 112 113 /* PXA27x: Various gpios can issue wakeup events. This logic only 114 * handles the simple cases, not the WEMUX2 and WEMUX3 options 115 */ 116 #define PXA27x_GPIO_NOWAKE_MASK \ 117 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) 118 #define WAKEMASK(gpio) \ 119 (((gpio) <= 15) \ 120 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ 121 : ((gpio == 35) ? (1 << 24) : 0)) 122 #else 123 124 /* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */ 125 #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0) 126 #endif 127 128 /* 129 * PXA GPIO edge detection for IRQs: 130 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 131 * Use this instead of directly setting GRER/GFER. 132 */ 133 134 static long GPIO_IRQ_rising_edge[4]; 135 static long GPIO_IRQ_falling_edge[4]; 136 static long GPIO_IRQ_mask[4]; 137 138 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 139 { 140 int gpio, idx; 141 u32 mask; 142 143 gpio = IRQ_TO_GPIO(irq); 144 idx = gpio >> 5; 145 mask = WAKEMASK(gpio); 146 147 if (type == IRQT_PROBE) { 148 /* Don't mess with enabled GPIOs using preconfigured edges or 149 GPIOs set to alternate function or to output during probe */ 150 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & 151 GPIO_bit(gpio)) 152 return 0; 153 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) 154 return 0; 155 type = __IRQT_RISEDGE | __IRQT_FALEDGE; 156 } 157 158 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ 159 160 pxa_gpio_mode(gpio | GPIO_IN); 161 162 if (type & __IRQT_RISEDGE) { 163 /* printk("rising "); */ 164 __set_bit (gpio, GPIO_IRQ_rising_edge); 165 PRER |= mask; 166 } else { 167 __clear_bit (gpio, GPIO_IRQ_rising_edge); 168 PRER &= ~mask; 169 } 170 171 if (type & __IRQT_FALEDGE) { 172 /* printk("falling "); */ 173 __set_bit (gpio, GPIO_IRQ_falling_edge); 174 PFER |= mask; 175 } else { 176 __clear_bit (gpio, GPIO_IRQ_falling_edge); 177 PFER &= ~mask; 178 } 179 180 /* printk("edges\n"); */ 181 182 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 183 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 184 return 0; 185 } 186 187 /* 188 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. 189 */ 190 191 static void pxa_ack_low_gpio(unsigned int irq) 192 { 193 GEDR0 = (1 << (irq - IRQ_GPIO0)); 194 } 195 196 static int pxa_set_gpio_wake(unsigned int irq, unsigned int on) 197 { 198 int gpio = IRQ_TO_GPIO(irq); 199 u32 mask = WAKEMASK(gpio); 200 201 if (!mask) 202 return -EINVAL; 203 204 if (on) 205 PWER |= mask; 206 else 207 PWER &= ~mask; 208 return 0; 209 } 210 211 212 static struct irq_chip pxa_low_gpio_chip = { 213 .name = "GPIO-l", 214 .ack = pxa_ack_low_gpio, 215 .mask = pxa_mask_low_irq, 216 .unmask = pxa_unmask_low_irq, 217 .set_type = pxa_gpio_irq_type, 218 .set_wake = pxa_set_gpio_wake, 219 }; 220 221 /* 222 * Demux handler for GPIO>=2 edge detect interrupts 223 */ 224 225 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 226 { 227 unsigned int mask; 228 int loop; 229 230 do { 231 loop = 0; 232 233 mask = GEDR0 & ~3; 234 if (mask) { 235 GEDR0 = mask; 236 irq = IRQ_GPIO(2); 237 desc = irq_desc + irq; 238 mask >>= 2; 239 do { 240 if (mask & 1) 241 desc_handle_irq(irq, desc); 242 irq++; 243 desc++; 244 mask >>= 1; 245 } while (mask); 246 loop = 1; 247 } 248 249 mask = GEDR1; 250 if (mask) { 251 GEDR1 = mask; 252 irq = IRQ_GPIO(32); 253 desc = irq_desc + irq; 254 do { 255 if (mask & 1) 256 desc_handle_irq(irq, desc); 257 irq++; 258 desc++; 259 mask >>= 1; 260 } while (mask); 261 loop = 1; 262 } 263 264 mask = GEDR2; 265 if (mask) { 266 GEDR2 = mask; 267 irq = IRQ_GPIO(64); 268 desc = irq_desc + irq; 269 do { 270 if (mask & 1) 271 desc_handle_irq(irq, desc); 272 irq++; 273 desc++; 274 mask >>= 1; 275 } while (mask); 276 loop = 1; 277 } 278 279 #if PXA_LAST_GPIO >= 96 280 mask = GEDR3; 281 if (mask) { 282 GEDR3 = mask; 283 irq = IRQ_GPIO(96); 284 desc = irq_desc + irq; 285 do { 286 if (mask & 1) 287 desc_handle_irq(irq, desc); 288 irq++; 289 desc++; 290 mask >>= 1; 291 } while (mask); 292 loop = 1; 293 } 294 #endif 295 } while (loop); 296 } 297 298 static void pxa_ack_muxed_gpio(unsigned int irq) 299 { 300 int gpio = irq - IRQ_GPIO(2) + 2; 301 GEDR(gpio) = GPIO_bit(gpio); 302 } 303 304 static void pxa_mask_muxed_gpio(unsigned int irq) 305 { 306 int gpio = irq - IRQ_GPIO(2) + 2; 307 __clear_bit(gpio, GPIO_IRQ_mask); 308 GRER(gpio) &= ~GPIO_bit(gpio); 309 GFER(gpio) &= ~GPIO_bit(gpio); 310 } 311 312 static void pxa_unmask_muxed_gpio(unsigned int irq) 313 { 314 int gpio = irq - IRQ_GPIO(2) + 2; 315 int idx = gpio >> 5; 316 __set_bit(gpio, GPIO_IRQ_mask); 317 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 318 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 319 } 320 321 static struct irq_chip pxa_muxed_gpio_chip = { 322 .name = "GPIO", 323 .ack = pxa_ack_muxed_gpio, 324 .mask = pxa_mask_muxed_gpio, 325 .unmask = pxa_unmask_muxed_gpio, 326 .set_type = pxa_gpio_irq_type, 327 .set_wake = pxa_set_gpio_wake, 328 }; 329 330 void __init pxa_init_irq(void) 331 { 332 int irq; 333 334 /* disable all IRQs */ 335 ICMR = 0; 336 337 /* all IRQs are IRQ, not FIQ */ 338 ICLR = 0; 339 340 /* clear all GPIO edge detects */ 341 GFER0 = 0; 342 GFER1 = 0; 343 GFER2 = 0; 344 GRER0 = 0; 345 GRER1 = 0; 346 GRER2 = 0; 347 GEDR0 = GEDR0; 348 GEDR1 = GEDR1; 349 GEDR2 = GEDR2; 350 351 #ifdef CONFIG_PXA27x 352 /* And similarly for the extra regs on the PXA27x */ 353 GFER3 = 0; 354 GRER3 = 0; 355 GEDR3 = GEDR3; 356 #endif 357 358 /* only unmasked interrupts kick us out of idle */ 359 ICCR = 1; 360 361 /* GPIO 0 and 1 must have their mask bit always set */ 362 GPIO_IRQ_mask[0] = 3; 363 364 for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { 365 set_irq_chip(irq, &pxa_internal_chip_low); 366 set_irq_handler(irq, handle_level_irq); 367 set_irq_flags(irq, IRQF_VALID); 368 } 369 370 #ifdef CONFIG_PXA27x 371 pxa_init_irq_high(); 372 #endif 373 374 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 375 set_irq_chip(irq, &pxa_low_gpio_chip); 376 set_irq_handler(irq, handle_edge_irq); 377 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 378 } 379 380 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { 381 set_irq_chip(irq, &pxa_muxed_gpio_chip); 382 set_irq_handler(irq, handle_edge_irq); 383 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 384 } 385 386 /* Install handler for GPIO>=2 edge detect interrupts */ 387 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 388 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 389 } 390