1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/sysdev.h> 19 20 #include <mach/hardware.h> 21 #include <asm/irq.h> 22 #include <asm/mach/irq.h> 23 #include <mach/gpio.h> 24 #include <mach/regs-intc.h> 25 26 #include "generic.h" 27 28 #define MAX_INTERNAL_IRQS 128 29 30 #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 31 #define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR)) 32 #define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR)) 33 34 /* 35 * This is for peripheral IRQs internal to the PXA chip. 36 */ 37 38 static int pxa_internal_irq_nr; 39 40 static inline int cpu_has_ipr(void) 41 { 42 return !cpu_is_pxa25x(); 43 } 44 45 static void pxa_mask_irq(unsigned int irq) 46 { 47 _ICMR(irq) &= ~(1 << IRQ_BIT(irq)); 48 } 49 50 static void pxa_unmask_irq(unsigned int irq) 51 { 52 _ICMR(irq) |= 1 << IRQ_BIT(irq); 53 } 54 55 static struct irq_chip pxa_internal_irq_chip = { 56 .name = "SC", 57 .ack = pxa_mask_irq, 58 .mask = pxa_mask_irq, 59 .unmask = pxa_unmask_irq, 60 }; 61 62 /* 63 * GPIO IRQs for GPIO 0 and 1 64 */ 65 static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type) 66 { 67 int gpio = irq - IRQ_GPIO0; 68 69 if (__gpio_is_occupied(gpio)) { 70 pr_err("%s failed: GPIO is configured\n", __func__); 71 return -EINVAL; 72 } 73 74 if (type & IRQ_TYPE_EDGE_RISING) 75 GRER0 |= GPIO_bit(gpio); 76 else 77 GRER0 &= ~GPIO_bit(gpio); 78 79 if (type & IRQ_TYPE_EDGE_FALLING) 80 GFER0 |= GPIO_bit(gpio); 81 else 82 GFER0 &= ~GPIO_bit(gpio); 83 84 return 0; 85 } 86 87 static void pxa_ack_low_gpio(unsigned int irq) 88 { 89 GEDR0 = (1 << (irq - IRQ_GPIO0)); 90 } 91 92 static void pxa_mask_low_gpio(unsigned int irq) 93 { 94 ICMR &= ~(1 << (irq - PXA_IRQ(0))); 95 } 96 97 static void pxa_unmask_low_gpio(unsigned int irq) 98 { 99 ICMR |= 1 << (irq - PXA_IRQ(0)); 100 } 101 102 static struct irq_chip pxa_low_gpio_chip = { 103 .name = "GPIO-l", 104 .ack = pxa_ack_low_gpio, 105 .mask = pxa_mask_low_gpio, 106 .unmask = pxa_unmask_low_gpio, 107 .set_type = pxa_set_low_gpio_type, 108 }; 109 110 static void __init pxa_init_low_gpio_irq(set_wake_t fn) 111 { 112 int irq; 113 114 /* clear edge detection on GPIO 0 and 1 */ 115 GFER0 &= ~0x3; 116 GRER0 &= ~0x3; 117 GEDR0 = 0x3; 118 119 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 120 set_irq_chip(irq, &pxa_low_gpio_chip); 121 set_irq_handler(irq, handle_edge_irq); 122 set_irq_flags(irq, IRQF_VALID); 123 } 124 125 pxa_low_gpio_chip.set_wake = fn; 126 } 127 128 void __init pxa_init_irq(int irq_nr, set_wake_t fn) 129 { 130 int irq, i; 131 132 BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 133 134 pxa_internal_irq_nr = irq_nr; 135 136 for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) { 137 _ICMR(irq) = 0; /* disable all IRQs */ 138 _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ 139 } 140 141 /* initialize interrupt priority */ 142 if (cpu_has_ipr()) { 143 for (i = 0; i < irq_nr; i++) 144 IPR(i) = i | (1 << 31); 145 } 146 147 /* only unmasked interrupts kick us out of idle */ 148 ICCR = 1; 149 150 for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { 151 set_irq_chip(irq, &pxa_internal_irq_chip); 152 set_irq_handler(irq, handle_level_irq); 153 set_irq_flags(irq, IRQF_VALID); 154 } 155 156 pxa_internal_irq_chip.set_wake = fn; 157 pxa_init_low_gpio_irq(fn); 158 } 159 160 #ifdef CONFIG_PM 161 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 162 static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 163 164 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) 165 { 166 int i, irq = PXA_IRQ(0); 167 168 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { 169 saved_icmr[i] = _ICMR(irq); 170 _ICMR(irq) = 0; 171 } 172 173 if (cpu_has_ipr()) { 174 for (i = 0; i < pxa_internal_irq_nr; i++) 175 saved_ipr[i] = IPR(i); 176 } 177 178 return 0; 179 } 180 181 static int pxa_irq_resume(struct sys_device *dev) 182 { 183 int i, irq = PXA_IRQ(0); 184 185 if (cpu_has_ipr()) { 186 for (i = 0; i < pxa_internal_irq_nr; i++) 187 IPR(i) = saved_ipr[i]; 188 } 189 190 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { 191 _ICMR(irq) = saved_icmr[i]; 192 _ICLR(irq) = 0; 193 } 194 195 ICCR = 1; 196 return 0; 197 } 198 #else 199 #define pxa_irq_suspend NULL 200 #define pxa_irq_resume NULL 201 #endif 202 203 struct sysdev_class pxa_irq_sysclass = { 204 .name = "irq", 205 .suspend = pxa_irq_suspend, 206 .resume = pxa_irq_resume, 207 }; 208 209 static int __init pxa_irq_init(void) 210 { 211 return sysdev_class_register(&pxa_irq_sysclass); 212 } 213 214 core_initcall(pxa_irq_init); 215