1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 22 #include <mach/hardware.h> 23 #include <mach/irqs.h> 24 #include <mach/gpio.h> 25 26 #include "generic.h" 27 28 #define IRQ_BASE io_p2v(0x40d00000) 29 30 #define ICIP (0x000) 31 #define ICMR (0x004) 32 #define ICLR (0x008) 33 #define ICFR (0x00c) 34 #define ICPR (0x010) 35 #define ICCR (0x014) 36 #define ICHP (0x018) 37 #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 38 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 39 (0x144 + (((i) - 64) << 2))) 40 #define ICHP_VAL_IRQ (1 << 31) 41 #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 42 #define IPR_VALID (1 << 31) 43 #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 44 45 #define MAX_INTERNAL_IRQS 128 46 47 /* 48 * This is for peripheral IRQs internal to the PXA chip. 49 */ 50 51 static int pxa_internal_irq_nr; 52 53 static inline int cpu_has_ipr(void) 54 { 55 return !cpu_is_pxa25x(); 56 } 57 58 static inline void __iomem *irq_base(int i) 59 { 60 static unsigned long phys_base[] = { 61 0x40d00000, 62 0x40d0009c, 63 0x40d00130, 64 }; 65 66 return io_p2v(phys_base[i]); 67 } 68 69 void pxa_mask_irq(struct irq_data *d) 70 { 71 void __iomem *base = irq_data_get_irq_chip_data(d); 72 uint32_t icmr = __raw_readl(base + ICMR); 73 74 icmr &= ~(1 << IRQ_BIT(d->irq)); 75 __raw_writel(icmr, base + ICMR); 76 } 77 78 void pxa_unmask_irq(struct irq_data *d) 79 { 80 void __iomem *base = irq_data_get_irq_chip_data(d); 81 uint32_t icmr = __raw_readl(base + ICMR); 82 83 icmr |= 1 << IRQ_BIT(d->irq); 84 __raw_writel(icmr, base + ICMR); 85 } 86 87 static struct irq_chip pxa_internal_irq_chip = { 88 .name = "SC", 89 .irq_ack = pxa_mask_irq, 90 .irq_mask = pxa_mask_irq, 91 .irq_unmask = pxa_unmask_irq, 92 }; 93 94 /* 95 * GPIO IRQs for GPIO 0 and 1 96 */ 97 static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) 98 { 99 int gpio = d->irq - IRQ_GPIO0; 100 101 if (__gpio_is_occupied(gpio)) { 102 pr_err("%s failed: GPIO is configured\n", __func__); 103 return -EINVAL; 104 } 105 106 if (type & IRQ_TYPE_EDGE_RISING) 107 GRER0 |= GPIO_bit(gpio); 108 else 109 GRER0 &= ~GPIO_bit(gpio); 110 111 if (type & IRQ_TYPE_EDGE_FALLING) 112 GFER0 |= GPIO_bit(gpio); 113 else 114 GFER0 &= ~GPIO_bit(gpio); 115 116 return 0; 117 } 118 119 static void pxa_ack_low_gpio(struct irq_data *d) 120 { 121 GEDR0 = (1 << (d->irq - IRQ_GPIO0)); 122 } 123 124 static struct irq_chip pxa_low_gpio_chip = { 125 .name = "GPIO-l", 126 .irq_ack = pxa_ack_low_gpio, 127 .irq_mask = pxa_mask_irq, 128 .irq_unmask = pxa_unmask_irq, 129 .irq_set_type = pxa_set_low_gpio_type, 130 }; 131 132 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 133 { 134 uint32_t icip, icmr, mask; 135 136 do { 137 icip = __raw_readl(IRQ_BASE + ICIP); 138 icmr = __raw_readl(IRQ_BASE + ICMR); 139 mask = icip & icmr; 140 141 if (mask == 0) 142 break; 143 144 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 145 } while (1); 146 } 147 148 asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 149 { 150 uint32_t ichp; 151 152 do { 153 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 154 155 if ((ichp & ICHP_VAL_IRQ) == 0) 156 break; 157 158 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 159 } while (1); 160 } 161 162 static void __init pxa_init_low_gpio_irq(set_wake_t fn) 163 { 164 int irq; 165 166 /* clear edge detection on GPIO 0 and 1 */ 167 GFER0 &= ~0x3; 168 GRER0 &= ~0x3; 169 GEDR0 = 0x3; 170 171 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 172 irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, 173 handle_edge_irq); 174 irq_set_chip_data(irq, irq_base(0)); 175 set_irq_flags(irq, IRQF_VALID); 176 } 177 178 pxa_low_gpio_chip.irq_set_wake = fn; 179 } 180 181 void __init pxa_init_irq(int irq_nr, set_wake_t fn) 182 { 183 int irq, i, n; 184 185 BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 186 187 pxa_internal_irq_nr = irq_nr; 188 189 for (n = 0; n < irq_nr; n += 32) { 190 void __iomem *base = irq_base(n >> 5); 191 192 __raw_writel(0, base + ICMR); /* disable all IRQs */ 193 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 194 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 195 /* initialize interrupt priority */ 196 if (cpu_has_ipr()) 197 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 198 199 irq = PXA_IRQ(i); 200 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, 201 handle_level_irq); 202 irq_set_chip_data(irq, base); 203 set_irq_flags(irq, IRQF_VALID); 204 } 205 } 206 207 /* only unmasked interrupts kick us out of idle */ 208 __raw_writel(1, irq_base(0) + ICCR); 209 210 pxa_internal_irq_chip.irq_set_wake = fn; 211 pxa_init_low_gpio_irq(fn); 212 } 213 214 #ifdef CONFIG_PM 215 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 216 static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 217 218 static int pxa_irq_suspend(void) 219 { 220 int i; 221 222 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 223 void __iomem *base = irq_base(i); 224 225 saved_icmr[i] = __raw_readl(base + ICMR); 226 __raw_writel(0, base + ICMR); 227 } 228 229 if (cpu_has_ipr()) { 230 for (i = 0; i < pxa_internal_irq_nr; i++) 231 saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 232 } 233 234 return 0; 235 } 236 237 static void pxa_irq_resume(void) 238 { 239 int i; 240 241 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 242 void __iomem *base = irq_base(i); 243 244 __raw_writel(saved_icmr[i], base + ICMR); 245 __raw_writel(0, base + ICLR); 246 } 247 248 if (cpu_has_ipr()) 249 for (i = 0; i < pxa_internal_irq_nr; i++) 250 __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 251 252 __raw_writel(1, IRQ_BASE + ICCR); 253 } 254 #else 255 #define pxa_irq_suspend NULL 256 #define pxa_irq_resume NULL 257 #endif 258 259 struct syscore_ops pxa_irq_syscore_ops = { 260 .suspend = pxa_irq_suspend, 261 .resume = pxa_irq_resume, 262 }; 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