1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/syscore_ops.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 21 #include <asm/exception.h> 22 23 #include <mach/hardware.h> 24 #include <mach/irqs.h> 25 #include <mach/gpio-pxa.h> 26 27 #include "generic.h" 28 29 #define IRQ_BASE io_p2v(0x40d00000) 30 31 #define ICIP (0x000) 32 #define ICMR (0x004) 33 #define ICLR (0x008) 34 #define ICFR (0x00c) 35 #define ICPR (0x010) 36 #define ICCR (0x014) 37 #define ICHP (0x018) 38 #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 39 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 40 (0x144 + (((i) - 64) << 2))) 41 #define ICHP_VAL_IRQ (1 << 31) 42 #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 43 #define IPR_VALID (1 << 31) 44 #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 45 46 #define MAX_INTERNAL_IRQS 128 47 48 /* 49 * This is for peripheral IRQs internal to the PXA chip. 50 */ 51 52 static int pxa_internal_irq_nr; 53 54 static inline int cpu_has_ipr(void) 55 { 56 return !cpu_is_pxa25x(); 57 } 58 59 static inline void __iomem *irq_base(int i) 60 { 61 static unsigned long phys_base[] = { 62 0x40d00000, 63 0x40d0009c, 64 0x40d00130, 65 }; 66 67 return io_p2v(phys_base[i]); 68 } 69 70 void pxa_mask_irq(struct irq_data *d) 71 { 72 void __iomem *base = irq_data_get_irq_chip_data(d); 73 uint32_t icmr = __raw_readl(base + ICMR); 74 75 icmr &= ~(1 << IRQ_BIT(d->irq)); 76 __raw_writel(icmr, base + ICMR); 77 } 78 79 void pxa_unmask_irq(struct irq_data *d) 80 { 81 void __iomem *base = irq_data_get_irq_chip_data(d); 82 uint32_t icmr = __raw_readl(base + ICMR); 83 84 icmr |= 1 << IRQ_BIT(d->irq); 85 __raw_writel(icmr, base + ICMR); 86 } 87 88 static struct irq_chip pxa_internal_irq_chip = { 89 .name = "SC", 90 .irq_ack = pxa_mask_irq, 91 .irq_mask = pxa_mask_irq, 92 .irq_unmask = pxa_unmask_irq, 93 }; 94 95 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 96 { 97 uint32_t icip, icmr, mask; 98 99 do { 100 icip = __raw_readl(IRQ_BASE + ICIP); 101 icmr = __raw_readl(IRQ_BASE + ICMR); 102 mask = icip & icmr; 103 104 if (mask == 0) 105 break; 106 107 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 108 } while (1); 109 } 110 111 asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 112 { 113 uint32_t ichp; 114 115 do { 116 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 117 118 if ((ichp & ICHP_VAL_IRQ) == 0) 119 break; 120 121 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 122 } while (1); 123 } 124 125 void __init pxa_init_irq(int irq_nr, set_wake_t fn) 126 { 127 int irq, i, n; 128 129 BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 130 131 pxa_internal_irq_nr = irq_nr; 132 133 for (n = 0; n < irq_nr; n += 32) { 134 void __iomem *base = irq_base(n >> 5); 135 136 __raw_writel(0, base + ICMR); /* disable all IRQs */ 137 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 138 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 139 /* initialize interrupt priority */ 140 if (cpu_has_ipr()) 141 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 142 143 irq = PXA_IRQ(i); 144 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, 145 handle_level_irq); 146 irq_set_chip_data(irq, base); 147 set_irq_flags(irq, IRQF_VALID); 148 } 149 } 150 151 /* only unmasked interrupts kick us out of idle */ 152 __raw_writel(1, irq_base(0) + ICCR); 153 154 pxa_internal_irq_chip.irq_set_wake = fn; 155 } 156 157 #ifdef CONFIG_PM 158 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 159 static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 160 161 static int pxa_irq_suspend(void) 162 { 163 int i; 164 165 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 166 void __iomem *base = irq_base(i); 167 168 saved_icmr[i] = __raw_readl(base + ICMR); 169 __raw_writel(0, base + ICMR); 170 } 171 172 if (cpu_has_ipr()) { 173 for (i = 0; i < pxa_internal_irq_nr; i++) 174 saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 175 } 176 177 return 0; 178 } 179 180 static void pxa_irq_resume(void) 181 { 182 int i; 183 184 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 185 void __iomem *base = irq_base(i); 186 187 __raw_writel(saved_icmr[i], base + ICMR); 188 __raw_writel(0, base + ICLR); 189 } 190 191 if (cpu_has_ipr()) 192 for (i = 0; i < pxa_internal_irq_nr; i++) 193 __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 194 195 __raw_writel(1, IRQ_BASE + ICCR); 196 } 197 #else 198 #define pxa_irq_suspend NULL 199 #define pxa_irq_resume NULL 200 #endif 201 202 struct syscore_ops pxa_irq_syscore_ops = { 203 .suspend = pxa_irq_suspend, 204 .resume = pxa_irq_resume, 205 }; 206