1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/sysdev.h> 19 20 #include <asm/hardware.h> 21 #include <asm/irq.h> 22 #include <asm/mach/irq.h> 23 #include <asm/arch/pxa-regs.h> 24 25 #include "generic.h" 26 27 28 /* 29 * This is for peripheral IRQs internal to the PXA chip. 30 */ 31 32 static void pxa_mask_low_irq(unsigned int irq) 33 { 34 ICMR &= ~(1 << irq); 35 } 36 37 static void pxa_unmask_low_irq(unsigned int irq) 38 { 39 ICMR |= (1 << irq); 40 } 41 42 static struct irq_chip pxa_internal_chip_low = { 43 .name = "SC", 44 .ack = pxa_mask_low_irq, 45 .mask = pxa_mask_low_irq, 46 .unmask = pxa_unmask_low_irq, 47 }; 48 49 void __init pxa_init_irq_low(void) 50 { 51 int irq; 52 53 /* disable all IRQs */ 54 ICMR = 0; 55 56 /* all IRQs are IRQ, not FIQ */ 57 ICLR = 0; 58 59 /* only unmasked interrupts kick us out of idle */ 60 ICCR = 1; 61 62 for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { 63 set_irq_chip(irq, &pxa_internal_chip_low); 64 set_irq_handler(irq, handle_level_irq); 65 set_irq_flags(irq, IRQF_VALID); 66 } 67 } 68 69 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 70 71 /* 72 * This is for the second set of internal IRQs as found on the PXA27x. 73 */ 74 75 static void pxa_mask_high_irq(unsigned int irq) 76 { 77 ICMR2 &= ~(1 << (irq - 32)); 78 } 79 80 static void pxa_unmask_high_irq(unsigned int irq) 81 { 82 ICMR2 |= (1 << (irq - 32)); 83 } 84 85 static struct irq_chip pxa_internal_chip_high = { 86 .name = "SC-hi", 87 .ack = pxa_mask_high_irq, 88 .mask = pxa_mask_high_irq, 89 .unmask = pxa_unmask_high_irq, 90 }; 91 92 void __init pxa_init_irq_high(void) 93 { 94 int irq; 95 96 ICMR2 = 0; 97 ICLR2 = 0; 98 99 for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { 100 set_irq_chip(irq, &pxa_internal_chip_high); 101 set_irq_handler(irq, handle_level_irq); 102 set_irq_flags(irq, IRQF_VALID); 103 } 104 } 105 #endif 106 107 /* 108 * PXA GPIO edge detection for IRQs: 109 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 110 * Use this instead of directly setting GRER/GFER. 111 */ 112 113 static long GPIO_IRQ_rising_edge[4]; 114 static long GPIO_IRQ_falling_edge[4]; 115 static long GPIO_IRQ_mask[4]; 116 117 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 118 { 119 int gpio, idx; 120 121 gpio = IRQ_TO_GPIO(irq); 122 idx = gpio >> 5; 123 124 if (type == IRQT_PROBE) { 125 /* Don't mess with enabled GPIOs using preconfigured edges or 126 GPIOs set to alternate function or to output during probe */ 127 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & 128 GPIO_bit(gpio)) 129 return 0; 130 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) 131 return 0; 132 type = __IRQT_RISEDGE | __IRQT_FALEDGE; 133 } 134 135 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ 136 137 pxa_gpio_mode(gpio | GPIO_IN); 138 139 if (type & __IRQT_RISEDGE) { 140 /* printk("rising "); */ 141 __set_bit (gpio, GPIO_IRQ_rising_edge); 142 } else { 143 __clear_bit (gpio, GPIO_IRQ_rising_edge); 144 } 145 146 if (type & __IRQT_FALEDGE) { 147 /* printk("falling "); */ 148 __set_bit (gpio, GPIO_IRQ_falling_edge); 149 } else { 150 __clear_bit (gpio, GPIO_IRQ_falling_edge); 151 } 152 153 /* printk("edges\n"); */ 154 155 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 156 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 157 return 0; 158 } 159 160 /* 161 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. 162 */ 163 164 static void pxa_ack_low_gpio(unsigned int irq) 165 { 166 GEDR0 = (1 << (irq - IRQ_GPIO0)); 167 } 168 169 static struct irq_chip pxa_low_gpio_chip = { 170 .name = "GPIO-l", 171 .ack = pxa_ack_low_gpio, 172 .mask = pxa_mask_low_irq, 173 .unmask = pxa_unmask_low_irq, 174 .set_type = pxa_gpio_irq_type, 175 }; 176 177 /* 178 * Demux handler for GPIO>=2 edge detect interrupts 179 */ 180 181 #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) 182 183 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 184 { 185 int loop, bit, n; 186 unsigned long gedr[4]; 187 188 do { 189 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; 190 gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; 191 gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; 192 gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; 193 194 GEDR0 = gedr[0]; GEDR1 = gedr[1]; 195 GEDR2 = gedr[2]; GEDR3 = gedr[3]; 196 197 loop = 0; 198 bit = find_first_bit(gedr, GEDR_BITS); 199 while (bit < GEDR_BITS) { 200 loop = 1; 201 202 n = PXA_GPIO_IRQ_BASE + bit; 203 desc_handle_irq(n, irq_desc + n); 204 205 bit = find_next_bit(gedr, GEDR_BITS, bit + 1); 206 } 207 } while (loop); 208 } 209 210 static void pxa_ack_muxed_gpio(unsigned int irq) 211 { 212 int gpio = irq - IRQ_GPIO(2) + 2; 213 GEDR(gpio) = GPIO_bit(gpio); 214 } 215 216 static void pxa_mask_muxed_gpio(unsigned int irq) 217 { 218 int gpio = irq - IRQ_GPIO(2) + 2; 219 __clear_bit(gpio, GPIO_IRQ_mask); 220 GRER(gpio) &= ~GPIO_bit(gpio); 221 GFER(gpio) &= ~GPIO_bit(gpio); 222 } 223 224 static void pxa_unmask_muxed_gpio(unsigned int irq) 225 { 226 int gpio = irq - IRQ_GPIO(2) + 2; 227 int idx = gpio >> 5; 228 __set_bit(gpio, GPIO_IRQ_mask); 229 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 230 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 231 } 232 233 static struct irq_chip pxa_muxed_gpio_chip = { 234 .name = "GPIO", 235 .ack = pxa_ack_muxed_gpio, 236 .mask = pxa_mask_muxed_gpio, 237 .unmask = pxa_unmask_muxed_gpio, 238 .set_type = pxa_gpio_irq_type, 239 }; 240 241 void __init pxa_init_irq_gpio(int gpio_nr) 242 { 243 int irq, i; 244 245 pxa_last_gpio = gpio_nr - 1; 246 247 /* clear all GPIO edge detects */ 248 for (i = 0; i < gpio_nr; i += 32) { 249 GFER(i) = 0; 250 GRER(i) = 0; 251 GEDR(i) = GEDR(i); 252 } 253 254 /* GPIO 0 and 1 must have their mask bit always set */ 255 GPIO_IRQ_mask[0] = 3; 256 257 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 258 set_irq_chip(irq, &pxa_low_gpio_chip); 259 set_irq_handler(irq, handle_edge_irq); 260 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 261 } 262 263 for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { 264 set_irq_chip(irq, &pxa_muxed_gpio_chip); 265 set_irq_handler(irq, handle_edge_irq); 266 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 267 } 268 269 /* Install handler for GPIO>=2 edge detect interrupts */ 270 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 271 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 272 273 pxa_init_gpio(gpio_nr); 274 } 275 276 void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) 277 { 278 pxa_internal_chip_low.set_wake = set_wake; 279 #ifdef CONFIG_PXA27x 280 pxa_internal_chip_high.set_wake = set_wake; 281 #endif 282 pxa_low_gpio_chip.set_wake = set_wake; 283 pxa_muxed_gpio_chip.set_wake = set_wake; 284 } 285 286 #ifdef CONFIG_PM 287 static unsigned long saved_icmr[2]; 288 289 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) 290 { 291 switch (dev->id) { 292 case 0: 293 saved_icmr[0] = ICMR; 294 ICMR = 0; 295 break; 296 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 297 case 1: 298 saved_icmr[1] = ICMR2; 299 ICMR2 = 0; 300 break; 301 #endif 302 default: 303 return -EINVAL; 304 } 305 306 return 0; 307 } 308 309 static int pxa_irq_resume(struct sys_device *dev) 310 { 311 switch (dev->id) { 312 case 0: 313 ICMR = saved_icmr[0]; 314 ICLR = 0; 315 ICCR = 1; 316 break; 317 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 318 case 1: 319 ICMR2 = saved_icmr[1]; 320 ICLR2 = 0; 321 break; 322 #endif 323 default: 324 return -EINVAL; 325 } 326 327 return 0; 328 } 329 #else 330 #define pxa_irq_suspend NULL 331 #define pxa_irq_resume NULL 332 #endif 333 334 struct sysdev_class pxa_irq_sysclass = { 335 .name = "irq", 336 .suspend = pxa_irq_suspend, 337 .resume = pxa_irq_resume, 338 }; 339 340 static int __init pxa_irq_init(void) 341 { 342 return sysdev_class_register(&pxa_irq_sysclass); 343 } 344 345 core_initcall(pxa_irq_init); 346