1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/syscore_ops.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 21 #include <asm/exception.h> 22 23 #include <mach/hardware.h> 24 #include <mach/irqs.h> 25 #include <mach/gpio-pxa.h> 26 27 #include "generic.h" 28 29 #define IRQ_BASE io_p2v(0x40d00000) 30 31 #define ICIP (0x000) 32 #define ICMR (0x004) 33 #define ICLR (0x008) 34 #define ICFR (0x00c) 35 #define ICPR (0x010) 36 #define ICCR (0x014) 37 #define ICHP (0x018) 38 #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 39 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 40 (0x144 + (((i) - 64) << 2))) 41 #define ICHP_VAL_IRQ (1 << 31) 42 #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 43 #define IPR_VALID (1 << 31) 44 #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 45 46 #define MAX_INTERNAL_IRQS 128 47 48 /* 49 * This is for peripheral IRQs internal to the PXA chip. 50 */ 51 52 static int pxa_internal_irq_nr; 53 54 static inline int cpu_has_ipr(void) 55 { 56 return !cpu_is_pxa25x(); 57 } 58 59 static inline void __iomem *irq_base(int i) 60 { 61 static unsigned long phys_base[] = { 62 0x40d00000, 63 0x40d0009c, 64 0x40d00130, 65 }; 66 67 return io_p2v(phys_base[i]); 68 } 69 70 void pxa_mask_irq(struct irq_data *d) 71 { 72 void __iomem *base = irq_data_get_irq_chip_data(d); 73 uint32_t icmr = __raw_readl(base + ICMR); 74 75 icmr &= ~(1 << IRQ_BIT(d->irq)); 76 __raw_writel(icmr, base + ICMR); 77 } 78 79 void pxa_unmask_irq(struct irq_data *d) 80 { 81 void __iomem *base = irq_data_get_irq_chip_data(d); 82 uint32_t icmr = __raw_readl(base + ICMR); 83 84 icmr |= 1 << IRQ_BIT(d->irq); 85 __raw_writel(icmr, base + ICMR); 86 } 87 88 static struct irq_chip pxa_internal_irq_chip = { 89 .name = "SC", 90 .irq_ack = pxa_mask_irq, 91 .irq_mask = pxa_mask_irq, 92 .irq_unmask = pxa_unmask_irq, 93 }; 94 95 /* 96 * GPIO IRQs for GPIO 0 and 1 97 */ 98 static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) 99 { 100 int gpio = d->irq - IRQ_GPIO0; 101 102 if (__gpio_is_occupied(gpio)) { 103 pr_err("%s failed: GPIO is configured\n", __func__); 104 return -EINVAL; 105 } 106 107 if (type & IRQ_TYPE_EDGE_RISING) 108 GRER0 |= GPIO_bit(gpio); 109 else 110 GRER0 &= ~GPIO_bit(gpio); 111 112 if (type & IRQ_TYPE_EDGE_FALLING) 113 GFER0 |= GPIO_bit(gpio); 114 else 115 GFER0 &= ~GPIO_bit(gpio); 116 117 return 0; 118 } 119 120 static void pxa_ack_low_gpio(struct irq_data *d) 121 { 122 GEDR0 = (1 << (d->irq - IRQ_GPIO0)); 123 } 124 125 static struct irq_chip pxa_low_gpio_chip = { 126 .name = "GPIO-l", 127 .irq_ack = pxa_ack_low_gpio, 128 .irq_mask = pxa_mask_irq, 129 .irq_unmask = pxa_unmask_irq, 130 .irq_set_type = pxa_set_low_gpio_type, 131 }; 132 133 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 134 { 135 uint32_t icip, icmr, mask; 136 137 do { 138 icip = __raw_readl(IRQ_BASE + ICIP); 139 icmr = __raw_readl(IRQ_BASE + ICMR); 140 mask = icip & icmr; 141 142 if (mask == 0) 143 break; 144 145 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 146 } while (1); 147 } 148 149 asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 150 { 151 uint32_t ichp; 152 153 do { 154 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 155 156 if ((ichp & ICHP_VAL_IRQ) == 0) 157 break; 158 159 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 160 } while (1); 161 } 162 163 static void __init pxa_init_low_gpio_irq(set_wake_t fn) 164 { 165 int irq; 166 167 /* clear edge detection on GPIO 0 and 1 */ 168 GFER0 &= ~0x3; 169 GRER0 &= ~0x3; 170 GEDR0 = 0x3; 171 172 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 173 irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, 174 handle_edge_irq); 175 irq_set_chip_data(irq, irq_base(0)); 176 set_irq_flags(irq, IRQF_VALID); 177 } 178 179 pxa_low_gpio_chip.irq_set_wake = fn; 180 } 181 182 void __init pxa_init_irq(int irq_nr, set_wake_t fn) 183 { 184 int irq, i, n; 185 186 BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 187 188 pxa_internal_irq_nr = irq_nr; 189 190 for (n = 0; n < irq_nr; n += 32) { 191 void __iomem *base = irq_base(n >> 5); 192 193 __raw_writel(0, base + ICMR); /* disable all IRQs */ 194 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 195 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 196 /* initialize interrupt priority */ 197 if (cpu_has_ipr()) 198 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 199 200 irq = PXA_IRQ(i); 201 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, 202 handle_level_irq); 203 irq_set_chip_data(irq, base); 204 set_irq_flags(irq, IRQF_VALID); 205 } 206 } 207 208 /* only unmasked interrupts kick us out of idle */ 209 __raw_writel(1, irq_base(0) + ICCR); 210 211 pxa_internal_irq_chip.irq_set_wake = fn; 212 pxa_init_low_gpio_irq(fn); 213 } 214 215 #ifdef CONFIG_PM 216 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 217 static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 218 219 static int pxa_irq_suspend(void) 220 { 221 int i; 222 223 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 224 void __iomem *base = irq_base(i); 225 226 saved_icmr[i] = __raw_readl(base + ICMR); 227 __raw_writel(0, base + ICMR); 228 } 229 230 if (cpu_has_ipr()) { 231 for (i = 0; i < pxa_internal_irq_nr; i++) 232 saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 233 } 234 235 return 0; 236 } 237 238 static void pxa_irq_resume(void) 239 { 240 int i; 241 242 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 243 void __iomem *base = irq_base(i); 244 245 __raw_writel(saved_icmr[i], base + ICMR); 246 __raw_writel(0, base + ICLR); 247 } 248 249 if (cpu_has_ipr()) 250 for (i = 0; i < pxa_internal_irq_nr; i++) 251 __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 252 253 __raw_writel(1, IRQ_BASE + ICCR); 254 } 255 #else 256 #define pxa_irq_suspend NULL 257 #define pxa_irq_resume NULL 258 #endif 259 260 struct syscore_ops pxa_irq_syscore_ops = { 261 .suspend = pxa_irq_suspend, 262 .resume = pxa_irq_resume, 263 }; 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