1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/sysdev.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 22 #include <mach/hardware.h> 23 #include <mach/irqs.h> 24 #include <mach/gpio.h> 25 26 #include "generic.h" 27 28 #define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) 29 30 #define ICIP (0x000) 31 #define ICMR (0x004) 32 #define ICLR (0x008) 33 #define ICFR (0x00c) 34 #define ICPR (0x010) 35 #define ICCR (0x014) 36 #define ICHP (0x018) 37 #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 38 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 39 (0x144 + (((i) - 64) << 2))) 40 #define IPR_VALID (1 << 31) 41 #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 42 43 #define MAX_INTERNAL_IRQS 128 44 45 /* 46 * This is for peripheral IRQs internal to the PXA chip. 47 */ 48 49 static int pxa_internal_irq_nr; 50 51 static inline int cpu_has_ipr(void) 52 { 53 return !cpu_is_pxa25x(); 54 } 55 56 static void pxa_mask_irq(struct irq_data *d) 57 { 58 void __iomem *base = irq_data_get_irq_chip_data(d); 59 uint32_t icmr = __raw_readl(base + ICMR); 60 61 icmr &= ~(1 << IRQ_BIT(d->irq)); 62 __raw_writel(icmr, base + ICMR); 63 } 64 65 static void pxa_unmask_irq(struct irq_data *d) 66 { 67 void __iomem *base = irq_data_get_irq_chip_data(d); 68 uint32_t icmr = __raw_readl(base + ICMR); 69 70 icmr |= 1 << IRQ_BIT(d->irq); 71 __raw_writel(icmr, base + ICMR); 72 } 73 74 static struct irq_chip pxa_internal_irq_chip = { 75 .name = "SC", 76 .irq_ack = pxa_mask_irq, 77 .irq_mask = pxa_mask_irq, 78 .irq_unmask = pxa_unmask_irq, 79 }; 80 81 /* 82 * GPIO IRQs for GPIO 0 and 1 83 */ 84 static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) 85 { 86 int gpio = d->irq - IRQ_GPIO0; 87 88 if (__gpio_is_occupied(gpio)) { 89 pr_err("%s failed: GPIO is configured\n", __func__); 90 return -EINVAL; 91 } 92 93 if (type & IRQ_TYPE_EDGE_RISING) 94 GRER0 |= GPIO_bit(gpio); 95 else 96 GRER0 &= ~GPIO_bit(gpio); 97 98 if (type & IRQ_TYPE_EDGE_FALLING) 99 GFER0 |= GPIO_bit(gpio); 100 else 101 GFER0 &= ~GPIO_bit(gpio); 102 103 return 0; 104 } 105 106 static void pxa_ack_low_gpio(struct irq_data *d) 107 { 108 GEDR0 = (1 << (d->irq - IRQ_GPIO0)); 109 } 110 111 static void pxa_mask_low_gpio(struct irq_data *d) 112 { 113 struct irq_desc *desc = irq_to_desc(d->irq); 114 115 desc->irq_data.chip->irq_mask(d); 116 } 117 118 static void pxa_unmask_low_gpio(struct irq_data *d) 119 { 120 struct irq_desc *desc = irq_to_desc(d->irq); 121 122 desc->irq_data.chip->irq_unmask(d); 123 } 124 125 static struct irq_chip pxa_low_gpio_chip = { 126 .name = "GPIO-l", 127 .irq_ack = pxa_ack_low_gpio, 128 .irq_mask = pxa_mask_low_gpio, 129 .irq_unmask = pxa_unmask_low_gpio, 130 .irq_set_type = pxa_set_low_gpio_type, 131 }; 132 133 static void __init pxa_init_low_gpio_irq(set_wake_t fn) 134 { 135 int irq; 136 137 /* clear edge detection on GPIO 0 and 1 */ 138 GFER0 &= ~0x3; 139 GRER0 &= ~0x3; 140 GEDR0 = 0x3; 141 142 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 143 set_irq_chip(irq, &pxa_low_gpio_chip); 144 set_irq_handler(irq, handle_edge_irq); 145 set_irq_flags(irq, IRQF_VALID); 146 } 147 148 pxa_low_gpio_chip.irq_set_wake = fn; 149 } 150 151 static inline void __iomem *irq_base(int i) 152 { 153 static unsigned long phys_base[] = { 154 0x40d00000, 155 0x40d0009c, 156 0x40d00130, 157 }; 158 159 return (void __iomem *)io_p2v(phys_base[i]); 160 } 161 162 void __init pxa_init_irq(int irq_nr, set_wake_t fn) 163 { 164 int irq, i, n; 165 166 BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 167 168 pxa_internal_irq_nr = irq_nr; 169 170 for (n = 0; n < irq_nr; n += 32) { 171 void __iomem *base = irq_base(n >> 5); 172 173 __raw_writel(0, base + ICMR); /* disable all IRQs */ 174 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 175 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 176 /* initialize interrupt priority */ 177 if (cpu_has_ipr()) 178 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 179 180 irq = PXA_IRQ(i); 181 set_irq_chip(irq, &pxa_internal_irq_chip); 182 set_irq_chip_data(irq, base); 183 set_irq_handler(irq, handle_level_irq); 184 set_irq_flags(irq, IRQF_VALID); 185 } 186 } 187 188 /* only unmasked interrupts kick us out of idle */ 189 __raw_writel(1, irq_base(0) + ICCR); 190 191 pxa_internal_irq_chip.irq_set_wake = fn; 192 pxa_init_low_gpio_irq(fn); 193 } 194 195 #ifdef CONFIG_PM 196 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 197 static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 198 199 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) 200 { 201 int i; 202 203 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 204 void __iomem *base = irq_base(i); 205 206 saved_icmr[i] = __raw_readl(base + ICMR); 207 __raw_writel(0, base + ICMR); 208 } 209 210 if (cpu_has_ipr()) { 211 for (i = 0; i < pxa_internal_irq_nr; i++) 212 saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 213 } 214 215 return 0; 216 } 217 218 static int pxa_irq_resume(struct sys_device *dev) 219 { 220 int i; 221 222 for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 223 void __iomem *base = irq_base(i); 224 225 __raw_writel(saved_icmr[i], base + ICMR); 226 __raw_writel(0, base + ICLR); 227 } 228 229 if (cpu_has_ipr()) 230 for (i = 0; i < pxa_internal_irq_nr; i++) 231 __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 232 233 __raw_writel(1, IRQ_BASE + ICCR); 234 return 0; 235 } 236 #else 237 #define pxa_irq_suspend NULL 238 #define pxa_irq_resume NULL 239 #endif 240 241 struct sysdev_class pxa_irq_sysclass = { 242 .name = "irq", 243 .suspend = pxa_irq_suspend, 244 .resume = pxa_irq_resume, 245 }; 246 247 static int __init pxa_irq_init(void) 248 { 249 return sysdev_class_register(&pxa_irq_sysclass); 250 } 251 252 core_initcall(pxa_irq_init); 253