1 /* 2 * linux/arch/arm/mach-pxa/irq.c 3 * 4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 19 #include <asm/hardware.h> 20 #include <asm/irq.h> 21 #include <asm/mach/irq.h> 22 #include <asm/arch/pxa-regs.h> 23 24 #include "generic.h" 25 26 27 /* 28 * This is for peripheral IRQs internal to the PXA chip. 29 */ 30 31 static void pxa_mask_low_irq(unsigned int irq) 32 { 33 ICMR &= ~(1 << (irq + PXA_IRQ_SKIP)); 34 } 35 36 static void pxa_unmask_low_irq(unsigned int irq) 37 { 38 ICMR |= (1 << (irq + PXA_IRQ_SKIP)); 39 } 40 41 static struct irq_chip pxa_internal_chip_low = { 42 .name = "SC", 43 .ack = pxa_mask_low_irq, 44 .mask = pxa_mask_low_irq, 45 .unmask = pxa_unmask_low_irq, 46 }; 47 48 #if PXA_INTERNAL_IRQS > 32 49 50 /* 51 * This is for the second set of internal IRQs as found on the PXA27x. 52 */ 53 54 static void pxa_mask_high_irq(unsigned int irq) 55 { 56 ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP)); 57 } 58 59 static void pxa_unmask_high_irq(unsigned int irq) 60 { 61 ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP)); 62 } 63 64 static struct irq_chip pxa_internal_chip_high = { 65 .name = "SC-hi", 66 .ack = pxa_mask_high_irq, 67 .mask = pxa_mask_high_irq, 68 .unmask = pxa_unmask_high_irq, 69 }; 70 71 #endif 72 73 /* 74 * PXA GPIO edge detection for IRQs: 75 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 76 * Use this instead of directly setting GRER/GFER. 77 */ 78 79 static long GPIO_IRQ_rising_edge[4]; 80 static long GPIO_IRQ_falling_edge[4]; 81 static long GPIO_IRQ_mask[4]; 82 83 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 84 { 85 int gpio, idx; 86 87 gpio = IRQ_TO_GPIO(irq); 88 idx = gpio >> 5; 89 90 if (type == IRQT_PROBE) { 91 /* Don't mess with enabled GPIOs using preconfigured edges or 92 GPIOs set to alternate function or to output during probe */ 93 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & 94 GPIO_bit(gpio)) 95 return 0; 96 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) 97 return 0; 98 type = __IRQT_RISEDGE | __IRQT_FALEDGE; 99 } 100 101 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ 102 103 pxa_gpio_mode(gpio | GPIO_IN); 104 105 if (type & __IRQT_RISEDGE) { 106 /* printk("rising "); */ 107 __set_bit (gpio, GPIO_IRQ_rising_edge); 108 } else 109 __clear_bit (gpio, GPIO_IRQ_rising_edge); 110 111 if (type & __IRQT_FALEDGE) { 112 /* printk("falling "); */ 113 __set_bit (gpio, GPIO_IRQ_falling_edge); 114 } else 115 __clear_bit (gpio, GPIO_IRQ_falling_edge); 116 117 /* printk("edges\n"); */ 118 119 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 120 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 121 return 0; 122 } 123 124 /* 125 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. 126 */ 127 128 static void pxa_ack_low_gpio(unsigned int irq) 129 { 130 GEDR0 = (1 << (irq - IRQ_GPIO0)); 131 } 132 133 static struct irq_chip pxa_low_gpio_chip = { 134 .name = "GPIO-l", 135 .ack = pxa_ack_low_gpio, 136 .mask = pxa_mask_low_irq, 137 .unmask = pxa_unmask_low_irq, 138 .set_type = pxa_gpio_irq_type, 139 }; 140 141 /* 142 * Demux handler for GPIO>=2 edge detect interrupts 143 */ 144 145 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 146 { 147 unsigned int mask; 148 int loop; 149 150 do { 151 loop = 0; 152 153 mask = GEDR0 & ~3; 154 if (mask) { 155 GEDR0 = mask; 156 irq = IRQ_GPIO(2); 157 desc = irq_desc + irq; 158 mask >>= 2; 159 do { 160 if (mask & 1) 161 desc_handle_irq(irq, desc); 162 irq++; 163 desc++; 164 mask >>= 1; 165 } while (mask); 166 loop = 1; 167 } 168 169 mask = GEDR1; 170 if (mask) { 171 GEDR1 = mask; 172 irq = IRQ_GPIO(32); 173 desc = irq_desc + irq; 174 do { 175 if (mask & 1) 176 desc_handle_irq(irq, desc); 177 irq++; 178 desc++; 179 mask >>= 1; 180 } while (mask); 181 loop = 1; 182 } 183 184 mask = GEDR2; 185 if (mask) { 186 GEDR2 = mask; 187 irq = IRQ_GPIO(64); 188 desc = irq_desc + irq; 189 do { 190 if (mask & 1) 191 desc_handle_irq(irq, desc); 192 irq++; 193 desc++; 194 mask >>= 1; 195 } while (mask); 196 loop = 1; 197 } 198 199 #if PXA_LAST_GPIO >= 96 200 mask = GEDR3; 201 if (mask) { 202 GEDR3 = mask; 203 irq = IRQ_GPIO(96); 204 desc = irq_desc + irq; 205 do { 206 if (mask & 1) 207 desc_handle_irq(irq, desc); 208 irq++; 209 desc++; 210 mask >>= 1; 211 } while (mask); 212 loop = 1; 213 } 214 #endif 215 } while (loop); 216 } 217 218 static void pxa_ack_muxed_gpio(unsigned int irq) 219 { 220 int gpio = irq - IRQ_GPIO(2) + 2; 221 GEDR(gpio) = GPIO_bit(gpio); 222 } 223 224 static void pxa_mask_muxed_gpio(unsigned int irq) 225 { 226 int gpio = irq - IRQ_GPIO(2) + 2; 227 __clear_bit(gpio, GPIO_IRQ_mask); 228 GRER(gpio) &= ~GPIO_bit(gpio); 229 GFER(gpio) &= ~GPIO_bit(gpio); 230 } 231 232 static void pxa_unmask_muxed_gpio(unsigned int irq) 233 { 234 int gpio = irq - IRQ_GPIO(2) + 2; 235 int idx = gpio >> 5; 236 __set_bit(gpio, GPIO_IRQ_mask); 237 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 238 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 239 } 240 241 static struct irq_chip pxa_muxed_gpio_chip = { 242 .name = "GPIO", 243 .ack = pxa_ack_muxed_gpio, 244 .mask = pxa_mask_muxed_gpio, 245 .unmask = pxa_unmask_muxed_gpio, 246 .set_type = pxa_gpio_irq_type, 247 }; 248 249 250 void __init pxa_init_irq(void) 251 { 252 int irq; 253 254 /* disable all IRQs */ 255 ICMR = 0; 256 257 /* all IRQs are IRQ, not FIQ */ 258 ICLR = 0; 259 260 /* clear all GPIO edge detects */ 261 GFER0 = 0; 262 GFER1 = 0; 263 GFER2 = 0; 264 GRER0 = 0; 265 GRER1 = 0; 266 GRER2 = 0; 267 GEDR0 = GEDR0; 268 GEDR1 = GEDR1; 269 GEDR2 = GEDR2; 270 271 #ifdef CONFIG_PXA27x 272 /* And similarly for the extra regs on the PXA27x */ 273 ICMR2 = 0; 274 ICLR2 = 0; 275 GFER3 = 0; 276 GRER3 = 0; 277 GEDR3 = GEDR3; 278 #endif 279 280 /* only unmasked interrupts kick us out of idle */ 281 ICCR = 1; 282 283 /* GPIO 0 and 1 must have their mask bit always set */ 284 GPIO_IRQ_mask[0] = 3; 285 286 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { 287 set_irq_chip(irq, &pxa_internal_chip_low); 288 set_irq_handler(irq, handle_level_irq); 289 set_irq_flags(irq, IRQF_VALID); 290 } 291 292 #if PXA_INTERNAL_IRQS > 32 293 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { 294 set_irq_chip(irq, &pxa_internal_chip_high); 295 set_irq_handler(irq, handle_level_irq); 296 set_irq_flags(irq, IRQF_VALID); 297 } 298 #endif 299 300 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 301 set_irq_chip(irq, &pxa_low_gpio_chip); 302 set_irq_handler(irq, handle_edge_irq); 303 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 304 } 305 306 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { 307 set_irq_chip(irq, &pxa_muxed_gpio_chip); 308 set_irq_handler(irq, handle_edge_irq); 309 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 310 } 311 312 /* Install handler for GPIO>=2 edge detect interrupts */ 313 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 314 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 315 } 316