1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 41da177e4SLinus Torvalds * 5e3630db1Seric miao * Generic PXA IRQ handling 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Author: Nicolas Pitre 81da177e4SLinus Torvalds * Created: Jun 15, 2001 91da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 101da177e4SLinus Torvalds */ 11d6cf30caSRobert Jarzmik #include <linux/bitops.h> 121da177e4SLinus Torvalds #include <linux/init.h> 131da177e4SLinus Torvalds #include <linux/module.h> 141da177e4SLinus Torvalds #include <linux/interrupt.h> 152eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 16a79a9ad9SHaojian Zhuang #include <linux/io.h> 17a79a9ad9SHaojian Zhuang #include <linux/irq.h> 18089d0362SDaniel Mack #include <linux/of_address.h> 19089d0362SDaniel Mack #include <linux/of_irq.h> 2008d3df8cSArnd Bergmann #include <linux/soc/pxa/cpu.h> 211da177e4SLinus Torvalds 225a567d78SJamie Iles #include <asm/exception.h> 235a567d78SJamie Iles 24*e6acc406SArnd Bergmann #include "irqs.h" 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds #include "generic.h" 2708d3df8cSArnd Bergmann #include "pxa-regs.h" 281da177e4SLinus Torvalds 29a79a9ad9SHaojian Zhuang #define ICIP (0x000) 30a79a9ad9SHaojian Zhuang #define ICMR (0x004) 31a79a9ad9SHaojian Zhuang #define ICLR (0x008) 32a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 33a79a9ad9SHaojian Zhuang #define ICPR (0x010) 34a79a9ad9SHaojian Zhuang #define ICCR (0x014) 35a79a9ad9SHaojian Zhuang #define ICHP (0x018) 36a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 37a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 38a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 39a551e4f7SEric Miao #define ICHP_VAL_IRQ (1 << 31) 40a551e4f7SEric Miao #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 41a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 42a79a9ad9SHaojian Zhuang 43a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 441da177e4SLinus Torvalds 451da177e4SLinus Torvalds /* 461da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 471da177e4SLinus Torvalds */ 481da177e4SLinus Torvalds 49089d0362SDaniel Mack static void __iomem *pxa_irq_base; 50f6fb7af4Seric miao static int pxa_internal_irq_nr; 51089d0362SDaniel Mack static bool cpu_has_ipr; 52d6cf30caSRobert Jarzmik static struct irq_domain *pxa_irq_domain; 53bb71bdd3SHaojian Zhuang 54a1015a15SEric Miao static inline void __iomem *irq_base(int i) 55a1015a15SEric Miao { 56089d0362SDaniel Mack static unsigned long phys_base_offset[] = { 57089d0362SDaniel Mack 0x0, 58089d0362SDaniel Mack 0x9c, 59089d0362SDaniel Mack 0x130, 60a1015a15SEric Miao }; 61a1015a15SEric Miao 62089d0362SDaniel Mack return pxa_irq_base + phys_base_offset[i]; 63a1015a15SEric Miao } 64a1015a15SEric Miao 655d284e35SEric Miao void pxa_mask_irq(struct irq_data *d) 661da177e4SLinus Torvalds { 67a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 68d6cf30caSRobert Jarzmik irq_hw_number_t irq = irqd_to_hwirq(d); 69a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 70a79a9ad9SHaojian Zhuang 71d6cf30caSRobert Jarzmik icmr &= ~BIT(irq & 0x1f); 72a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 731da177e4SLinus Torvalds } 741da177e4SLinus Torvalds 755d284e35SEric Miao void pxa_unmask_irq(struct irq_data *d) 761da177e4SLinus Torvalds { 77a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 78d6cf30caSRobert Jarzmik irq_hw_number_t irq = irqd_to_hwirq(d); 79a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 80a79a9ad9SHaojian Zhuang 81d6cf30caSRobert Jarzmik icmr |= BIT(irq & 0x1f); 82a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 831da177e4SLinus Torvalds } 841da177e4SLinus Torvalds 85f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 8638c677cbSDavid Brownell .name = "SC", 87a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 88a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 89a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 901da177e4SLinus Torvalds }; 911da177e4SLinus Torvalds 92a551e4f7SEric Miao asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 93a551e4f7SEric Miao { 94a551e4f7SEric Miao uint32_t icip, icmr, mask; 95a551e4f7SEric Miao 96a551e4f7SEric Miao do { 97089d0362SDaniel Mack icip = __raw_readl(pxa_irq_base + ICIP); 98089d0362SDaniel Mack icmr = __raw_readl(pxa_irq_base + ICMR); 99a551e4f7SEric Miao mask = icip & icmr; 100a551e4f7SEric Miao 101a551e4f7SEric Miao if (mask == 0) 102a551e4f7SEric Miao break; 103a551e4f7SEric Miao 104a551e4f7SEric Miao handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 105a551e4f7SEric Miao } while (1); 106a551e4f7SEric Miao } 107a551e4f7SEric Miao 108a551e4f7SEric Miao asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 109a551e4f7SEric Miao { 110a551e4f7SEric Miao uint32_t ichp; 111a551e4f7SEric Miao 112a551e4f7SEric Miao do { 113a551e4f7SEric Miao __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 114a551e4f7SEric Miao 115a551e4f7SEric Miao if ((ichp & ICHP_VAL_IRQ) == 0) 116a551e4f7SEric Miao break; 117a551e4f7SEric Miao 118a551e4f7SEric Miao handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 119a551e4f7SEric Miao } while (1); 120a551e4f7SEric Miao } 121a551e4f7SEric Miao 122d6cf30caSRobert Jarzmik static int pxa_irq_map(struct irq_domain *h, unsigned int virq, 123d6cf30caSRobert Jarzmik irq_hw_number_t hw) 12453665a50SEric Miao { 125d6cf30caSRobert Jarzmik void __iomem *base = irq_base(hw / 32); 12653665a50SEric Miao 127d6cf30caSRobert Jarzmik /* initialize interrupt priority */ 128d6cf30caSRobert Jarzmik if (cpu_has_ipr) 129d6cf30caSRobert Jarzmik __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); 130d6cf30caSRobert Jarzmik 131d6cf30caSRobert Jarzmik irq_set_chip_and_handler(virq, &pxa_internal_irq_chip, 132d6cf30caSRobert Jarzmik handle_level_irq); 133d6cf30caSRobert Jarzmik irq_set_chip_data(virq, base); 134d6cf30caSRobert Jarzmik 135d6cf30caSRobert Jarzmik return 0; 136d6cf30caSRobert Jarzmik } 137d6cf30caSRobert Jarzmik 13864227114SKrzysztof Kozlowski static const struct irq_domain_ops pxa_irq_ops = { 139d6cf30caSRobert Jarzmik .map = pxa_irq_map, 140d6cf30caSRobert Jarzmik .xlate = irq_domain_xlate_onecell, 141d6cf30caSRobert Jarzmik }; 142d6cf30caSRobert Jarzmik 143d6cf30caSRobert Jarzmik static __init void 144d6cf30caSRobert Jarzmik pxa_init_irq_common(struct device_node *node, int irq_nr, 145d6cf30caSRobert Jarzmik int (*fn)(struct irq_data *, unsigned int)) 146d6cf30caSRobert Jarzmik { 147d6cf30caSRobert Jarzmik int n; 148c482ae4dSHaojian Zhuang 149f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 150d6cf30caSRobert Jarzmik pxa_irq_domain = irq_domain_add_legacy(node, irq_nr, 151d6cf30caSRobert Jarzmik PXA_IRQ(0), 0, 152d6cf30caSRobert Jarzmik &pxa_irq_ops, NULL); 153d6cf30caSRobert Jarzmik if (!pxa_irq_domain) 154d6cf30caSRobert Jarzmik panic("Unable to add PXA IRQ domain\n"); 155d6cf30caSRobert Jarzmik irq_set_default_host(pxa_irq_domain); 15653665a50SEric Miao 157a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 1581b624fb6SMarek Vasut void __iomem *base = irq_base(n >> 5); 15953665a50SEric Miao 160a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 161a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 16253665a50SEric Miao } 163a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 164a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 16553665a50SEric Miao 166a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 167c95530c7Seric miao } 168c0165504Seric miao 169d6cf30caSRobert Jarzmik void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 170d6cf30caSRobert Jarzmik { 171d6cf30caSRobert Jarzmik BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 172d6cf30caSRobert Jarzmik 173d6cf30caSRobert Jarzmik pxa_irq_base = io_p2v(0x40d00000); 174d6cf30caSRobert Jarzmik cpu_has_ipr = !cpu_is_pxa25x(); 175d6cf30caSRobert Jarzmik pxa_init_irq_common(NULL, irq_nr, fn); 176d6cf30caSRobert Jarzmik } 177d6cf30caSRobert Jarzmik 178c0165504Seric miao #ifdef CONFIG_PM 179c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 180c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 181c0165504Seric miao 1822eaa03b5SRafael J. Wysocki static int pxa_irq_suspend(void) 183c0165504Seric miao { 184a79a9ad9SHaojian Zhuang int i; 185f6fb7af4Seric miao 1860c1049dcSDaniel Mack for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) { 187a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 188a79a9ad9SHaojian Zhuang 189a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 190a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 191c0165504Seric miao } 192c70f5a60SEric Miao 193089d0362SDaniel Mack if (cpu_has_ipr) { 194c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 195089d0362SDaniel Mack saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); 196c70f5a60SEric Miao } 197c0165504Seric miao 198c0165504Seric miao return 0; 199c0165504Seric miao } 200c0165504Seric miao 2012eaa03b5SRafael J. Wysocki static void pxa_irq_resume(void) 202c0165504Seric miao { 203a79a9ad9SHaojian Zhuang int i; 204f6fb7af4Seric miao 2050c1049dcSDaniel Mack for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) { 206a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 207a79a9ad9SHaojian Zhuang 208a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 209a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 210a79a9ad9SHaojian Zhuang } 211a79a9ad9SHaojian Zhuang 212089d0362SDaniel Mack if (cpu_has_ipr) 213c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 214089d0362SDaniel Mack __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); 215c70f5a60SEric Miao 216089d0362SDaniel Mack __raw_writel(1, pxa_irq_base + ICCR); 217c0165504Seric miao } 218c0165504Seric miao #else 219c0165504Seric miao #define pxa_irq_suspend NULL 220c0165504Seric miao #define pxa_irq_resume NULL 221c0165504Seric miao #endif 222c0165504Seric miao 2232eaa03b5SRafael J. Wysocki struct syscore_ops pxa_irq_syscore_ops = { 224c0165504Seric miao .suspend = pxa_irq_suspend, 225c0165504Seric miao .resume = pxa_irq_resume, 226c0165504Seric miao }; 227089d0362SDaniel Mack 228089d0362SDaniel Mack #ifdef CONFIG_OF 229089d0362SDaniel Mack static const struct of_device_id intc_ids[] __initconst = { 230089d0362SDaniel Mack { .compatible = "marvell,pxa-intc", }, 231089d0362SDaniel Mack {} 232089d0362SDaniel Mack }; 233089d0362SDaniel Mack 234089d0362SDaniel Mack void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) 235089d0362SDaniel Mack { 236089d0362SDaniel Mack struct device_node *node; 237089d0362SDaniel Mack struct resource res; 238d6cf30caSRobert Jarzmik int ret; 239089d0362SDaniel Mack 240089d0362SDaniel Mack node = of_find_matching_node(NULL, intc_ids); 241089d0362SDaniel Mack if (!node) { 242089d0362SDaniel Mack pr_err("Failed to find interrupt controller in arch-pxa\n"); 243089d0362SDaniel Mack return; 244089d0362SDaniel Mack } 245089d0362SDaniel Mack 246089d0362SDaniel Mack ret = of_property_read_u32(node, "marvell,intc-nr-irqs", 247089d0362SDaniel Mack &pxa_internal_irq_nr); 248089d0362SDaniel Mack if (ret) { 249089d0362SDaniel Mack pr_err("Not found marvell,intc-nr-irqs property\n"); 250089d0362SDaniel Mack return; 251089d0362SDaniel Mack } 252089d0362SDaniel Mack 253089d0362SDaniel Mack ret = of_address_to_resource(node, 0, &res); 254089d0362SDaniel Mack if (ret < 0) { 255089d0362SDaniel Mack pr_err("No registers defined for node\n"); 256089d0362SDaniel Mack return; 257089d0362SDaniel Mack } 258089d0362SDaniel Mack pxa_irq_base = io_p2v(res.start); 259089d0362SDaniel Mack 260089d0362SDaniel Mack if (of_find_property(node, "marvell,intc-priority", NULL)) 261089d0362SDaniel Mack cpu_has_ipr = 1; 262089d0362SDaniel Mack 263089d0362SDaniel Mack ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0); 264089d0362SDaniel Mack if (ret < 0) { 265089d0362SDaniel Mack pr_err("Failed to allocate IRQ numbers\n"); 266089d0362SDaniel Mack return; 267089d0362SDaniel Mack } 268089d0362SDaniel Mack 269d6cf30caSRobert Jarzmik pxa_init_irq_common(node, pxa_internal_irq_nr, fn); 270089d0362SDaniel Mack } 271089d0362SDaniel Mack #endif /* CONFIG_OF */ 272