1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 41da177e4SLinus Torvalds * 5e3630db1Seric miao * Generic PXA IRQ handling 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Author: Nicolas Pitre 81da177e4SLinus Torvalds * Created: Jun 15, 2001 91da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 101da177e4SLinus Torvalds */ 11d6cf30caSRobert Jarzmik #include <linux/bitops.h> 121da177e4SLinus Torvalds #include <linux/init.h> 131da177e4SLinus Torvalds #include <linux/module.h> 141da177e4SLinus Torvalds #include <linux/interrupt.h> 152eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 16a79a9ad9SHaojian Zhuang #include <linux/io.h> 17a79a9ad9SHaojian Zhuang #include <linux/irq.h> 18089d0362SDaniel Mack #include <linux/of_address.h> 19089d0362SDaniel Mack #include <linux/of_irq.h> 201da177e4SLinus Torvalds 215a567d78SJamie Iles #include <asm/exception.h> 225a567d78SJamie Iles 23a09e64fbSRussell King #include <mach/hardware.h> 24a79a9ad9SHaojian Zhuang #include <mach/irqs.h> 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds #include "generic.h" 271da177e4SLinus Torvalds 28a79a9ad9SHaojian Zhuang #define ICIP (0x000) 29a79a9ad9SHaojian Zhuang #define ICMR (0x004) 30a79a9ad9SHaojian Zhuang #define ICLR (0x008) 31a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 32a79a9ad9SHaojian Zhuang #define ICPR (0x010) 33a79a9ad9SHaojian Zhuang #define ICCR (0x014) 34a79a9ad9SHaojian Zhuang #define ICHP (0x018) 35a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 36a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 37a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 38a551e4f7SEric Miao #define ICHP_VAL_IRQ (1 << 31) 39a551e4f7SEric Miao #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 40a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 41a79a9ad9SHaojian Zhuang 42a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 431da177e4SLinus Torvalds 441da177e4SLinus Torvalds /* 451da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 461da177e4SLinus Torvalds */ 471da177e4SLinus Torvalds 48089d0362SDaniel Mack static void __iomem *pxa_irq_base; 49f6fb7af4Seric miao static int pxa_internal_irq_nr; 50089d0362SDaniel Mack static bool cpu_has_ipr; 51d6cf30caSRobert Jarzmik static struct irq_domain *pxa_irq_domain; 52bb71bdd3SHaojian Zhuang 53a1015a15SEric Miao static inline void __iomem *irq_base(int i) 54a1015a15SEric Miao { 55089d0362SDaniel Mack static unsigned long phys_base_offset[] = { 56089d0362SDaniel Mack 0x0, 57089d0362SDaniel Mack 0x9c, 58089d0362SDaniel Mack 0x130, 59a1015a15SEric Miao }; 60a1015a15SEric Miao 61089d0362SDaniel Mack return pxa_irq_base + phys_base_offset[i]; 62a1015a15SEric Miao } 63a1015a15SEric Miao 645d284e35SEric Miao void pxa_mask_irq(struct irq_data *d) 651da177e4SLinus Torvalds { 66a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 67d6cf30caSRobert Jarzmik irq_hw_number_t irq = irqd_to_hwirq(d); 68a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 69a79a9ad9SHaojian Zhuang 70d6cf30caSRobert Jarzmik icmr &= ~BIT(irq & 0x1f); 71a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 721da177e4SLinus Torvalds } 731da177e4SLinus Torvalds 745d284e35SEric Miao void pxa_unmask_irq(struct irq_data *d) 751da177e4SLinus Torvalds { 76a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 77d6cf30caSRobert Jarzmik irq_hw_number_t irq = irqd_to_hwirq(d); 78a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 79a79a9ad9SHaojian Zhuang 80d6cf30caSRobert Jarzmik icmr |= BIT(irq & 0x1f); 81a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 821da177e4SLinus Torvalds } 831da177e4SLinus Torvalds 84f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 8538c677cbSDavid Brownell .name = "SC", 86a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 87a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 88a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 891da177e4SLinus Torvalds }; 901da177e4SLinus Torvalds 91a551e4f7SEric Miao asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 92a551e4f7SEric Miao { 93a551e4f7SEric Miao uint32_t icip, icmr, mask; 94a551e4f7SEric Miao 95a551e4f7SEric Miao do { 96089d0362SDaniel Mack icip = __raw_readl(pxa_irq_base + ICIP); 97089d0362SDaniel Mack icmr = __raw_readl(pxa_irq_base + ICMR); 98a551e4f7SEric Miao mask = icip & icmr; 99a551e4f7SEric Miao 100a551e4f7SEric Miao if (mask == 0) 101a551e4f7SEric Miao break; 102a551e4f7SEric Miao 103a551e4f7SEric Miao handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 104a551e4f7SEric Miao } while (1); 105a551e4f7SEric Miao } 106a551e4f7SEric Miao 107a551e4f7SEric Miao asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 108a551e4f7SEric Miao { 109a551e4f7SEric Miao uint32_t ichp; 110a551e4f7SEric Miao 111a551e4f7SEric Miao do { 112a551e4f7SEric Miao __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 113a551e4f7SEric Miao 114a551e4f7SEric Miao if ((ichp & ICHP_VAL_IRQ) == 0) 115a551e4f7SEric Miao break; 116a551e4f7SEric Miao 117a551e4f7SEric Miao handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 118a551e4f7SEric Miao } while (1); 119a551e4f7SEric Miao } 120a551e4f7SEric Miao 121d6cf30caSRobert Jarzmik static int pxa_irq_map(struct irq_domain *h, unsigned int virq, 122d6cf30caSRobert Jarzmik irq_hw_number_t hw) 12353665a50SEric Miao { 124d6cf30caSRobert Jarzmik void __iomem *base = irq_base(hw / 32); 12553665a50SEric Miao 126d6cf30caSRobert Jarzmik /* initialize interrupt priority */ 127d6cf30caSRobert Jarzmik if (cpu_has_ipr) 128d6cf30caSRobert Jarzmik __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); 129d6cf30caSRobert Jarzmik 130d6cf30caSRobert Jarzmik irq_set_chip_and_handler(virq, &pxa_internal_irq_chip, 131d6cf30caSRobert Jarzmik handle_level_irq); 132d6cf30caSRobert Jarzmik irq_set_chip_data(virq, base); 133d6cf30caSRobert Jarzmik 134d6cf30caSRobert Jarzmik return 0; 135d6cf30caSRobert Jarzmik } 136d6cf30caSRobert Jarzmik 13764227114SKrzysztof Kozlowski static const struct irq_domain_ops pxa_irq_ops = { 138d6cf30caSRobert Jarzmik .map = pxa_irq_map, 139d6cf30caSRobert Jarzmik .xlate = irq_domain_xlate_onecell, 140d6cf30caSRobert Jarzmik }; 141d6cf30caSRobert Jarzmik 142d6cf30caSRobert Jarzmik static __init void 143d6cf30caSRobert Jarzmik pxa_init_irq_common(struct device_node *node, int irq_nr, 144d6cf30caSRobert Jarzmik int (*fn)(struct irq_data *, unsigned int)) 145d6cf30caSRobert Jarzmik { 146d6cf30caSRobert Jarzmik int n; 147c482ae4dSHaojian Zhuang 148f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 149d6cf30caSRobert Jarzmik pxa_irq_domain = irq_domain_add_legacy(node, irq_nr, 150d6cf30caSRobert Jarzmik PXA_IRQ(0), 0, 151d6cf30caSRobert Jarzmik &pxa_irq_ops, NULL); 152d6cf30caSRobert Jarzmik if (!pxa_irq_domain) 153d6cf30caSRobert Jarzmik panic("Unable to add PXA IRQ domain\n"); 154d6cf30caSRobert Jarzmik irq_set_default_host(pxa_irq_domain); 15553665a50SEric Miao 156a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 1571b624fb6SMarek Vasut void __iomem *base = irq_base(n >> 5); 15853665a50SEric Miao 159a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 160a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 16153665a50SEric Miao } 162a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 163a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 16453665a50SEric Miao 165a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 166c95530c7Seric miao } 167c0165504Seric miao 168d6cf30caSRobert Jarzmik void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 169d6cf30caSRobert Jarzmik { 170d6cf30caSRobert Jarzmik BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 171d6cf30caSRobert Jarzmik 172d6cf30caSRobert Jarzmik pxa_irq_base = io_p2v(0x40d00000); 173d6cf30caSRobert Jarzmik cpu_has_ipr = !cpu_is_pxa25x(); 174d6cf30caSRobert Jarzmik pxa_init_irq_common(NULL, irq_nr, fn); 175d6cf30caSRobert Jarzmik } 176d6cf30caSRobert Jarzmik 177c0165504Seric miao #ifdef CONFIG_PM 178c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 179c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 180c0165504Seric miao 1812eaa03b5SRafael J. Wysocki static int pxa_irq_suspend(void) 182c0165504Seric miao { 183a79a9ad9SHaojian Zhuang int i; 184f6fb7af4Seric miao 1850c1049dcSDaniel Mack for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) { 186a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 187a79a9ad9SHaojian Zhuang 188a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 189a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 190c0165504Seric miao } 191c70f5a60SEric Miao 192089d0362SDaniel Mack if (cpu_has_ipr) { 193c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 194089d0362SDaniel Mack saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); 195c70f5a60SEric Miao } 196c0165504Seric miao 197c0165504Seric miao return 0; 198c0165504Seric miao } 199c0165504Seric miao 2002eaa03b5SRafael J. Wysocki static void pxa_irq_resume(void) 201c0165504Seric miao { 202a79a9ad9SHaojian Zhuang int i; 203f6fb7af4Seric miao 2040c1049dcSDaniel Mack for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) { 205a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 206a79a9ad9SHaojian Zhuang 207a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 208a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 209a79a9ad9SHaojian Zhuang } 210a79a9ad9SHaojian Zhuang 211089d0362SDaniel Mack if (cpu_has_ipr) 212c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 213089d0362SDaniel Mack __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); 214c70f5a60SEric Miao 215089d0362SDaniel Mack __raw_writel(1, pxa_irq_base + ICCR); 216c0165504Seric miao } 217c0165504Seric miao #else 218c0165504Seric miao #define pxa_irq_suspend NULL 219c0165504Seric miao #define pxa_irq_resume NULL 220c0165504Seric miao #endif 221c0165504Seric miao 2222eaa03b5SRafael J. Wysocki struct syscore_ops pxa_irq_syscore_ops = { 223c0165504Seric miao .suspend = pxa_irq_suspend, 224c0165504Seric miao .resume = pxa_irq_resume, 225c0165504Seric miao }; 226089d0362SDaniel Mack 227089d0362SDaniel Mack #ifdef CONFIG_OF 228089d0362SDaniel Mack static const struct of_device_id intc_ids[] __initconst = { 229089d0362SDaniel Mack { .compatible = "marvell,pxa-intc", }, 230089d0362SDaniel Mack {} 231089d0362SDaniel Mack }; 232089d0362SDaniel Mack 233089d0362SDaniel Mack void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) 234089d0362SDaniel Mack { 235089d0362SDaniel Mack struct device_node *node; 236089d0362SDaniel Mack struct resource res; 237d6cf30caSRobert Jarzmik int ret; 238089d0362SDaniel Mack 239089d0362SDaniel Mack node = of_find_matching_node(NULL, intc_ids); 240089d0362SDaniel Mack if (!node) { 241089d0362SDaniel Mack pr_err("Failed to find interrupt controller in arch-pxa\n"); 242089d0362SDaniel Mack return; 243089d0362SDaniel Mack } 244089d0362SDaniel Mack 245089d0362SDaniel Mack ret = of_property_read_u32(node, "marvell,intc-nr-irqs", 246089d0362SDaniel Mack &pxa_internal_irq_nr); 247089d0362SDaniel Mack if (ret) { 248089d0362SDaniel Mack pr_err("Not found marvell,intc-nr-irqs property\n"); 249089d0362SDaniel Mack return; 250089d0362SDaniel Mack } 251089d0362SDaniel Mack 252089d0362SDaniel Mack ret = of_address_to_resource(node, 0, &res); 253089d0362SDaniel Mack if (ret < 0) { 254089d0362SDaniel Mack pr_err("No registers defined for node\n"); 255089d0362SDaniel Mack return; 256089d0362SDaniel Mack } 257089d0362SDaniel Mack pxa_irq_base = io_p2v(res.start); 258089d0362SDaniel Mack 259089d0362SDaniel Mack if (of_find_property(node, "marvell,intc-priority", NULL)) 260089d0362SDaniel Mack cpu_has_ipr = 1; 261089d0362SDaniel Mack 262089d0362SDaniel Mack ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0); 263089d0362SDaniel Mack if (ret < 0) { 264089d0362SDaniel Mack pr_err("Failed to allocate IRQ numbers\n"); 265089d0362SDaniel Mack return; 266089d0362SDaniel Mack } 267089d0362SDaniel Mack 268d6cf30caSRobert Jarzmik pxa_init_irq_common(node, pxa_internal_irq_nr, fn); 269089d0362SDaniel Mack } 270089d0362SDaniel Mack #endif /* CONFIG_OF */ 271