11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds #include <linux/init.h> 161da177e4SLinus Torvalds #include <linux/module.h> 171da177e4SLinus Torvalds #include <linux/interrupt.h> 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds #include <asm/hardware.h> 201da177e4SLinus Torvalds #include <asm/irq.h> 211da177e4SLinus Torvalds #include <asm/mach/irq.h> 221da177e4SLinus Torvalds #include <asm/arch/pxa-regs.h> 231da177e4SLinus Torvalds 241da177e4SLinus Torvalds #include "generic.h" 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds 271da177e4SLinus Torvalds /* 281da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 291da177e4SLinus Torvalds */ 301da177e4SLinus Torvalds 311da177e4SLinus Torvalds static void pxa_mask_low_irq(unsigned int irq) 321da177e4SLinus Torvalds { 33486c9551SEric Miao ICMR &= ~(1 << irq); 341da177e4SLinus Torvalds } 351da177e4SLinus Torvalds 361da177e4SLinus Torvalds static void pxa_unmask_low_irq(unsigned int irq) 371da177e4SLinus Torvalds { 38486c9551SEric Miao ICMR |= (1 << irq); 391da177e4SLinus Torvalds } 401da177e4SLinus Torvalds 414fe4a2bfSPhilipp Zabel static int pxa_set_wake(unsigned int irq, unsigned int on) 424fe4a2bfSPhilipp Zabel { 434fe4a2bfSPhilipp Zabel u32 mask; 444fe4a2bfSPhilipp Zabel 454fe4a2bfSPhilipp Zabel switch (irq) { 464fe4a2bfSPhilipp Zabel case IRQ_RTCAlrm: 474fe4a2bfSPhilipp Zabel mask = PWER_RTC; 484fe4a2bfSPhilipp Zabel break; 494fe4a2bfSPhilipp Zabel #ifdef CONFIG_PXA27x 504fe4a2bfSPhilipp Zabel /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */ 514fe4a2bfSPhilipp Zabel #endif 524fe4a2bfSPhilipp Zabel default: 534fe4a2bfSPhilipp Zabel return -EINVAL; 544fe4a2bfSPhilipp Zabel } 554fe4a2bfSPhilipp Zabel if (on) 564fe4a2bfSPhilipp Zabel PWER |= mask; 574fe4a2bfSPhilipp Zabel else 584fe4a2bfSPhilipp Zabel PWER &= ~mask; 594fe4a2bfSPhilipp Zabel return 0; 604fe4a2bfSPhilipp Zabel } 614fe4a2bfSPhilipp Zabel 6238c677cbSDavid Brownell static struct irq_chip pxa_internal_chip_low = { 6338c677cbSDavid Brownell .name = "SC", 641da177e4SLinus Torvalds .ack = pxa_mask_low_irq, 651da177e4SLinus Torvalds .mask = pxa_mask_low_irq, 661da177e4SLinus Torvalds .unmask = pxa_unmask_low_irq, 674fe4a2bfSPhilipp Zabel .set_wake = pxa_set_wake, 681da177e4SLinus Torvalds }; 691da177e4SLinus Torvalds 70c08b7b3eSEric Miao #ifdef CONFIG_PXA27x 711da177e4SLinus Torvalds 721da177e4SLinus Torvalds /* 731da177e4SLinus Torvalds * This is for the second set of internal IRQs as found on the PXA27x. 741da177e4SLinus Torvalds */ 751da177e4SLinus Torvalds 761da177e4SLinus Torvalds static void pxa_mask_high_irq(unsigned int irq) 771da177e4SLinus Torvalds { 78486c9551SEric Miao ICMR2 &= ~(1 << (irq - 32)); 791da177e4SLinus Torvalds } 801da177e4SLinus Torvalds 811da177e4SLinus Torvalds static void pxa_unmask_high_irq(unsigned int irq) 821da177e4SLinus Torvalds { 83486c9551SEric Miao ICMR2 |= (1 << (irq - 32)); 841da177e4SLinus Torvalds } 851da177e4SLinus Torvalds 8638c677cbSDavid Brownell static struct irq_chip pxa_internal_chip_high = { 8738c677cbSDavid Brownell .name = "SC-hi", 881da177e4SLinus Torvalds .ack = pxa_mask_high_irq, 891da177e4SLinus Torvalds .mask = pxa_mask_high_irq, 901da177e4SLinus Torvalds .unmask = pxa_unmask_high_irq, 911da177e4SLinus Torvalds }; 921da177e4SLinus Torvalds 93c08b7b3eSEric Miao void __init pxa_init_irq_high(void) 94c08b7b3eSEric Miao { 95c08b7b3eSEric Miao int irq; 96c08b7b3eSEric Miao 97c08b7b3eSEric Miao ICMR2 = 0; 98c08b7b3eSEric Miao ICLR2 = 0; 99c08b7b3eSEric Miao 100c08b7b3eSEric Miao for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { 101c08b7b3eSEric Miao set_irq_chip(irq, &pxa_internal_chip_high); 102c08b7b3eSEric Miao set_irq_handler(irq, handle_level_irq); 103c08b7b3eSEric Miao set_irq_flags(irq, IRQF_VALID); 104c08b7b3eSEric Miao } 105c08b7b3eSEric Miao } 1061da177e4SLinus Torvalds #endif 1071da177e4SLinus Torvalds 1084fe4a2bfSPhilipp Zabel /* Note that if an input/irq line ever gets changed to an output during 1094fe4a2bfSPhilipp Zabel * suspend, the relevant PWER, PRER, and PFER bits should be cleared. 1104fe4a2bfSPhilipp Zabel */ 1114fe4a2bfSPhilipp Zabel #ifdef CONFIG_PXA27x 1124fe4a2bfSPhilipp Zabel 1134fe4a2bfSPhilipp Zabel /* PXA27x: Various gpios can issue wakeup events. This logic only 1144fe4a2bfSPhilipp Zabel * handles the simple cases, not the WEMUX2 and WEMUX3 options 1154fe4a2bfSPhilipp Zabel */ 1164fe4a2bfSPhilipp Zabel #define PXA27x_GPIO_NOWAKE_MASK \ 1174fe4a2bfSPhilipp Zabel ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) 1184fe4a2bfSPhilipp Zabel #define WAKEMASK(gpio) \ 1194fe4a2bfSPhilipp Zabel (((gpio) <= 15) \ 1204fe4a2bfSPhilipp Zabel ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ 1214fe4a2bfSPhilipp Zabel : ((gpio == 35) ? (1 << 24) : 0)) 1224fe4a2bfSPhilipp Zabel #else 1234fe4a2bfSPhilipp Zabel 1244fe4a2bfSPhilipp Zabel /* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */ 1254fe4a2bfSPhilipp Zabel #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0) 1264fe4a2bfSPhilipp Zabel #endif 1274fe4a2bfSPhilipp Zabel 1281da177e4SLinus Torvalds /* 1291da177e4SLinus Torvalds * PXA GPIO edge detection for IRQs: 1301da177e4SLinus Torvalds * IRQs are generated on Falling-Edge, Rising-Edge, or both. 1311da177e4SLinus Torvalds * Use this instead of directly setting GRER/GFER. 1321da177e4SLinus Torvalds */ 1331da177e4SLinus Torvalds 1341da177e4SLinus Torvalds static long GPIO_IRQ_rising_edge[4]; 1351da177e4SLinus Torvalds static long GPIO_IRQ_falling_edge[4]; 1361da177e4SLinus Torvalds static long GPIO_IRQ_mask[4]; 1371da177e4SLinus Torvalds 1381da177e4SLinus Torvalds static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 1391da177e4SLinus Torvalds { 1401da177e4SLinus Torvalds int gpio, idx; 1414fe4a2bfSPhilipp Zabel u32 mask; 1421da177e4SLinus Torvalds 1431da177e4SLinus Torvalds gpio = IRQ_TO_GPIO(irq); 1441da177e4SLinus Torvalds idx = gpio >> 5; 1454fe4a2bfSPhilipp Zabel mask = WAKEMASK(gpio); 1461da177e4SLinus Torvalds 1471da177e4SLinus Torvalds if (type == IRQT_PROBE) { 1481da177e4SLinus Torvalds /* Don't mess with enabled GPIOs using preconfigured edges or 149e033108bSGuennadi Liakhovetski GPIOs set to alternate function or to output during probe */ 150e033108bSGuennadi Liakhovetski if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & 1511da177e4SLinus Torvalds GPIO_bit(gpio)) 1521da177e4SLinus Torvalds return 0; 1531da177e4SLinus Torvalds if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) 1541da177e4SLinus Torvalds return 0; 1551da177e4SLinus Torvalds type = __IRQT_RISEDGE | __IRQT_FALEDGE; 1561da177e4SLinus Torvalds } 1571da177e4SLinus Torvalds 1581da177e4SLinus Torvalds /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ 1591da177e4SLinus Torvalds 1601da177e4SLinus Torvalds pxa_gpio_mode(gpio | GPIO_IN); 1611da177e4SLinus Torvalds 1621da177e4SLinus Torvalds if (type & __IRQT_RISEDGE) { 1631da177e4SLinus Torvalds /* printk("rising "); */ 1641da177e4SLinus Torvalds __set_bit (gpio, GPIO_IRQ_rising_edge); 1654fe4a2bfSPhilipp Zabel PRER |= mask; 1664fe4a2bfSPhilipp Zabel } else { 1671da177e4SLinus Torvalds __clear_bit (gpio, GPIO_IRQ_rising_edge); 1684fe4a2bfSPhilipp Zabel PRER &= ~mask; 1694fe4a2bfSPhilipp Zabel } 1701da177e4SLinus Torvalds 1711da177e4SLinus Torvalds if (type & __IRQT_FALEDGE) { 1721da177e4SLinus Torvalds /* printk("falling "); */ 1731da177e4SLinus Torvalds __set_bit (gpio, GPIO_IRQ_falling_edge); 1744fe4a2bfSPhilipp Zabel PFER |= mask; 1754fe4a2bfSPhilipp Zabel } else { 1761da177e4SLinus Torvalds __clear_bit (gpio, GPIO_IRQ_falling_edge); 1774fe4a2bfSPhilipp Zabel PFER &= ~mask; 1784fe4a2bfSPhilipp Zabel } 1791da177e4SLinus Torvalds 1801da177e4SLinus Torvalds /* printk("edges\n"); */ 1811da177e4SLinus Torvalds 1821da177e4SLinus Torvalds GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 1831da177e4SLinus Torvalds GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 1841da177e4SLinus Torvalds return 0; 1851da177e4SLinus Torvalds } 1861da177e4SLinus Torvalds 1871da177e4SLinus Torvalds /* 1881da177e4SLinus Torvalds * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. 1891da177e4SLinus Torvalds */ 1901da177e4SLinus Torvalds 1911da177e4SLinus Torvalds static void pxa_ack_low_gpio(unsigned int irq) 1921da177e4SLinus Torvalds { 1931da177e4SLinus Torvalds GEDR0 = (1 << (irq - IRQ_GPIO0)); 1941da177e4SLinus Torvalds } 1951da177e4SLinus Torvalds 1964fe4a2bfSPhilipp Zabel static int pxa_set_gpio_wake(unsigned int irq, unsigned int on) 1974fe4a2bfSPhilipp Zabel { 1984fe4a2bfSPhilipp Zabel int gpio = IRQ_TO_GPIO(irq); 1994fe4a2bfSPhilipp Zabel u32 mask = WAKEMASK(gpio); 2004fe4a2bfSPhilipp Zabel 2014fe4a2bfSPhilipp Zabel if (!mask) 2024fe4a2bfSPhilipp Zabel return -EINVAL; 2034fe4a2bfSPhilipp Zabel 2044fe4a2bfSPhilipp Zabel if (on) 2054fe4a2bfSPhilipp Zabel PWER |= mask; 2064fe4a2bfSPhilipp Zabel else 2074fe4a2bfSPhilipp Zabel PWER &= ~mask; 2084fe4a2bfSPhilipp Zabel return 0; 2094fe4a2bfSPhilipp Zabel } 2104fe4a2bfSPhilipp Zabel 2114fe4a2bfSPhilipp Zabel 21238c677cbSDavid Brownell static struct irq_chip pxa_low_gpio_chip = { 21338c677cbSDavid Brownell .name = "GPIO-l", 2141da177e4SLinus Torvalds .ack = pxa_ack_low_gpio, 2151da177e4SLinus Torvalds .mask = pxa_mask_low_irq, 2161da177e4SLinus Torvalds .unmask = pxa_unmask_low_irq, 2177801907bSRussell King .set_type = pxa_gpio_irq_type, 2184fe4a2bfSPhilipp Zabel .set_wake = pxa_set_gpio_wake, 2191da177e4SLinus Torvalds }; 2201da177e4SLinus Torvalds 2211da177e4SLinus Torvalds /* 2221da177e4SLinus Torvalds * Demux handler for GPIO>=2 edge detect interrupts 2231da177e4SLinus Torvalds */ 2241da177e4SLinus Torvalds 22510dd5ce2SRussell King static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 2261da177e4SLinus Torvalds { 2271da177e4SLinus Torvalds unsigned int mask; 2281da177e4SLinus Torvalds int loop; 2291da177e4SLinus Torvalds 2301da177e4SLinus Torvalds do { 2311da177e4SLinus Torvalds loop = 0; 2321da177e4SLinus Torvalds 2331da177e4SLinus Torvalds mask = GEDR0 & ~3; 2341da177e4SLinus Torvalds if (mask) { 2351da177e4SLinus Torvalds GEDR0 = mask; 2361da177e4SLinus Torvalds irq = IRQ_GPIO(2); 2371da177e4SLinus Torvalds desc = irq_desc + irq; 2381da177e4SLinus Torvalds mask >>= 2; 2391da177e4SLinus Torvalds do { 2401da177e4SLinus Torvalds if (mask & 1) 2410cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2421da177e4SLinus Torvalds irq++; 2431da177e4SLinus Torvalds desc++; 2441da177e4SLinus Torvalds mask >>= 1; 2451da177e4SLinus Torvalds } while (mask); 2461da177e4SLinus Torvalds loop = 1; 2471da177e4SLinus Torvalds } 2481da177e4SLinus Torvalds 2491da177e4SLinus Torvalds mask = GEDR1; 2501da177e4SLinus Torvalds if (mask) { 2511da177e4SLinus Torvalds GEDR1 = mask; 2521da177e4SLinus Torvalds irq = IRQ_GPIO(32); 2531da177e4SLinus Torvalds desc = irq_desc + irq; 2541da177e4SLinus Torvalds do { 2551da177e4SLinus Torvalds if (mask & 1) 2560cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2571da177e4SLinus Torvalds irq++; 2581da177e4SLinus Torvalds desc++; 2591da177e4SLinus Torvalds mask >>= 1; 2601da177e4SLinus Torvalds } while (mask); 2611da177e4SLinus Torvalds loop = 1; 2621da177e4SLinus Torvalds } 2631da177e4SLinus Torvalds 2641da177e4SLinus Torvalds mask = GEDR2; 2651da177e4SLinus Torvalds if (mask) { 2661da177e4SLinus Torvalds GEDR2 = mask; 2671da177e4SLinus Torvalds irq = IRQ_GPIO(64); 2681da177e4SLinus Torvalds desc = irq_desc + irq; 2691da177e4SLinus Torvalds do { 2701da177e4SLinus Torvalds if (mask & 1) 2710cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2721da177e4SLinus Torvalds irq++; 2731da177e4SLinus Torvalds desc++; 2741da177e4SLinus Torvalds mask >>= 1; 2751da177e4SLinus Torvalds } while (mask); 2761da177e4SLinus Torvalds loop = 1; 2771da177e4SLinus Torvalds } 2781da177e4SLinus Torvalds 2791da177e4SLinus Torvalds #if PXA_LAST_GPIO >= 96 2801da177e4SLinus Torvalds mask = GEDR3; 2811da177e4SLinus Torvalds if (mask) { 2821da177e4SLinus Torvalds GEDR3 = mask; 2831da177e4SLinus Torvalds irq = IRQ_GPIO(96); 2841da177e4SLinus Torvalds desc = irq_desc + irq; 2851da177e4SLinus Torvalds do { 2861da177e4SLinus Torvalds if (mask & 1) 2870cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2881da177e4SLinus Torvalds irq++; 2891da177e4SLinus Torvalds desc++; 2901da177e4SLinus Torvalds mask >>= 1; 2911da177e4SLinus Torvalds } while (mask); 2921da177e4SLinus Torvalds loop = 1; 2931da177e4SLinus Torvalds } 2941da177e4SLinus Torvalds #endif 2951da177e4SLinus Torvalds } while (loop); 2961da177e4SLinus Torvalds } 2971da177e4SLinus Torvalds 2981da177e4SLinus Torvalds static void pxa_ack_muxed_gpio(unsigned int irq) 2991da177e4SLinus Torvalds { 3001da177e4SLinus Torvalds int gpio = irq - IRQ_GPIO(2) + 2; 3011da177e4SLinus Torvalds GEDR(gpio) = GPIO_bit(gpio); 3021da177e4SLinus Torvalds } 3031da177e4SLinus Torvalds 3041da177e4SLinus Torvalds static void pxa_mask_muxed_gpio(unsigned int irq) 3051da177e4SLinus Torvalds { 3061da177e4SLinus Torvalds int gpio = irq - IRQ_GPIO(2) + 2; 3071da177e4SLinus Torvalds __clear_bit(gpio, GPIO_IRQ_mask); 3081da177e4SLinus Torvalds GRER(gpio) &= ~GPIO_bit(gpio); 3091da177e4SLinus Torvalds GFER(gpio) &= ~GPIO_bit(gpio); 3101da177e4SLinus Torvalds } 3111da177e4SLinus Torvalds 3121da177e4SLinus Torvalds static void pxa_unmask_muxed_gpio(unsigned int irq) 3131da177e4SLinus Torvalds { 3141da177e4SLinus Torvalds int gpio = irq - IRQ_GPIO(2) + 2; 3151da177e4SLinus Torvalds int idx = gpio >> 5; 3161da177e4SLinus Torvalds __set_bit(gpio, GPIO_IRQ_mask); 3171da177e4SLinus Torvalds GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 3181da177e4SLinus Torvalds GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 3191da177e4SLinus Torvalds } 3201da177e4SLinus Torvalds 32138c677cbSDavid Brownell static struct irq_chip pxa_muxed_gpio_chip = { 32238c677cbSDavid Brownell .name = "GPIO", 3231da177e4SLinus Torvalds .ack = pxa_ack_muxed_gpio, 3241da177e4SLinus Torvalds .mask = pxa_mask_muxed_gpio, 3251da177e4SLinus Torvalds .unmask = pxa_unmask_muxed_gpio, 3267801907bSRussell King .set_type = pxa_gpio_irq_type, 3274fe4a2bfSPhilipp Zabel .set_wake = pxa_set_gpio_wake, 3281da177e4SLinus Torvalds }; 3291da177e4SLinus Torvalds 3301da177e4SLinus Torvalds void __init pxa_init_irq(void) 3311da177e4SLinus Torvalds { 3321da177e4SLinus Torvalds int irq; 3331da177e4SLinus Torvalds 3341da177e4SLinus Torvalds /* disable all IRQs */ 3351da177e4SLinus Torvalds ICMR = 0; 3361da177e4SLinus Torvalds 3371da177e4SLinus Torvalds /* all IRQs are IRQ, not FIQ */ 3381da177e4SLinus Torvalds ICLR = 0; 3391da177e4SLinus Torvalds 3401da177e4SLinus Torvalds /* clear all GPIO edge detects */ 3411da177e4SLinus Torvalds GFER0 = 0; 3421da177e4SLinus Torvalds GFER1 = 0; 3431da177e4SLinus Torvalds GFER2 = 0; 3441da177e4SLinus Torvalds GRER0 = 0; 3451da177e4SLinus Torvalds GRER1 = 0; 3461da177e4SLinus Torvalds GRER2 = 0; 3471da177e4SLinus Torvalds GEDR0 = GEDR0; 3481da177e4SLinus Torvalds GEDR1 = GEDR1; 3491da177e4SLinus Torvalds GEDR2 = GEDR2; 3501da177e4SLinus Torvalds 3511da177e4SLinus Torvalds #ifdef CONFIG_PXA27x 3521da177e4SLinus Torvalds /* And similarly for the extra regs on the PXA27x */ 3531da177e4SLinus Torvalds GFER3 = 0; 3541da177e4SLinus Torvalds GRER3 = 0; 3551da177e4SLinus Torvalds GEDR3 = GEDR3; 3561da177e4SLinus Torvalds #endif 3571da177e4SLinus Torvalds 3581da177e4SLinus Torvalds /* only unmasked interrupts kick us out of idle */ 3591da177e4SLinus Torvalds ICCR = 1; 3601da177e4SLinus Torvalds 3611da177e4SLinus Torvalds /* GPIO 0 and 1 must have their mask bit always set */ 3621da177e4SLinus Torvalds GPIO_IRQ_mask[0] = 3; 3631da177e4SLinus Torvalds 364486c9551SEric Miao for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { 3651da177e4SLinus Torvalds set_irq_chip(irq, &pxa_internal_chip_low); 36610dd5ce2SRussell King set_irq_handler(irq, handle_level_irq); 3671da177e4SLinus Torvalds set_irq_flags(irq, IRQF_VALID); 3681da177e4SLinus Torvalds } 3691da177e4SLinus Torvalds 370c08b7b3eSEric Miao #ifdef CONFIG_PXA27x 371c08b7b3eSEric Miao pxa_init_irq_high(); 3721da177e4SLinus Torvalds #endif 3731da177e4SLinus Torvalds 3741da177e4SLinus Torvalds for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 3751da177e4SLinus Torvalds set_irq_chip(irq, &pxa_low_gpio_chip); 37610dd5ce2SRussell King set_irq_handler(irq, handle_edge_irq); 3771da177e4SLinus Torvalds set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 3781da177e4SLinus Torvalds } 3791da177e4SLinus Torvalds 3801da177e4SLinus Torvalds for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { 3811da177e4SLinus Torvalds set_irq_chip(irq, &pxa_muxed_gpio_chip); 38210dd5ce2SRussell King set_irq_handler(irq, handle_edge_irq); 3831da177e4SLinus Torvalds set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 3841da177e4SLinus Torvalds } 3851da177e4SLinus Torvalds 3861da177e4SLinus Torvalds /* Install handler for GPIO>=2 edge detect interrupts */ 3871da177e4SLinus Torvalds set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 3881da177e4SLinus Torvalds set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 3891da177e4SLinus Torvalds } 390