11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 4e3630db1Seric miao * Generic PXA IRQ handling 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds #include <linux/init.h> 161da177e4SLinus Torvalds #include <linux/module.h> 171da177e4SLinus Torvalds #include <linux/interrupt.h> 18c0165504Seric miao #include <linux/sysdev.h> 19a79a9ad9SHaojian Zhuang #include <linux/io.h> 20a79a9ad9SHaojian Zhuang #include <linux/irq.h> 211da177e4SLinus Torvalds 22a09e64fbSRussell King #include <mach/hardware.h> 23a79a9ad9SHaojian Zhuang #include <mach/irqs.h> 24a58fbcd8SEric Miao #include <mach/gpio.h> 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds #include "generic.h" 271da177e4SLinus Torvalds 28a79a9ad9SHaojian Zhuang #define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) 29c482ae4dSHaojian Zhuang 30a79a9ad9SHaojian Zhuang #define ICIP (0x000) 31a79a9ad9SHaojian Zhuang #define ICMR (0x004) 32a79a9ad9SHaojian Zhuang #define ICLR (0x008) 33a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 34a79a9ad9SHaojian Zhuang #define ICPR (0x010) 35a79a9ad9SHaojian Zhuang #define ICCR (0x014) 36a79a9ad9SHaojian Zhuang #define ICHP (0x018) 37a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 38a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 39a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 40a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 41f6fb7af4Seric miao #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 42a79a9ad9SHaojian Zhuang 43a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 441da177e4SLinus Torvalds 451da177e4SLinus Torvalds /* 461da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 471da177e4SLinus Torvalds */ 481da177e4SLinus Torvalds 49f6fb7af4Seric miao static int pxa_internal_irq_nr; 50f6fb7af4Seric miao 51bb71bdd3SHaojian Zhuang static inline int cpu_has_ipr(void) 52bb71bdd3SHaojian Zhuang { 53bb71bdd3SHaojian Zhuang return !cpu_is_pxa25x(); 54bb71bdd3SHaojian Zhuang } 55bb71bdd3SHaojian Zhuang 56a1015a15SEric Miao static inline void __iomem *irq_base(int i) 57a1015a15SEric Miao { 58a1015a15SEric Miao static unsigned long phys_base[] = { 59a1015a15SEric Miao 0x40d00000, 60a1015a15SEric Miao 0x40d0009c, 61a1015a15SEric Miao 0x40d00130, 62a1015a15SEric Miao }; 63a1015a15SEric Miao 64a1015a15SEric Miao return (void __iomem *)io_p2v(phys_base[i]); 65a1015a15SEric Miao } 66a1015a15SEric Miao 67a3f4c927SLennert Buytenhek static void pxa_mask_irq(struct irq_data *d) 681da177e4SLinus Torvalds { 69a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 70a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 71a79a9ad9SHaojian Zhuang 72a3f4c927SLennert Buytenhek icmr &= ~(1 << IRQ_BIT(d->irq)); 73a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 741da177e4SLinus Torvalds } 751da177e4SLinus Torvalds 76a3f4c927SLennert Buytenhek static void pxa_unmask_irq(struct irq_data *d) 771da177e4SLinus Torvalds { 78a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 79a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 80a79a9ad9SHaojian Zhuang 81a3f4c927SLennert Buytenhek icmr |= 1 << IRQ_BIT(d->irq); 82a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 831da177e4SLinus Torvalds } 841da177e4SLinus Torvalds 85f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 8638c677cbSDavid Brownell .name = "SC", 87a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 88a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 89a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 901da177e4SLinus Torvalds }; 911da177e4SLinus Torvalds 92a58fbcd8SEric Miao /* 93a58fbcd8SEric Miao * GPIO IRQs for GPIO 0 and 1 94a58fbcd8SEric Miao */ 95a3f4c927SLennert Buytenhek static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) 96a58fbcd8SEric Miao { 97a3f4c927SLennert Buytenhek int gpio = d->irq - IRQ_GPIO0; 98a58fbcd8SEric Miao 99a58fbcd8SEric Miao if (__gpio_is_occupied(gpio)) { 100a58fbcd8SEric Miao pr_err("%s failed: GPIO is configured\n", __func__); 101a58fbcd8SEric Miao return -EINVAL; 102a58fbcd8SEric Miao } 103a58fbcd8SEric Miao 104a58fbcd8SEric Miao if (type & IRQ_TYPE_EDGE_RISING) 105a58fbcd8SEric Miao GRER0 |= GPIO_bit(gpio); 106a58fbcd8SEric Miao else 107a58fbcd8SEric Miao GRER0 &= ~GPIO_bit(gpio); 108a58fbcd8SEric Miao 109a58fbcd8SEric Miao if (type & IRQ_TYPE_EDGE_FALLING) 110a58fbcd8SEric Miao GFER0 |= GPIO_bit(gpio); 111a58fbcd8SEric Miao else 112a58fbcd8SEric Miao GFER0 &= ~GPIO_bit(gpio); 113a58fbcd8SEric Miao 114a58fbcd8SEric Miao return 0; 115a58fbcd8SEric Miao } 116a58fbcd8SEric Miao 117a3f4c927SLennert Buytenhek static void pxa_ack_low_gpio(struct irq_data *d) 118a58fbcd8SEric Miao { 119a3f4c927SLennert Buytenhek GEDR0 = (1 << (d->irq - IRQ_GPIO0)); 120a58fbcd8SEric Miao } 121a58fbcd8SEric Miao 122a58fbcd8SEric Miao static struct irq_chip pxa_low_gpio_chip = { 123a58fbcd8SEric Miao .name = "GPIO-l", 124a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_low_gpio, 125a1015a15SEric Miao .irq_mask = pxa_mask_irq, 126a1015a15SEric Miao .irq_unmask = pxa_unmask_irq, 127a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_low_gpio_type, 128a58fbcd8SEric Miao }; 129a58fbcd8SEric Miao 130a58fbcd8SEric Miao static void __init pxa_init_low_gpio_irq(set_wake_t fn) 131a58fbcd8SEric Miao { 132a58fbcd8SEric Miao int irq; 133a58fbcd8SEric Miao 134a58fbcd8SEric Miao /* clear edge detection on GPIO 0 and 1 */ 135a58fbcd8SEric Miao GFER0 &= ~0x3; 136a58fbcd8SEric Miao GRER0 &= ~0x3; 137a58fbcd8SEric Miao GEDR0 = 0x3; 138a58fbcd8SEric Miao 139a58fbcd8SEric Miao for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 1406845664aSThomas Gleixner irq_set_chip(irq, &pxa_low_gpio_chip); 1416845664aSThomas Gleixner irq_set_chip_data(irq, irq_base(0)); 1426845664aSThomas Gleixner irq_set_handler(irq, handle_edge_irq); 143a58fbcd8SEric Miao set_irq_flags(irq, IRQF_VALID); 144a58fbcd8SEric Miao } 145a58fbcd8SEric Miao 146a3f4c927SLennert Buytenhek pxa_low_gpio_chip.irq_set_wake = fn; 147a58fbcd8SEric Miao } 148a58fbcd8SEric Miao 149b9e25aceSeric miao void __init pxa_init_irq(int irq_nr, set_wake_t fn) 15053665a50SEric Miao { 151a79a9ad9SHaojian Zhuang int irq, i, n; 15253665a50SEric Miao 153c482ae4dSHaojian Zhuang BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 154c482ae4dSHaojian Zhuang 155f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 15653665a50SEric Miao 157a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 1581b624fb6SMarek Vasut void __iomem *base = irq_base(n >> 5); 15953665a50SEric Miao 160a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 161a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 162a79a9ad9SHaojian Zhuang for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 163d2c37068SHaojian Zhuang /* initialize interrupt priority */ 164a79a9ad9SHaojian Zhuang if (cpu_has_ipr()) 165a79a9ad9SHaojian Zhuang __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 166d2c37068SHaojian Zhuang 167a79a9ad9SHaojian Zhuang irq = PXA_IRQ(i); 1686845664aSThomas Gleixner irq_set_chip(irq, &pxa_internal_irq_chip); 1696845664aSThomas Gleixner irq_set_chip_data(irq, base); 1706845664aSThomas Gleixner irq_set_handler(irq, handle_level_irq); 17153665a50SEric Miao set_irq_flags(irq, IRQF_VALID); 17253665a50SEric Miao } 173a79a9ad9SHaojian Zhuang } 174a79a9ad9SHaojian Zhuang 175a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 176a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 17753665a50SEric Miao 178a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 179a58fbcd8SEric Miao pxa_init_low_gpio_irq(fn); 180c95530c7Seric miao } 181c0165504Seric miao 182c0165504Seric miao #ifdef CONFIG_PM 183c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 184c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 185c0165504Seric miao 186c0165504Seric miao static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) 187c0165504Seric miao { 188a79a9ad9SHaojian Zhuang int i; 189f6fb7af4Seric miao 1901b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 191a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 192a79a9ad9SHaojian Zhuang 193a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 194a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 195c0165504Seric miao } 196c70f5a60SEric Miao 197bb71bdd3SHaojian Zhuang if (cpu_has_ipr()) { 198c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 199a79a9ad9SHaojian Zhuang saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 200c70f5a60SEric Miao } 201c0165504Seric miao 202c0165504Seric miao return 0; 203c0165504Seric miao } 204c0165504Seric miao 205c0165504Seric miao static int pxa_irq_resume(struct sys_device *dev) 206c0165504Seric miao { 207a79a9ad9SHaojian Zhuang int i; 208f6fb7af4Seric miao 2091b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 210a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 211a79a9ad9SHaojian Zhuang 212a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 213a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 214a79a9ad9SHaojian Zhuang } 215a79a9ad9SHaojian Zhuang 21657879b8cSMarek Vasut if (cpu_has_ipr()) 217c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 218a79a9ad9SHaojian Zhuang __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 219c70f5a60SEric Miao 220a79a9ad9SHaojian Zhuang __raw_writel(1, IRQ_BASE + ICCR); 221c0165504Seric miao return 0; 222c0165504Seric miao } 223c0165504Seric miao #else 224c0165504Seric miao #define pxa_irq_suspend NULL 225c0165504Seric miao #define pxa_irq_resume NULL 226c0165504Seric miao #endif 227c0165504Seric miao 228c0165504Seric miao struct sysdev_class pxa_irq_sysclass = { 229c0165504Seric miao .name = "irq", 230c0165504Seric miao .suspend = pxa_irq_suspend, 231c0165504Seric miao .resume = pxa_irq_resume, 232c0165504Seric miao }; 233c0165504Seric miao 234c0165504Seric miao static int __init pxa_irq_init(void) 235c0165504Seric miao { 236c0165504Seric miao return sysdev_class_register(&pxa_irq_sysclass); 237c0165504Seric miao } 238c0165504Seric miao 239c0165504Seric miao core_initcall(pxa_irq_init); 240