11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 4e3630db1Seric miao * Generic PXA IRQ handling 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 14d6cf30caSRobert Jarzmik #include <linux/bitops.h> 151da177e4SLinus Torvalds #include <linux/init.h> 161da177e4SLinus Torvalds #include <linux/module.h> 171da177e4SLinus Torvalds #include <linux/interrupt.h> 182eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 19a79a9ad9SHaojian Zhuang #include <linux/io.h> 20a79a9ad9SHaojian Zhuang #include <linux/irq.h> 21089d0362SDaniel Mack #include <linux/of_address.h> 22089d0362SDaniel Mack #include <linux/of_irq.h> 231da177e4SLinus Torvalds 245a567d78SJamie Iles #include <asm/exception.h> 255a567d78SJamie Iles 26a09e64fbSRussell King #include <mach/hardware.h> 27a79a9ad9SHaojian Zhuang #include <mach/irqs.h> 281da177e4SLinus Torvalds 291da177e4SLinus Torvalds #include "generic.h" 301da177e4SLinus Torvalds 31a79a9ad9SHaojian Zhuang #define ICIP (0x000) 32a79a9ad9SHaojian Zhuang #define ICMR (0x004) 33a79a9ad9SHaojian Zhuang #define ICLR (0x008) 34a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 35a79a9ad9SHaojian Zhuang #define ICPR (0x010) 36a79a9ad9SHaojian Zhuang #define ICCR (0x014) 37a79a9ad9SHaojian Zhuang #define ICHP (0x018) 38a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 39a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 40a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 41a551e4f7SEric Miao #define ICHP_VAL_IRQ (1 << 31) 42a551e4f7SEric Miao #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 43a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 44a79a9ad9SHaojian Zhuang 45a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 461da177e4SLinus Torvalds 471da177e4SLinus Torvalds /* 481da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 491da177e4SLinus Torvalds */ 501da177e4SLinus Torvalds 51089d0362SDaniel Mack static void __iomem *pxa_irq_base; 52f6fb7af4Seric miao static int pxa_internal_irq_nr; 53089d0362SDaniel Mack static bool cpu_has_ipr; 54d6cf30caSRobert Jarzmik static struct irq_domain *pxa_irq_domain; 55bb71bdd3SHaojian Zhuang 56a1015a15SEric Miao static inline void __iomem *irq_base(int i) 57a1015a15SEric Miao { 58089d0362SDaniel Mack static unsigned long phys_base_offset[] = { 59089d0362SDaniel Mack 0x0, 60089d0362SDaniel Mack 0x9c, 61089d0362SDaniel Mack 0x130, 62a1015a15SEric Miao }; 63a1015a15SEric Miao 64089d0362SDaniel Mack return pxa_irq_base + phys_base_offset[i]; 65a1015a15SEric Miao } 66a1015a15SEric Miao 675d284e35SEric Miao void pxa_mask_irq(struct irq_data *d) 681da177e4SLinus Torvalds { 69a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 70d6cf30caSRobert Jarzmik irq_hw_number_t irq = irqd_to_hwirq(d); 71a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 72a79a9ad9SHaojian Zhuang 73d6cf30caSRobert Jarzmik icmr &= ~BIT(irq & 0x1f); 74a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 751da177e4SLinus Torvalds } 761da177e4SLinus Torvalds 775d284e35SEric Miao void pxa_unmask_irq(struct irq_data *d) 781da177e4SLinus Torvalds { 79a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 80d6cf30caSRobert Jarzmik irq_hw_number_t irq = irqd_to_hwirq(d); 81a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 82a79a9ad9SHaojian Zhuang 83d6cf30caSRobert Jarzmik icmr |= BIT(irq & 0x1f); 84a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 851da177e4SLinus Torvalds } 861da177e4SLinus Torvalds 87f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 8838c677cbSDavid Brownell .name = "SC", 89a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 90a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 91a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 921da177e4SLinus Torvalds }; 931da177e4SLinus Torvalds 94a551e4f7SEric Miao asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 95a551e4f7SEric Miao { 96a551e4f7SEric Miao uint32_t icip, icmr, mask; 97a551e4f7SEric Miao 98a551e4f7SEric Miao do { 99089d0362SDaniel Mack icip = __raw_readl(pxa_irq_base + ICIP); 100089d0362SDaniel Mack icmr = __raw_readl(pxa_irq_base + ICMR); 101a551e4f7SEric Miao mask = icip & icmr; 102a551e4f7SEric Miao 103a551e4f7SEric Miao if (mask == 0) 104a551e4f7SEric Miao break; 105a551e4f7SEric Miao 106a551e4f7SEric Miao handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 107a551e4f7SEric Miao } while (1); 108a551e4f7SEric Miao } 109a551e4f7SEric Miao 110a551e4f7SEric Miao asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 111a551e4f7SEric Miao { 112a551e4f7SEric Miao uint32_t ichp; 113a551e4f7SEric Miao 114a551e4f7SEric Miao do { 115a551e4f7SEric Miao __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 116a551e4f7SEric Miao 117a551e4f7SEric Miao if ((ichp & ICHP_VAL_IRQ) == 0) 118a551e4f7SEric Miao break; 119a551e4f7SEric Miao 120a551e4f7SEric Miao handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 121a551e4f7SEric Miao } while (1); 122a551e4f7SEric Miao } 123a551e4f7SEric Miao 124d6cf30caSRobert Jarzmik static int pxa_irq_map(struct irq_domain *h, unsigned int virq, 125d6cf30caSRobert Jarzmik irq_hw_number_t hw) 12653665a50SEric Miao { 127d6cf30caSRobert Jarzmik void __iomem *base = irq_base(hw / 32); 12853665a50SEric Miao 129d6cf30caSRobert Jarzmik /* initialize interrupt priority */ 130d6cf30caSRobert Jarzmik if (cpu_has_ipr) 131d6cf30caSRobert Jarzmik __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); 132d6cf30caSRobert Jarzmik 133d6cf30caSRobert Jarzmik irq_set_chip_and_handler(virq, &pxa_internal_irq_chip, 134d6cf30caSRobert Jarzmik handle_level_irq); 135d6cf30caSRobert Jarzmik irq_set_chip_data(virq, base); 136d6cf30caSRobert Jarzmik set_irq_flags(virq, IRQF_VALID); 137d6cf30caSRobert Jarzmik 138d6cf30caSRobert Jarzmik return 0; 139d6cf30caSRobert Jarzmik } 140d6cf30caSRobert Jarzmik 14164227114SKrzysztof Kozlowski static const struct irq_domain_ops pxa_irq_ops = { 142d6cf30caSRobert Jarzmik .map = pxa_irq_map, 143d6cf30caSRobert Jarzmik .xlate = irq_domain_xlate_onecell, 144d6cf30caSRobert Jarzmik }; 145d6cf30caSRobert Jarzmik 146d6cf30caSRobert Jarzmik static __init void 147d6cf30caSRobert Jarzmik pxa_init_irq_common(struct device_node *node, int irq_nr, 148d6cf30caSRobert Jarzmik int (*fn)(struct irq_data *, unsigned int)) 149d6cf30caSRobert Jarzmik { 150d6cf30caSRobert Jarzmik int n; 151c482ae4dSHaojian Zhuang 152f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 153d6cf30caSRobert Jarzmik pxa_irq_domain = irq_domain_add_legacy(node, irq_nr, 154d6cf30caSRobert Jarzmik PXA_IRQ(0), 0, 155d6cf30caSRobert Jarzmik &pxa_irq_ops, NULL); 156d6cf30caSRobert Jarzmik if (!pxa_irq_domain) 157d6cf30caSRobert Jarzmik panic("Unable to add PXA IRQ domain\n"); 158d6cf30caSRobert Jarzmik irq_set_default_host(pxa_irq_domain); 15953665a50SEric Miao 160a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 1611b624fb6SMarek Vasut void __iomem *base = irq_base(n >> 5); 16253665a50SEric Miao 163a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 164a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 16553665a50SEric Miao } 166a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 167a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 16853665a50SEric Miao 169a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 170c95530c7Seric miao } 171c0165504Seric miao 172d6cf30caSRobert Jarzmik void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 173d6cf30caSRobert Jarzmik { 174d6cf30caSRobert Jarzmik BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 175d6cf30caSRobert Jarzmik 176d6cf30caSRobert Jarzmik pxa_irq_base = io_p2v(0x40d00000); 177d6cf30caSRobert Jarzmik cpu_has_ipr = !cpu_is_pxa25x(); 178d6cf30caSRobert Jarzmik pxa_init_irq_common(NULL, irq_nr, fn); 179d6cf30caSRobert Jarzmik } 180d6cf30caSRobert Jarzmik 181c0165504Seric miao #ifdef CONFIG_PM 182c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 183c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 184c0165504Seric miao 1852eaa03b5SRafael J. Wysocki static int pxa_irq_suspend(void) 186c0165504Seric miao { 187a79a9ad9SHaojian Zhuang int i; 188f6fb7af4Seric miao 1891b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 190a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 191a79a9ad9SHaojian Zhuang 192a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 193a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 194c0165504Seric miao } 195c70f5a60SEric Miao 196089d0362SDaniel Mack if (cpu_has_ipr) { 197c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 198089d0362SDaniel Mack saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); 199c70f5a60SEric Miao } 200c0165504Seric miao 201c0165504Seric miao return 0; 202c0165504Seric miao } 203c0165504Seric miao 2042eaa03b5SRafael J. Wysocki static void pxa_irq_resume(void) 205c0165504Seric miao { 206a79a9ad9SHaojian Zhuang int i; 207f6fb7af4Seric miao 2081b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 209a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 210a79a9ad9SHaojian Zhuang 211a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 212a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 213a79a9ad9SHaojian Zhuang } 214a79a9ad9SHaojian Zhuang 215089d0362SDaniel Mack if (cpu_has_ipr) 216c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 217089d0362SDaniel Mack __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); 218c70f5a60SEric Miao 219089d0362SDaniel Mack __raw_writel(1, pxa_irq_base + ICCR); 220c0165504Seric miao } 221c0165504Seric miao #else 222c0165504Seric miao #define pxa_irq_suspend NULL 223c0165504Seric miao #define pxa_irq_resume NULL 224c0165504Seric miao #endif 225c0165504Seric miao 2262eaa03b5SRafael J. Wysocki struct syscore_ops pxa_irq_syscore_ops = { 227c0165504Seric miao .suspend = pxa_irq_suspend, 228c0165504Seric miao .resume = pxa_irq_resume, 229c0165504Seric miao }; 230089d0362SDaniel Mack 231089d0362SDaniel Mack #ifdef CONFIG_OF 232089d0362SDaniel Mack static const struct of_device_id intc_ids[] __initconst = { 233089d0362SDaniel Mack { .compatible = "marvell,pxa-intc", }, 234089d0362SDaniel Mack {} 235089d0362SDaniel Mack }; 236089d0362SDaniel Mack 237089d0362SDaniel Mack void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) 238089d0362SDaniel Mack { 239089d0362SDaniel Mack struct device_node *node; 240089d0362SDaniel Mack struct resource res; 241d6cf30caSRobert Jarzmik int ret; 242089d0362SDaniel Mack 243089d0362SDaniel Mack node = of_find_matching_node(NULL, intc_ids); 244089d0362SDaniel Mack if (!node) { 245089d0362SDaniel Mack pr_err("Failed to find interrupt controller in arch-pxa\n"); 246089d0362SDaniel Mack return; 247089d0362SDaniel Mack } 248089d0362SDaniel Mack 249089d0362SDaniel Mack ret = of_property_read_u32(node, "marvell,intc-nr-irqs", 250089d0362SDaniel Mack &pxa_internal_irq_nr); 251089d0362SDaniel Mack if (ret) { 252089d0362SDaniel Mack pr_err("Not found marvell,intc-nr-irqs property\n"); 253089d0362SDaniel Mack return; 254089d0362SDaniel Mack } 255089d0362SDaniel Mack 256089d0362SDaniel Mack ret = of_address_to_resource(node, 0, &res); 257089d0362SDaniel Mack if (ret < 0) { 258089d0362SDaniel Mack pr_err("No registers defined for node\n"); 259089d0362SDaniel Mack return; 260089d0362SDaniel Mack } 261089d0362SDaniel Mack pxa_irq_base = io_p2v(res.start); 262089d0362SDaniel Mack 263089d0362SDaniel Mack if (of_find_property(node, "marvell,intc-priority", NULL)) 264089d0362SDaniel Mack cpu_has_ipr = 1; 265089d0362SDaniel Mack 266089d0362SDaniel Mack ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0); 267089d0362SDaniel Mack if (ret < 0) { 268089d0362SDaniel Mack pr_err("Failed to allocate IRQ numbers\n"); 269089d0362SDaniel Mack return; 270089d0362SDaniel Mack } 271089d0362SDaniel Mack 272d6cf30caSRobert Jarzmik pxa_init_irq_common(node, pxa_internal_irq_nr, fn); 273089d0362SDaniel Mack } 274089d0362SDaniel Mack #endif /* CONFIG_OF */ 275