11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 4e3630db1Seric miao * Generic PXA IRQ handling 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds #include <linux/init.h> 161da177e4SLinus Torvalds #include <linux/module.h> 171da177e4SLinus Torvalds #include <linux/interrupt.h> 182eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 19a79a9ad9SHaojian Zhuang #include <linux/io.h> 20a79a9ad9SHaojian Zhuang #include <linux/irq.h> 211da177e4SLinus Torvalds 225a567d78SJamie Iles #include <asm/exception.h> 235a567d78SJamie Iles 24a09e64fbSRussell King #include <mach/hardware.h> 25a79a9ad9SHaojian Zhuang #include <mach/irqs.h> 26a58fbcd8SEric Miao #include <mach/gpio.h> 271da177e4SLinus Torvalds 281da177e4SLinus Torvalds #include "generic.h" 291da177e4SLinus Torvalds 30a79a9ad9SHaojian Zhuang #define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) 31c482ae4dSHaojian Zhuang 32a79a9ad9SHaojian Zhuang #define ICIP (0x000) 33a79a9ad9SHaojian Zhuang #define ICMR (0x004) 34a79a9ad9SHaojian Zhuang #define ICLR (0x008) 35a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 36a79a9ad9SHaojian Zhuang #define ICPR (0x010) 37a79a9ad9SHaojian Zhuang #define ICCR (0x014) 38a79a9ad9SHaojian Zhuang #define ICHP (0x018) 39a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 40a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 41a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 42a551e4f7SEric Miao #define ICHP_VAL_IRQ (1 << 31) 43a551e4f7SEric Miao #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 44a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 45f6fb7af4Seric miao #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 46a79a9ad9SHaojian Zhuang 47a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 481da177e4SLinus Torvalds 491da177e4SLinus Torvalds /* 501da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 511da177e4SLinus Torvalds */ 521da177e4SLinus Torvalds 53f6fb7af4Seric miao static int pxa_internal_irq_nr; 54f6fb7af4Seric miao 55bb71bdd3SHaojian Zhuang static inline int cpu_has_ipr(void) 56bb71bdd3SHaojian Zhuang { 57bb71bdd3SHaojian Zhuang return !cpu_is_pxa25x(); 58bb71bdd3SHaojian Zhuang } 59bb71bdd3SHaojian Zhuang 60a1015a15SEric Miao static inline void __iomem *irq_base(int i) 61a1015a15SEric Miao { 62a1015a15SEric Miao static unsigned long phys_base[] = { 63a1015a15SEric Miao 0x40d00000, 64a1015a15SEric Miao 0x40d0009c, 65a1015a15SEric Miao 0x40d00130, 66a1015a15SEric Miao }; 67a1015a15SEric Miao 68a1015a15SEric Miao return (void __iomem *)io_p2v(phys_base[i]); 69a1015a15SEric Miao } 70a1015a15SEric Miao 715d284e35SEric Miao void pxa_mask_irq(struct irq_data *d) 721da177e4SLinus Torvalds { 73a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 74a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 75a79a9ad9SHaojian Zhuang 76a3f4c927SLennert Buytenhek icmr &= ~(1 << IRQ_BIT(d->irq)); 77a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 781da177e4SLinus Torvalds } 791da177e4SLinus Torvalds 805d284e35SEric Miao void pxa_unmask_irq(struct irq_data *d) 811da177e4SLinus Torvalds { 82a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 83a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 84a79a9ad9SHaojian Zhuang 85a3f4c927SLennert Buytenhek icmr |= 1 << IRQ_BIT(d->irq); 86a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 871da177e4SLinus Torvalds } 881da177e4SLinus Torvalds 89f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 9038c677cbSDavid Brownell .name = "SC", 91a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 92a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 93a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 941da177e4SLinus Torvalds }; 951da177e4SLinus Torvalds 96a58fbcd8SEric Miao /* 97a58fbcd8SEric Miao * GPIO IRQs for GPIO 0 and 1 98a58fbcd8SEric Miao */ 99a3f4c927SLennert Buytenhek static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) 100a58fbcd8SEric Miao { 101a3f4c927SLennert Buytenhek int gpio = d->irq - IRQ_GPIO0; 102a58fbcd8SEric Miao 103a58fbcd8SEric Miao if (__gpio_is_occupied(gpio)) { 104a58fbcd8SEric Miao pr_err("%s failed: GPIO is configured\n", __func__); 105a58fbcd8SEric Miao return -EINVAL; 106a58fbcd8SEric Miao } 107a58fbcd8SEric Miao 108a58fbcd8SEric Miao if (type & IRQ_TYPE_EDGE_RISING) 109a58fbcd8SEric Miao GRER0 |= GPIO_bit(gpio); 110a58fbcd8SEric Miao else 111a58fbcd8SEric Miao GRER0 &= ~GPIO_bit(gpio); 112a58fbcd8SEric Miao 113a58fbcd8SEric Miao if (type & IRQ_TYPE_EDGE_FALLING) 114a58fbcd8SEric Miao GFER0 |= GPIO_bit(gpio); 115a58fbcd8SEric Miao else 116a58fbcd8SEric Miao GFER0 &= ~GPIO_bit(gpio); 117a58fbcd8SEric Miao 118a58fbcd8SEric Miao return 0; 119a58fbcd8SEric Miao } 120a58fbcd8SEric Miao 121a3f4c927SLennert Buytenhek static void pxa_ack_low_gpio(struct irq_data *d) 122a58fbcd8SEric Miao { 123a3f4c927SLennert Buytenhek GEDR0 = (1 << (d->irq - IRQ_GPIO0)); 124a58fbcd8SEric Miao } 125a58fbcd8SEric Miao 126a58fbcd8SEric Miao static struct irq_chip pxa_low_gpio_chip = { 127a58fbcd8SEric Miao .name = "GPIO-l", 128a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_low_gpio, 129a1015a15SEric Miao .irq_mask = pxa_mask_irq, 130a1015a15SEric Miao .irq_unmask = pxa_unmask_irq, 131a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_low_gpio_type, 132a58fbcd8SEric Miao }; 133a58fbcd8SEric Miao 134a551e4f7SEric Miao asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 135a551e4f7SEric Miao { 136a551e4f7SEric Miao uint32_t icip, icmr, mask; 137a551e4f7SEric Miao 138a551e4f7SEric Miao do { 139a551e4f7SEric Miao icip = __raw_readl(IRQ_BASE + ICIP); 140a551e4f7SEric Miao icmr = __raw_readl(IRQ_BASE + ICMR); 141a551e4f7SEric Miao mask = icip & icmr; 142a551e4f7SEric Miao 143a551e4f7SEric Miao if (mask == 0) 144a551e4f7SEric Miao break; 145a551e4f7SEric Miao 146a551e4f7SEric Miao handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 147a551e4f7SEric Miao } while (1); 148a551e4f7SEric Miao } 149a551e4f7SEric Miao 150a551e4f7SEric Miao asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 151a551e4f7SEric Miao { 152a551e4f7SEric Miao uint32_t ichp; 153a551e4f7SEric Miao 154a551e4f7SEric Miao do { 155a551e4f7SEric Miao __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 156a551e4f7SEric Miao 157a551e4f7SEric Miao if ((ichp & ICHP_VAL_IRQ) == 0) 158a551e4f7SEric Miao break; 159a551e4f7SEric Miao 160a551e4f7SEric Miao handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 161a551e4f7SEric Miao } while (1); 162a551e4f7SEric Miao } 163a551e4f7SEric Miao 164a58fbcd8SEric Miao static void __init pxa_init_low_gpio_irq(set_wake_t fn) 165a58fbcd8SEric Miao { 166a58fbcd8SEric Miao int irq; 167a58fbcd8SEric Miao 168a58fbcd8SEric Miao /* clear edge detection on GPIO 0 and 1 */ 169a58fbcd8SEric Miao GFER0 &= ~0x3; 170a58fbcd8SEric Miao GRER0 &= ~0x3; 171a58fbcd8SEric Miao GEDR0 = 0x3; 172a58fbcd8SEric Miao 173a58fbcd8SEric Miao for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 174f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, 175f38c02f3SThomas Gleixner handle_edge_irq); 1769323f261SThomas Gleixner irq_set_chip_data(irq, irq_base(0)); 177a58fbcd8SEric Miao set_irq_flags(irq, IRQF_VALID); 178a58fbcd8SEric Miao } 179a58fbcd8SEric Miao 180a3f4c927SLennert Buytenhek pxa_low_gpio_chip.irq_set_wake = fn; 181a58fbcd8SEric Miao } 182a58fbcd8SEric Miao 183b9e25aceSeric miao void __init pxa_init_irq(int irq_nr, set_wake_t fn) 18453665a50SEric Miao { 185a79a9ad9SHaojian Zhuang int irq, i, n; 18653665a50SEric Miao 187c482ae4dSHaojian Zhuang BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 188c482ae4dSHaojian Zhuang 189f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 19053665a50SEric Miao 191a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 1921b624fb6SMarek Vasut void __iomem *base = irq_base(n >> 5); 19353665a50SEric Miao 194a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 195a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 196a79a9ad9SHaojian Zhuang for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 197d2c37068SHaojian Zhuang /* initialize interrupt priority */ 198a79a9ad9SHaojian Zhuang if (cpu_has_ipr()) 199a79a9ad9SHaojian Zhuang __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 200d2c37068SHaojian Zhuang 201a79a9ad9SHaojian Zhuang irq = PXA_IRQ(i); 202f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, 203f38c02f3SThomas Gleixner handle_level_irq); 2049323f261SThomas Gleixner irq_set_chip_data(irq, base); 20553665a50SEric Miao set_irq_flags(irq, IRQF_VALID); 20653665a50SEric Miao } 207a79a9ad9SHaojian Zhuang } 208a79a9ad9SHaojian Zhuang 209a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 210a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 21153665a50SEric Miao 212a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 213a58fbcd8SEric Miao pxa_init_low_gpio_irq(fn); 214c95530c7Seric miao } 215c0165504Seric miao 216c0165504Seric miao #ifdef CONFIG_PM 217c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 218c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 219c0165504Seric miao 2202eaa03b5SRafael J. Wysocki static int pxa_irq_suspend(void) 221c0165504Seric miao { 222a79a9ad9SHaojian Zhuang int i; 223f6fb7af4Seric miao 2241b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 225a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 226a79a9ad9SHaojian Zhuang 227a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 228a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 229c0165504Seric miao } 230c70f5a60SEric Miao 231bb71bdd3SHaojian Zhuang if (cpu_has_ipr()) { 232c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 233a79a9ad9SHaojian Zhuang saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 234c70f5a60SEric Miao } 235c0165504Seric miao 236c0165504Seric miao return 0; 237c0165504Seric miao } 238c0165504Seric miao 2392eaa03b5SRafael J. Wysocki static void pxa_irq_resume(void) 240c0165504Seric miao { 241a79a9ad9SHaojian Zhuang int i; 242f6fb7af4Seric miao 2431b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 244a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 245a79a9ad9SHaojian Zhuang 246a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 247a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 248a79a9ad9SHaojian Zhuang } 249a79a9ad9SHaojian Zhuang 25057879b8cSMarek Vasut if (cpu_has_ipr()) 251c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 252a79a9ad9SHaojian Zhuang __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 253c70f5a60SEric Miao 254a79a9ad9SHaojian Zhuang __raw_writel(1, IRQ_BASE + ICCR); 255c0165504Seric miao } 256c0165504Seric miao #else 257c0165504Seric miao #define pxa_irq_suspend NULL 258c0165504Seric miao #define pxa_irq_resume NULL 259c0165504Seric miao #endif 260c0165504Seric miao 2612eaa03b5SRafael J. Wysocki struct syscore_ops pxa_irq_syscore_ops = { 262c0165504Seric miao .suspend = pxa_irq_suspend, 263c0165504Seric miao .resume = pxa_irq_resume, 264c0165504Seric miao }; 265