11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 4e3630db1Seric miao * Generic PXA IRQ handling 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds #include <linux/init.h> 161da177e4SLinus Torvalds #include <linux/module.h> 171da177e4SLinus Torvalds #include <linux/interrupt.h> 18c0165504Seric miao #include <linux/sysdev.h> 19a79a9ad9SHaojian Zhuang #include <linux/io.h> 20a79a9ad9SHaojian Zhuang #include <linux/irq.h> 211da177e4SLinus Torvalds 22a09e64fbSRussell King #include <mach/hardware.h> 23a79a9ad9SHaojian Zhuang #include <mach/irqs.h> 24a58fbcd8SEric Miao #include <mach/gpio.h> 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds #include "generic.h" 271da177e4SLinus Torvalds 28a79a9ad9SHaojian Zhuang #define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) 29c482ae4dSHaojian Zhuang 30a79a9ad9SHaojian Zhuang #define ICIP (0x000) 31a79a9ad9SHaojian Zhuang #define ICMR (0x004) 32a79a9ad9SHaojian Zhuang #define ICLR (0x008) 33a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 34a79a9ad9SHaojian Zhuang #define ICPR (0x010) 35a79a9ad9SHaojian Zhuang #define ICCR (0x014) 36a79a9ad9SHaojian Zhuang #define ICHP (0x018) 37a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 38a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 39a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 40a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 41f6fb7af4Seric miao #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 42a79a9ad9SHaojian Zhuang 43a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 441da177e4SLinus Torvalds 451da177e4SLinus Torvalds /* 461da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 471da177e4SLinus Torvalds */ 481da177e4SLinus Torvalds 49f6fb7af4Seric miao static int pxa_internal_irq_nr; 50f6fb7af4Seric miao 51bb71bdd3SHaojian Zhuang static inline int cpu_has_ipr(void) 52bb71bdd3SHaojian Zhuang { 53bb71bdd3SHaojian Zhuang return !cpu_is_pxa25x(); 54bb71bdd3SHaojian Zhuang } 55bb71bdd3SHaojian Zhuang 56a3f4c927SLennert Buytenhek static void pxa_mask_irq(struct irq_data *d) 571da177e4SLinus Torvalds { 58a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 59a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 60a79a9ad9SHaojian Zhuang 61a3f4c927SLennert Buytenhek icmr &= ~(1 << IRQ_BIT(d->irq)); 62a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 631da177e4SLinus Torvalds } 641da177e4SLinus Torvalds 65a3f4c927SLennert Buytenhek static void pxa_unmask_irq(struct irq_data *d) 661da177e4SLinus Torvalds { 67a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 68a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 69a79a9ad9SHaojian Zhuang 70a3f4c927SLennert Buytenhek icmr |= 1 << IRQ_BIT(d->irq); 71a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 721da177e4SLinus Torvalds } 731da177e4SLinus Torvalds 74f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 7538c677cbSDavid Brownell .name = "SC", 76a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 77a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 78a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 791da177e4SLinus Torvalds }; 801da177e4SLinus Torvalds 81a58fbcd8SEric Miao /* 82a58fbcd8SEric Miao * GPIO IRQs for GPIO 0 and 1 83a58fbcd8SEric Miao */ 84a3f4c927SLennert Buytenhek static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) 85a58fbcd8SEric Miao { 86a3f4c927SLennert Buytenhek int gpio = d->irq - IRQ_GPIO0; 87a58fbcd8SEric Miao 88a58fbcd8SEric Miao if (__gpio_is_occupied(gpio)) { 89a58fbcd8SEric Miao pr_err("%s failed: GPIO is configured\n", __func__); 90a58fbcd8SEric Miao return -EINVAL; 91a58fbcd8SEric Miao } 92a58fbcd8SEric Miao 93a58fbcd8SEric Miao if (type & IRQ_TYPE_EDGE_RISING) 94a58fbcd8SEric Miao GRER0 |= GPIO_bit(gpio); 95a58fbcd8SEric Miao else 96a58fbcd8SEric Miao GRER0 &= ~GPIO_bit(gpio); 97a58fbcd8SEric Miao 98a58fbcd8SEric Miao if (type & IRQ_TYPE_EDGE_FALLING) 99a58fbcd8SEric Miao GFER0 |= GPIO_bit(gpio); 100a58fbcd8SEric Miao else 101a58fbcd8SEric Miao GFER0 &= ~GPIO_bit(gpio); 102a58fbcd8SEric Miao 103a58fbcd8SEric Miao return 0; 104a58fbcd8SEric Miao } 105a58fbcd8SEric Miao 106a3f4c927SLennert Buytenhek static void pxa_ack_low_gpio(struct irq_data *d) 107a58fbcd8SEric Miao { 108a3f4c927SLennert Buytenhek GEDR0 = (1 << (d->irq - IRQ_GPIO0)); 109a58fbcd8SEric Miao } 110a58fbcd8SEric Miao 111a3f4c927SLennert Buytenhek static void pxa_mask_low_gpio(struct irq_data *d) 112a58fbcd8SEric Miao { 113a3f4c927SLennert Buytenhek struct irq_desc *desc = irq_to_desc(d->irq); 114a79a9ad9SHaojian Zhuang 115a3f4c927SLennert Buytenhek desc->irq_data.chip->irq_mask(d); 116a58fbcd8SEric Miao } 117a58fbcd8SEric Miao 118a3f4c927SLennert Buytenhek static void pxa_unmask_low_gpio(struct irq_data *d) 119a58fbcd8SEric Miao { 120a3f4c927SLennert Buytenhek struct irq_desc *desc = irq_to_desc(d->irq); 121a79a9ad9SHaojian Zhuang 122a3f4c927SLennert Buytenhek desc->irq_data.chip->irq_unmask(d); 123a58fbcd8SEric Miao } 124a58fbcd8SEric Miao 125a58fbcd8SEric Miao static struct irq_chip pxa_low_gpio_chip = { 126a58fbcd8SEric Miao .name = "GPIO-l", 127a3f4c927SLennert Buytenhek .irq_ack = pxa_ack_low_gpio, 128a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_low_gpio, 129a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_low_gpio, 130a3f4c927SLennert Buytenhek .irq_set_type = pxa_set_low_gpio_type, 131a58fbcd8SEric Miao }; 132a58fbcd8SEric Miao 133a58fbcd8SEric Miao static void __init pxa_init_low_gpio_irq(set_wake_t fn) 134a58fbcd8SEric Miao { 135a58fbcd8SEric Miao int irq; 136a58fbcd8SEric Miao 137a58fbcd8SEric Miao /* clear edge detection on GPIO 0 and 1 */ 138a58fbcd8SEric Miao GFER0 &= ~0x3; 139a58fbcd8SEric Miao GRER0 &= ~0x3; 140a58fbcd8SEric Miao GEDR0 = 0x3; 141a58fbcd8SEric Miao 142a58fbcd8SEric Miao for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 143a58fbcd8SEric Miao set_irq_chip(irq, &pxa_low_gpio_chip); 144a58fbcd8SEric Miao set_irq_handler(irq, handle_edge_irq); 145a58fbcd8SEric Miao set_irq_flags(irq, IRQF_VALID); 146a58fbcd8SEric Miao } 147a58fbcd8SEric Miao 148a3f4c927SLennert Buytenhek pxa_low_gpio_chip.irq_set_wake = fn; 149a58fbcd8SEric Miao } 150a58fbcd8SEric Miao 151a79a9ad9SHaojian Zhuang static inline void __iomem *irq_base(int i) 152a79a9ad9SHaojian Zhuang { 153a79a9ad9SHaojian Zhuang static unsigned long phys_base[] = { 154a79a9ad9SHaojian Zhuang 0x40d00000, 155a79a9ad9SHaojian Zhuang 0x40d0009c, 156a79a9ad9SHaojian Zhuang 0x40d00130, 157a79a9ad9SHaojian Zhuang }; 158a79a9ad9SHaojian Zhuang 159a79a9ad9SHaojian Zhuang return (void __iomem *)io_p2v(phys_base[i >> 5]); 160a79a9ad9SHaojian Zhuang } 161a79a9ad9SHaojian Zhuang 162b9e25aceSeric miao void __init pxa_init_irq(int irq_nr, set_wake_t fn) 16353665a50SEric Miao { 164a79a9ad9SHaojian Zhuang int irq, i, n; 16553665a50SEric Miao 166c482ae4dSHaojian Zhuang BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 167c482ae4dSHaojian Zhuang 168f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 16953665a50SEric Miao 170a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 171a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(n); 17253665a50SEric Miao 173a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 174a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 175a79a9ad9SHaojian Zhuang for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 176d2c37068SHaojian Zhuang /* initialize interrupt priority */ 177a79a9ad9SHaojian Zhuang if (cpu_has_ipr()) 178a79a9ad9SHaojian Zhuang __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 179d2c37068SHaojian Zhuang 180a79a9ad9SHaojian Zhuang irq = PXA_IRQ(i); 181f6fb7af4Seric miao set_irq_chip(irq, &pxa_internal_irq_chip); 182a79a9ad9SHaojian Zhuang set_irq_chip_data(irq, base); 18353665a50SEric Miao set_irq_handler(irq, handle_level_irq); 18453665a50SEric Miao set_irq_flags(irq, IRQF_VALID); 18553665a50SEric Miao } 186a79a9ad9SHaojian Zhuang } 187a79a9ad9SHaojian Zhuang 188a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 189a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 19053665a50SEric Miao 191a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 192a58fbcd8SEric Miao pxa_init_low_gpio_irq(fn); 193c95530c7Seric miao } 194c0165504Seric miao 195c0165504Seric miao #ifdef CONFIG_PM 196c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 197c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 198c0165504Seric miao 199c0165504Seric miao static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) 200c0165504Seric miao { 201a79a9ad9SHaojian Zhuang int i; 202f6fb7af4Seric miao 203a79a9ad9SHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i += 32) { 204a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 205a79a9ad9SHaojian Zhuang 206a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 207a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 208c0165504Seric miao } 209c70f5a60SEric Miao 210bb71bdd3SHaojian Zhuang if (cpu_has_ipr()) { 211c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 212a79a9ad9SHaojian Zhuang saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 213c70f5a60SEric Miao } 214c0165504Seric miao 215c0165504Seric miao return 0; 216c0165504Seric miao } 217c0165504Seric miao 218c0165504Seric miao static int pxa_irq_resume(struct sys_device *dev) 219c0165504Seric miao { 220a79a9ad9SHaojian Zhuang int i; 221f6fb7af4Seric miao 222a79a9ad9SHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i += 32) { 223a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 224a79a9ad9SHaojian Zhuang 225a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 226a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 227a79a9ad9SHaojian Zhuang } 228a79a9ad9SHaojian Zhuang 22957879b8cSMarek Vasut if (cpu_has_ipr()) 230c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 231a79a9ad9SHaojian Zhuang __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 232c70f5a60SEric Miao 233a79a9ad9SHaojian Zhuang __raw_writel(1, IRQ_BASE + ICCR); 234c0165504Seric miao return 0; 235c0165504Seric miao } 236c0165504Seric miao #else 237c0165504Seric miao #define pxa_irq_suspend NULL 238c0165504Seric miao #define pxa_irq_resume NULL 239c0165504Seric miao #endif 240c0165504Seric miao 241c0165504Seric miao struct sysdev_class pxa_irq_sysclass = { 242c0165504Seric miao .name = "irq", 243c0165504Seric miao .suspend = pxa_irq_suspend, 244c0165504Seric miao .resume = pxa_irq_resume, 245c0165504Seric miao }; 246c0165504Seric miao 247c0165504Seric miao static int __init pxa_irq_init(void) 248c0165504Seric miao { 249c0165504Seric miao return sysdev_class_register(&pxa_irq_sysclass); 250c0165504Seric miao } 251c0165504Seric miao 252c0165504Seric miao core_initcall(pxa_irq_init); 253