11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds #include <linux/init.h> 161da177e4SLinus Torvalds #include <linux/module.h> 171da177e4SLinus Torvalds #include <linux/interrupt.h> 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds #include <asm/hardware.h> 201da177e4SLinus Torvalds #include <asm/irq.h> 211da177e4SLinus Torvalds #include <asm/mach/irq.h> 221da177e4SLinus Torvalds #include <asm/arch/pxa-regs.h> 231da177e4SLinus Torvalds 241da177e4SLinus Torvalds #include "generic.h" 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds 271da177e4SLinus Torvalds /* 281da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 291da177e4SLinus Torvalds */ 301da177e4SLinus Torvalds 311da177e4SLinus Torvalds static void pxa_mask_low_irq(unsigned int irq) 321da177e4SLinus Torvalds { 33486c9551SEric Miao ICMR &= ~(1 << irq); 341da177e4SLinus Torvalds } 351da177e4SLinus Torvalds 361da177e4SLinus Torvalds static void pxa_unmask_low_irq(unsigned int irq) 371da177e4SLinus Torvalds { 38486c9551SEric Miao ICMR |= (1 << irq); 391da177e4SLinus Torvalds } 401da177e4SLinus Torvalds 414fe4a2bfSPhilipp Zabel static int pxa_set_wake(unsigned int irq, unsigned int on) 424fe4a2bfSPhilipp Zabel { 434fe4a2bfSPhilipp Zabel u32 mask; 444fe4a2bfSPhilipp Zabel 454fe4a2bfSPhilipp Zabel switch (irq) { 464fe4a2bfSPhilipp Zabel case IRQ_RTCAlrm: 474fe4a2bfSPhilipp Zabel mask = PWER_RTC; 484fe4a2bfSPhilipp Zabel break; 494fe4a2bfSPhilipp Zabel #ifdef CONFIG_PXA27x 504fe4a2bfSPhilipp Zabel /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */ 514fe4a2bfSPhilipp Zabel #endif 524fe4a2bfSPhilipp Zabel default: 534fe4a2bfSPhilipp Zabel return -EINVAL; 544fe4a2bfSPhilipp Zabel } 554fe4a2bfSPhilipp Zabel if (on) 564fe4a2bfSPhilipp Zabel PWER |= mask; 574fe4a2bfSPhilipp Zabel else 584fe4a2bfSPhilipp Zabel PWER &= ~mask; 594fe4a2bfSPhilipp Zabel return 0; 604fe4a2bfSPhilipp Zabel } 614fe4a2bfSPhilipp Zabel 6238c677cbSDavid Brownell static struct irq_chip pxa_internal_chip_low = { 6338c677cbSDavid Brownell .name = "SC", 641da177e4SLinus Torvalds .ack = pxa_mask_low_irq, 651da177e4SLinus Torvalds .mask = pxa_mask_low_irq, 661da177e4SLinus Torvalds .unmask = pxa_unmask_low_irq, 674fe4a2bfSPhilipp Zabel .set_wake = pxa_set_wake, 681da177e4SLinus Torvalds }; 691da177e4SLinus Torvalds 701da177e4SLinus Torvalds #if PXA_INTERNAL_IRQS > 32 711da177e4SLinus Torvalds 721da177e4SLinus Torvalds /* 731da177e4SLinus Torvalds * This is for the second set of internal IRQs as found on the PXA27x. 741da177e4SLinus Torvalds */ 751da177e4SLinus Torvalds 761da177e4SLinus Torvalds static void pxa_mask_high_irq(unsigned int irq) 771da177e4SLinus Torvalds { 78486c9551SEric Miao ICMR2 &= ~(1 << (irq - 32)); 791da177e4SLinus Torvalds } 801da177e4SLinus Torvalds 811da177e4SLinus Torvalds static void pxa_unmask_high_irq(unsigned int irq) 821da177e4SLinus Torvalds { 83486c9551SEric Miao ICMR2 |= (1 << (irq - 32)); 841da177e4SLinus Torvalds } 851da177e4SLinus Torvalds 8638c677cbSDavid Brownell static struct irq_chip pxa_internal_chip_high = { 8738c677cbSDavid Brownell .name = "SC-hi", 881da177e4SLinus Torvalds .ack = pxa_mask_high_irq, 891da177e4SLinus Torvalds .mask = pxa_mask_high_irq, 901da177e4SLinus Torvalds .unmask = pxa_unmask_high_irq, 911da177e4SLinus Torvalds }; 921da177e4SLinus Torvalds 931da177e4SLinus Torvalds #endif 941da177e4SLinus Torvalds 954fe4a2bfSPhilipp Zabel /* Note that if an input/irq line ever gets changed to an output during 964fe4a2bfSPhilipp Zabel * suspend, the relevant PWER, PRER, and PFER bits should be cleared. 974fe4a2bfSPhilipp Zabel */ 984fe4a2bfSPhilipp Zabel #ifdef CONFIG_PXA27x 994fe4a2bfSPhilipp Zabel 1004fe4a2bfSPhilipp Zabel /* PXA27x: Various gpios can issue wakeup events. This logic only 1014fe4a2bfSPhilipp Zabel * handles the simple cases, not the WEMUX2 and WEMUX3 options 1024fe4a2bfSPhilipp Zabel */ 1034fe4a2bfSPhilipp Zabel #define PXA27x_GPIO_NOWAKE_MASK \ 1044fe4a2bfSPhilipp Zabel ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) 1054fe4a2bfSPhilipp Zabel #define WAKEMASK(gpio) \ 1064fe4a2bfSPhilipp Zabel (((gpio) <= 15) \ 1074fe4a2bfSPhilipp Zabel ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ 1084fe4a2bfSPhilipp Zabel : ((gpio == 35) ? (1 << 24) : 0)) 1094fe4a2bfSPhilipp Zabel #else 1104fe4a2bfSPhilipp Zabel 1114fe4a2bfSPhilipp Zabel /* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */ 1124fe4a2bfSPhilipp Zabel #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0) 1134fe4a2bfSPhilipp Zabel #endif 1144fe4a2bfSPhilipp Zabel 1151da177e4SLinus Torvalds /* 1161da177e4SLinus Torvalds * PXA GPIO edge detection for IRQs: 1171da177e4SLinus Torvalds * IRQs are generated on Falling-Edge, Rising-Edge, or both. 1181da177e4SLinus Torvalds * Use this instead of directly setting GRER/GFER. 1191da177e4SLinus Torvalds */ 1201da177e4SLinus Torvalds 1211da177e4SLinus Torvalds static long GPIO_IRQ_rising_edge[4]; 1221da177e4SLinus Torvalds static long GPIO_IRQ_falling_edge[4]; 1231da177e4SLinus Torvalds static long GPIO_IRQ_mask[4]; 1241da177e4SLinus Torvalds 1251da177e4SLinus Torvalds static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 1261da177e4SLinus Torvalds { 1271da177e4SLinus Torvalds int gpio, idx; 1284fe4a2bfSPhilipp Zabel u32 mask; 1291da177e4SLinus Torvalds 1301da177e4SLinus Torvalds gpio = IRQ_TO_GPIO(irq); 1311da177e4SLinus Torvalds idx = gpio >> 5; 1324fe4a2bfSPhilipp Zabel mask = WAKEMASK(gpio); 1331da177e4SLinus Torvalds 1341da177e4SLinus Torvalds if (type == IRQT_PROBE) { 1351da177e4SLinus Torvalds /* Don't mess with enabled GPIOs using preconfigured edges or 136e033108bSGuennadi Liakhovetski GPIOs set to alternate function or to output during probe */ 137e033108bSGuennadi Liakhovetski if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & 1381da177e4SLinus Torvalds GPIO_bit(gpio)) 1391da177e4SLinus Torvalds return 0; 1401da177e4SLinus Torvalds if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) 1411da177e4SLinus Torvalds return 0; 1421da177e4SLinus Torvalds type = __IRQT_RISEDGE | __IRQT_FALEDGE; 1431da177e4SLinus Torvalds } 1441da177e4SLinus Torvalds 1451da177e4SLinus Torvalds /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ 1461da177e4SLinus Torvalds 1471da177e4SLinus Torvalds pxa_gpio_mode(gpio | GPIO_IN); 1481da177e4SLinus Torvalds 1491da177e4SLinus Torvalds if (type & __IRQT_RISEDGE) { 1501da177e4SLinus Torvalds /* printk("rising "); */ 1511da177e4SLinus Torvalds __set_bit (gpio, GPIO_IRQ_rising_edge); 1524fe4a2bfSPhilipp Zabel PRER |= mask; 1534fe4a2bfSPhilipp Zabel } else { 1541da177e4SLinus Torvalds __clear_bit (gpio, GPIO_IRQ_rising_edge); 1554fe4a2bfSPhilipp Zabel PRER &= ~mask; 1564fe4a2bfSPhilipp Zabel } 1571da177e4SLinus Torvalds 1581da177e4SLinus Torvalds if (type & __IRQT_FALEDGE) { 1591da177e4SLinus Torvalds /* printk("falling "); */ 1601da177e4SLinus Torvalds __set_bit (gpio, GPIO_IRQ_falling_edge); 1614fe4a2bfSPhilipp Zabel PFER |= mask; 1624fe4a2bfSPhilipp Zabel } else { 1631da177e4SLinus Torvalds __clear_bit (gpio, GPIO_IRQ_falling_edge); 1644fe4a2bfSPhilipp Zabel PFER &= ~mask; 1654fe4a2bfSPhilipp Zabel } 1661da177e4SLinus Torvalds 1671da177e4SLinus Torvalds /* printk("edges\n"); */ 1681da177e4SLinus Torvalds 1691da177e4SLinus Torvalds GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 1701da177e4SLinus Torvalds GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 1711da177e4SLinus Torvalds return 0; 1721da177e4SLinus Torvalds } 1731da177e4SLinus Torvalds 1741da177e4SLinus Torvalds /* 1751da177e4SLinus Torvalds * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. 1761da177e4SLinus Torvalds */ 1771da177e4SLinus Torvalds 1781da177e4SLinus Torvalds static void pxa_ack_low_gpio(unsigned int irq) 1791da177e4SLinus Torvalds { 1801da177e4SLinus Torvalds GEDR0 = (1 << (irq - IRQ_GPIO0)); 1811da177e4SLinus Torvalds } 1821da177e4SLinus Torvalds 1834fe4a2bfSPhilipp Zabel static int pxa_set_gpio_wake(unsigned int irq, unsigned int on) 1844fe4a2bfSPhilipp Zabel { 1854fe4a2bfSPhilipp Zabel int gpio = IRQ_TO_GPIO(irq); 1864fe4a2bfSPhilipp Zabel u32 mask = WAKEMASK(gpio); 1874fe4a2bfSPhilipp Zabel 1884fe4a2bfSPhilipp Zabel if (!mask) 1894fe4a2bfSPhilipp Zabel return -EINVAL; 1904fe4a2bfSPhilipp Zabel 1914fe4a2bfSPhilipp Zabel if (on) 1924fe4a2bfSPhilipp Zabel PWER |= mask; 1934fe4a2bfSPhilipp Zabel else 1944fe4a2bfSPhilipp Zabel PWER &= ~mask; 1954fe4a2bfSPhilipp Zabel return 0; 1964fe4a2bfSPhilipp Zabel } 1974fe4a2bfSPhilipp Zabel 1984fe4a2bfSPhilipp Zabel 19938c677cbSDavid Brownell static struct irq_chip pxa_low_gpio_chip = { 20038c677cbSDavid Brownell .name = "GPIO-l", 2011da177e4SLinus Torvalds .ack = pxa_ack_low_gpio, 2021da177e4SLinus Torvalds .mask = pxa_mask_low_irq, 2031da177e4SLinus Torvalds .unmask = pxa_unmask_low_irq, 2047801907bSRussell King .set_type = pxa_gpio_irq_type, 2054fe4a2bfSPhilipp Zabel .set_wake = pxa_set_gpio_wake, 2061da177e4SLinus Torvalds }; 2071da177e4SLinus Torvalds 2081da177e4SLinus Torvalds /* 2091da177e4SLinus Torvalds * Demux handler for GPIO>=2 edge detect interrupts 2101da177e4SLinus Torvalds */ 2111da177e4SLinus Torvalds 21210dd5ce2SRussell King static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 2131da177e4SLinus Torvalds { 2141da177e4SLinus Torvalds unsigned int mask; 2151da177e4SLinus Torvalds int loop; 2161da177e4SLinus Torvalds 2171da177e4SLinus Torvalds do { 2181da177e4SLinus Torvalds loop = 0; 2191da177e4SLinus Torvalds 2201da177e4SLinus Torvalds mask = GEDR0 & ~3; 2211da177e4SLinus Torvalds if (mask) { 2221da177e4SLinus Torvalds GEDR0 = mask; 2231da177e4SLinus Torvalds irq = IRQ_GPIO(2); 2241da177e4SLinus Torvalds desc = irq_desc + irq; 2251da177e4SLinus Torvalds mask >>= 2; 2261da177e4SLinus Torvalds do { 2271da177e4SLinus Torvalds if (mask & 1) 2280cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2291da177e4SLinus Torvalds irq++; 2301da177e4SLinus Torvalds desc++; 2311da177e4SLinus Torvalds mask >>= 1; 2321da177e4SLinus Torvalds } while (mask); 2331da177e4SLinus Torvalds loop = 1; 2341da177e4SLinus Torvalds } 2351da177e4SLinus Torvalds 2361da177e4SLinus Torvalds mask = GEDR1; 2371da177e4SLinus Torvalds if (mask) { 2381da177e4SLinus Torvalds GEDR1 = mask; 2391da177e4SLinus Torvalds irq = IRQ_GPIO(32); 2401da177e4SLinus Torvalds desc = irq_desc + irq; 2411da177e4SLinus Torvalds do { 2421da177e4SLinus Torvalds if (mask & 1) 2430cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2441da177e4SLinus Torvalds irq++; 2451da177e4SLinus Torvalds desc++; 2461da177e4SLinus Torvalds mask >>= 1; 2471da177e4SLinus Torvalds } while (mask); 2481da177e4SLinus Torvalds loop = 1; 2491da177e4SLinus Torvalds } 2501da177e4SLinus Torvalds 2511da177e4SLinus Torvalds mask = GEDR2; 2521da177e4SLinus Torvalds if (mask) { 2531da177e4SLinus Torvalds GEDR2 = mask; 2541da177e4SLinus Torvalds irq = IRQ_GPIO(64); 2551da177e4SLinus Torvalds desc = irq_desc + irq; 2561da177e4SLinus Torvalds do { 2571da177e4SLinus Torvalds if (mask & 1) 2580cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2591da177e4SLinus Torvalds irq++; 2601da177e4SLinus Torvalds desc++; 2611da177e4SLinus Torvalds mask >>= 1; 2621da177e4SLinus Torvalds } while (mask); 2631da177e4SLinus Torvalds loop = 1; 2641da177e4SLinus Torvalds } 2651da177e4SLinus Torvalds 2661da177e4SLinus Torvalds #if PXA_LAST_GPIO >= 96 2671da177e4SLinus Torvalds mask = GEDR3; 2681da177e4SLinus Torvalds if (mask) { 2691da177e4SLinus Torvalds GEDR3 = mask; 2701da177e4SLinus Torvalds irq = IRQ_GPIO(96); 2711da177e4SLinus Torvalds desc = irq_desc + irq; 2721da177e4SLinus Torvalds do { 2731da177e4SLinus Torvalds if (mask & 1) 2740cd61b68SLinus Torvalds desc_handle_irq(irq, desc); 2751da177e4SLinus Torvalds irq++; 2761da177e4SLinus Torvalds desc++; 2771da177e4SLinus Torvalds mask >>= 1; 2781da177e4SLinus Torvalds } while (mask); 2791da177e4SLinus Torvalds loop = 1; 2801da177e4SLinus Torvalds } 2811da177e4SLinus Torvalds #endif 2821da177e4SLinus Torvalds } while (loop); 2831da177e4SLinus Torvalds } 2841da177e4SLinus Torvalds 2851da177e4SLinus Torvalds static void pxa_ack_muxed_gpio(unsigned int irq) 2861da177e4SLinus Torvalds { 2871da177e4SLinus Torvalds int gpio = irq - IRQ_GPIO(2) + 2; 2881da177e4SLinus Torvalds GEDR(gpio) = GPIO_bit(gpio); 2891da177e4SLinus Torvalds } 2901da177e4SLinus Torvalds 2911da177e4SLinus Torvalds static void pxa_mask_muxed_gpio(unsigned int irq) 2921da177e4SLinus Torvalds { 2931da177e4SLinus Torvalds int gpio = irq - IRQ_GPIO(2) + 2; 2941da177e4SLinus Torvalds __clear_bit(gpio, GPIO_IRQ_mask); 2951da177e4SLinus Torvalds GRER(gpio) &= ~GPIO_bit(gpio); 2961da177e4SLinus Torvalds GFER(gpio) &= ~GPIO_bit(gpio); 2971da177e4SLinus Torvalds } 2981da177e4SLinus Torvalds 2991da177e4SLinus Torvalds static void pxa_unmask_muxed_gpio(unsigned int irq) 3001da177e4SLinus Torvalds { 3011da177e4SLinus Torvalds int gpio = irq - IRQ_GPIO(2) + 2; 3021da177e4SLinus Torvalds int idx = gpio >> 5; 3031da177e4SLinus Torvalds __set_bit(gpio, GPIO_IRQ_mask); 3041da177e4SLinus Torvalds GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; 3051da177e4SLinus Torvalds GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; 3061da177e4SLinus Torvalds } 3071da177e4SLinus Torvalds 30838c677cbSDavid Brownell static struct irq_chip pxa_muxed_gpio_chip = { 30938c677cbSDavid Brownell .name = "GPIO", 3101da177e4SLinus Torvalds .ack = pxa_ack_muxed_gpio, 3111da177e4SLinus Torvalds .mask = pxa_mask_muxed_gpio, 3121da177e4SLinus Torvalds .unmask = pxa_unmask_muxed_gpio, 3137801907bSRussell King .set_type = pxa_gpio_irq_type, 3144fe4a2bfSPhilipp Zabel .set_wake = pxa_set_gpio_wake, 3151da177e4SLinus Torvalds }; 3161da177e4SLinus Torvalds 3171da177e4SLinus Torvalds 3181da177e4SLinus Torvalds void __init pxa_init_irq(void) 3191da177e4SLinus Torvalds { 3201da177e4SLinus Torvalds int irq; 3211da177e4SLinus Torvalds 3221da177e4SLinus Torvalds /* disable all IRQs */ 3231da177e4SLinus Torvalds ICMR = 0; 3241da177e4SLinus Torvalds 3251da177e4SLinus Torvalds /* all IRQs are IRQ, not FIQ */ 3261da177e4SLinus Torvalds ICLR = 0; 3271da177e4SLinus Torvalds 3281da177e4SLinus Torvalds /* clear all GPIO edge detects */ 3291da177e4SLinus Torvalds GFER0 = 0; 3301da177e4SLinus Torvalds GFER1 = 0; 3311da177e4SLinus Torvalds GFER2 = 0; 3321da177e4SLinus Torvalds GRER0 = 0; 3331da177e4SLinus Torvalds GRER1 = 0; 3341da177e4SLinus Torvalds GRER2 = 0; 3351da177e4SLinus Torvalds GEDR0 = GEDR0; 3361da177e4SLinus Torvalds GEDR1 = GEDR1; 3371da177e4SLinus Torvalds GEDR2 = GEDR2; 3381da177e4SLinus Torvalds 3391da177e4SLinus Torvalds #ifdef CONFIG_PXA27x 3401da177e4SLinus Torvalds /* And similarly for the extra regs on the PXA27x */ 3411da177e4SLinus Torvalds ICMR2 = 0; 3421da177e4SLinus Torvalds ICLR2 = 0; 3431da177e4SLinus Torvalds GFER3 = 0; 3441da177e4SLinus Torvalds GRER3 = 0; 3451da177e4SLinus Torvalds GEDR3 = GEDR3; 3461da177e4SLinus Torvalds #endif 3471da177e4SLinus Torvalds 3481da177e4SLinus Torvalds /* only unmasked interrupts kick us out of idle */ 3491da177e4SLinus Torvalds ICCR = 1; 3501da177e4SLinus Torvalds 3511da177e4SLinus Torvalds /* GPIO 0 and 1 must have their mask bit always set */ 3521da177e4SLinus Torvalds GPIO_IRQ_mask[0] = 3; 3531da177e4SLinus Torvalds 354486c9551SEric Miao for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { 3551da177e4SLinus Torvalds set_irq_chip(irq, &pxa_internal_chip_low); 35610dd5ce2SRussell King set_irq_handler(irq, handle_level_irq); 3571da177e4SLinus Torvalds set_irq_flags(irq, IRQF_VALID); 3581da177e4SLinus Torvalds } 3591da177e4SLinus Torvalds 3601da177e4SLinus Torvalds #if PXA_INTERNAL_IRQS > 32 3611da177e4SLinus Torvalds for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { 3621da177e4SLinus Torvalds set_irq_chip(irq, &pxa_internal_chip_high); 36310dd5ce2SRussell King set_irq_handler(irq, handle_level_irq); 3641da177e4SLinus Torvalds set_irq_flags(irq, IRQF_VALID); 3651da177e4SLinus Torvalds } 3661da177e4SLinus Torvalds #endif 3671da177e4SLinus Torvalds 3681da177e4SLinus Torvalds for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 3691da177e4SLinus Torvalds set_irq_chip(irq, &pxa_low_gpio_chip); 37010dd5ce2SRussell King set_irq_handler(irq, handle_edge_irq); 3711da177e4SLinus Torvalds set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 3721da177e4SLinus Torvalds } 3731da177e4SLinus Torvalds 3741da177e4SLinus Torvalds for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { 3751da177e4SLinus Torvalds set_irq_chip(irq, &pxa_muxed_gpio_chip); 37610dd5ce2SRussell King set_irq_handler(irq, handle_edge_irq); 3771da177e4SLinus Torvalds set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 3781da177e4SLinus Torvalds } 3791da177e4SLinus Torvalds 3801da177e4SLinus Torvalds /* Install handler for GPIO>=2 edge detect interrupts */ 3811da177e4SLinus Torvalds set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 3821da177e4SLinus Torvalds set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 3831da177e4SLinus Torvalds } 384