11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 4e3630db1Seric miao * Generic PXA IRQ handling 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds #include <linux/init.h> 151da177e4SLinus Torvalds #include <linux/module.h> 161da177e4SLinus Torvalds #include <linux/interrupt.h> 172eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 18a79a9ad9SHaojian Zhuang #include <linux/io.h> 19a79a9ad9SHaojian Zhuang #include <linux/irq.h> 201da177e4SLinus Torvalds 215a567d78SJamie Iles #include <asm/exception.h> 225a567d78SJamie Iles 23a09e64fbSRussell King #include <mach/hardware.h> 24a79a9ad9SHaojian Zhuang #include <mach/irqs.h> 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds #include "generic.h" 271da177e4SLinus Torvalds 2897b09da4SArnd Bergmann #define IRQ_BASE io_p2v(0x40d00000) 29c482ae4dSHaojian Zhuang 30a79a9ad9SHaojian Zhuang #define ICIP (0x000) 31a79a9ad9SHaojian Zhuang #define ICMR (0x004) 32a79a9ad9SHaojian Zhuang #define ICLR (0x008) 33a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 34a79a9ad9SHaojian Zhuang #define ICPR (0x010) 35a79a9ad9SHaojian Zhuang #define ICCR (0x014) 36a79a9ad9SHaojian Zhuang #define ICHP (0x018) 37a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 38a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 39a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 40a551e4f7SEric Miao #define ICHP_VAL_IRQ (1 << 31) 41a551e4f7SEric Miao #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 42a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 43f6fb7af4Seric miao #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 44a79a9ad9SHaojian Zhuang 45a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 461da177e4SLinus Torvalds 471da177e4SLinus Torvalds /* 481da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 491da177e4SLinus Torvalds */ 501da177e4SLinus Torvalds 51f6fb7af4Seric miao static int pxa_internal_irq_nr; 52f6fb7af4Seric miao 53bb71bdd3SHaojian Zhuang static inline int cpu_has_ipr(void) 54bb71bdd3SHaojian Zhuang { 55bb71bdd3SHaojian Zhuang return !cpu_is_pxa25x(); 56bb71bdd3SHaojian Zhuang } 57bb71bdd3SHaojian Zhuang 58a1015a15SEric Miao static inline void __iomem *irq_base(int i) 59a1015a15SEric Miao { 60a1015a15SEric Miao static unsigned long phys_base[] = { 61a1015a15SEric Miao 0x40d00000, 62a1015a15SEric Miao 0x40d0009c, 63a1015a15SEric Miao 0x40d00130, 64a1015a15SEric Miao }; 65a1015a15SEric Miao 6697b09da4SArnd Bergmann return io_p2v(phys_base[i]); 67a1015a15SEric Miao } 68a1015a15SEric Miao 695d284e35SEric Miao void pxa_mask_irq(struct irq_data *d) 701da177e4SLinus Torvalds { 71a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 72a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 73a79a9ad9SHaojian Zhuang 74a3f4c927SLennert Buytenhek icmr &= ~(1 << IRQ_BIT(d->irq)); 75a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 761da177e4SLinus Torvalds } 771da177e4SLinus Torvalds 785d284e35SEric Miao void pxa_unmask_irq(struct irq_data *d) 791da177e4SLinus Torvalds { 80a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 81a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 82a79a9ad9SHaojian Zhuang 83a3f4c927SLennert Buytenhek icmr |= 1 << IRQ_BIT(d->irq); 84a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 851da177e4SLinus Torvalds } 861da177e4SLinus Torvalds 87f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 8838c677cbSDavid Brownell .name = "SC", 89a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 90a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 91a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 921da177e4SLinus Torvalds }; 931da177e4SLinus Torvalds 94a551e4f7SEric Miao asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 95a551e4f7SEric Miao { 96a551e4f7SEric Miao uint32_t icip, icmr, mask; 97a551e4f7SEric Miao 98a551e4f7SEric Miao do { 99a551e4f7SEric Miao icip = __raw_readl(IRQ_BASE + ICIP); 100a551e4f7SEric Miao icmr = __raw_readl(IRQ_BASE + ICMR); 101a551e4f7SEric Miao mask = icip & icmr; 102a551e4f7SEric Miao 103a551e4f7SEric Miao if (mask == 0) 104a551e4f7SEric Miao break; 105a551e4f7SEric Miao 106a551e4f7SEric Miao handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 107a551e4f7SEric Miao } while (1); 108a551e4f7SEric Miao } 109a551e4f7SEric Miao 110a551e4f7SEric Miao asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 111a551e4f7SEric Miao { 112a551e4f7SEric Miao uint32_t ichp; 113a551e4f7SEric Miao 114a551e4f7SEric Miao do { 115a551e4f7SEric Miao __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 116a551e4f7SEric Miao 117a551e4f7SEric Miao if ((ichp & ICHP_VAL_IRQ) == 0) 118a551e4f7SEric Miao break; 119a551e4f7SEric Miao 120a551e4f7SEric Miao handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 121a551e4f7SEric Miao } while (1); 122a551e4f7SEric Miao } 123a551e4f7SEric Miao 124157d2644SHaojian Zhuang void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 12553665a50SEric Miao { 126a79a9ad9SHaojian Zhuang int irq, i, n; 12753665a50SEric Miao 128c482ae4dSHaojian Zhuang BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 129c482ae4dSHaojian Zhuang 130f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 13153665a50SEric Miao 132a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 1331b624fb6SMarek Vasut void __iomem *base = irq_base(n >> 5); 13453665a50SEric Miao 135a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 136a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 137a79a9ad9SHaojian Zhuang for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 138d2c37068SHaojian Zhuang /* initialize interrupt priority */ 139a79a9ad9SHaojian Zhuang if (cpu_has_ipr()) 140a79a9ad9SHaojian Zhuang __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 141d2c37068SHaojian Zhuang 142a79a9ad9SHaojian Zhuang irq = PXA_IRQ(i); 143f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, 144f38c02f3SThomas Gleixner handle_level_irq); 1459323f261SThomas Gleixner irq_set_chip_data(irq, base); 14653665a50SEric Miao set_irq_flags(irq, IRQF_VALID); 14753665a50SEric Miao } 148a79a9ad9SHaojian Zhuang } 149a79a9ad9SHaojian Zhuang 150a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 151a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 15253665a50SEric Miao 153a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 154c95530c7Seric miao } 155c0165504Seric miao 156c0165504Seric miao #ifdef CONFIG_PM 157c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 158c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 159c0165504Seric miao 1602eaa03b5SRafael J. Wysocki static int pxa_irq_suspend(void) 161c0165504Seric miao { 162a79a9ad9SHaojian Zhuang int i; 163f6fb7af4Seric miao 1641b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 165a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 166a79a9ad9SHaojian Zhuang 167a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 168a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 169c0165504Seric miao } 170c70f5a60SEric Miao 171bb71bdd3SHaojian Zhuang if (cpu_has_ipr()) { 172c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 173a79a9ad9SHaojian Zhuang saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); 174c70f5a60SEric Miao } 175c0165504Seric miao 176c0165504Seric miao return 0; 177c0165504Seric miao } 178c0165504Seric miao 1792eaa03b5SRafael J. Wysocki static void pxa_irq_resume(void) 180c0165504Seric miao { 181a79a9ad9SHaojian Zhuang int i; 182f6fb7af4Seric miao 1831b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 184a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 185a79a9ad9SHaojian Zhuang 186a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 187a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 188a79a9ad9SHaojian Zhuang } 189a79a9ad9SHaojian Zhuang 19057879b8cSMarek Vasut if (cpu_has_ipr()) 191c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 192a79a9ad9SHaojian Zhuang __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); 193c70f5a60SEric Miao 194a79a9ad9SHaojian Zhuang __raw_writel(1, IRQ_BASE + ICCR); 195c0165504Seric miao } 196c0165504Seric miao #else 197c0165504Seric miao #define pxa_irq_suspend NULL 198c0165504Seric miao #define pxa_irq_resume NULL 199c0165504Seric miao #endif 200c0165504Seric miao 2012eaa03b5SRafael J. Wysocki struct syscore_ops pxa_irq_syscore_ops = { 202c0165504Seric miao .suspend = pxa_irq_suspend, 203c0165504Seric miao .resume = pxa_irq_resume, 204c0165504Seric miao }; 205