11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * linux/arch/arm/mach-pxa/irq.c 31da177e4SLinus Torvalds * 4e3630db1Seric miao * Generic PXA IRQ handling 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Author: Nicolas Pitre 71da177e4SLinus Torvalds * Created: Jun 15, 2001 81da177e4SLinus Torvalds * Copyright: MontaVista Software Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 111da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds */ 141da177e4SLinus Torvalds #include <linux/init.h> 151da177e4SLinus Torvalds #include <linux/module.h> 161da177e4SLinus Torvalds #include <linux/interrupt.h> 172eaa03b5SRafael J. Wysocki #include <linux/syscore_ops.h> 18a79a9ad9SHaojian Zhuang #include <linux/io.h> 19a79a9ad9SHaojian Zhuang #include <linux/irq.h> 20089d0362SDaniel Mack #include <linux/of_address.h> 21089d0362SDaniel Mack #include <linux/of_irq.h> 221da177e4SLinus Torvalds 235a567d78SJamie Iles #include <asm/exception.h> 245a567d78SJamie Iles 25a09e64fbSRussell King #include <mach/hardware.h> 26a79a9ad9SHaojian Zhuang #include <mach/irqs.h> 271da177e4SLinus Torvalds 281da177e4SLinus Torvalds #include "generic.h" 291da177e4SLinus Torvalds 30a79a9ad9SHaojian Zhuang #define ICIP (0x000) 31a79a9ad9SHaojian Zhuang #define ICMR (0x004) 32a79a9ad9SHaojian Zhuang #define ICLR (0x008) 33a79a9ad9SHaojian Zhuang #define ICFR (0x00c) 34a79a9ad9SHaojian Zhuang #define ICPR (0x010) 35a79a9ad9SHaojian Zhuang #define ICCR (0x014) 36a79a9ad9SHaojian Zhuang #define ICHP (0x018) 37a79a9ad9SHaojian Zhuang #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ 38a79a9ad9SHaojian Zhuang ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ 39a79a9ad9SHaojian Zhuang (0x144 + (((i) - 64) << 2))) 40a551e4f7SEric Miao #define ICHP_VAL_IRQ (1 << 31) 41a551e4f7SEric Miao #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 42a79a9ad9SHaojian Zhuang #define IPR_VALID (1 << 31) 43f6fb7af4Seric miao #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 44a79a9ad9SHaojian Zhuang 45a79a9ad9SHaojian Zhuang #define MAX_INTERNAL_IRQS 128 461da177e4SLinus Torvalds 471da177e4SLinus Torvalds /* 481da177e4SLinus Torvalds * This is for peripheral IRQs internal to the PXA chip. 491da177e4SLinus Torvalds */ 501da177e4SLinus Torvalds 51089d0362SDaniel Mack static void __iomem *pxa_irq_base; 52f6fb7af4Seric miao static int pxa_internal_irq_nr; 53089d0362SDaniel Mack static bool cpu_has_ipr; 54bb71bdd3SHaojian Zhuang 55a1015a15SEric Miao static inline void __iomem *irq_base(int i) 56a1015a15SEric Miao { 57089d0362SDaniel Mack static unsigned long phys_base_offset[] = { 58089d0362SDaniel Mack 0x0, 59089d0362SDaniel Mack 0x9c, 60089d0362SDaniel Mack 0x130, 61a1015a15SEric Miao }; 62a1015a15SEric Miao 63089d0362SDaniel Mack return pxa_irq_base + phys_base_offset[i]; 64a1015a15SEric Miao } 65a1015a15SEric Miao 665d284e35SEric Miao void pxa_mask_irq(struct irq_data *d) 671da177e4SLinus Torvalds { 68a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 69a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 70a79a9ad9SHaojian Zhuang 71a3f4c927SLennert Buytenhek icmr &= ~(1 << IRQ_BIT(d->irq)); 72a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 731da177e4SLinus Torvalds } 741da177e4SLinus Torvalds 755d284e35SEric Miao void pxa_unmask_irq(struct irq_data *d) 761da177e4SLinus Torvalds { 77a3f4c927SLennert Buytenhek void __iomem *base = irq_data_get_irq_chip_data(d); 78a79a9ad9SHaojian Zhuang uint32_t icmr = __raw_readl(base + ICMR); 79a79a9ad9SHaojian Zhuang 80a3f4c927SLennert Buytenhek icmr |= 1 << IRQ_BIT(d->irq); 81a79a9ad9SHaojian Zhuang __raw_writel(icmr, base + ICMR); 821da177e4SLinus Torvalds } 831da177e4SLinus Torvalds 84f6fb7af4Seric miao static struct irq_chip pxa_internal_irq_chip = { 8538c677cbSDavid Brownell .name = "SC", 86a3f4c927SLennert Buytenhek .irq_ack = pxa_mask_irq, 87a3f4c927SLennert Buytenhek .irq_mask = pxa_mask_irq, 88a3f4c927SLennert Buytenhek .irq_unmask = pxa_unmask_irq, 891da177e4SLinus Torvalds }; 901da177e4SLinus Torvalds 91a551e4f7SEric Miao asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) 92a551e4f7SEric Miao { 93a551e4f7SEric Miao uint32_t icip, icmr, mask; 94a551e4f7SEric Miao 95a551e4f7SEric Miao do { 96089d0362SDaniel Mack icip = __raw_readl(pxa_irq_base + ICIP); 97089d0362SDaniel Mack icmr = __raw_readl(pxa_irq_base + ICMR); 98a551e4f7SEric Miao mask = icip & icmr; 99a551e4f7SEric Miao 100a551e4f7SEric Miao if (mask == 0) 101a551e4f7SEric Miao break; 102a551e4f7SEric Miao 103a551e4f7SEric Miao handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); 104a551e4f7SEric Miao } while (1); 105a551e4f7SEric Miao } 106a551e4f7SEric Miao 107a551e4f7SEric Miao asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) 108a551e4f7SEric Miao { 109a551e4f7SEric Miao uint32_t ichp; 110a551e4f7SEric Miao 111a551e4f7SEric Miao do { 112a551e4f7SEric Miao __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); 113a551e4f7SEric Miao 114a551e4f7SEric Miao if ((ichp & ICHP_VAL_IRQ) == 0) 115a551e4f7SEric Miao break; 116a551e4f7SEric Miao 117a551e4f7SEric Miao handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); 118a551e4f7SEric Miao } while (1); 119a551e4f7SEric Miao } 120a551e4f7SEric Miao 121157d2644SHaojian Zhuang void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 12253665a50SEric Miao { 123a79a9ad9SHaojian Zhuang int irq, i, n; 12453665a50SEric Miao 125c482ae4dSHaojian Zhuang BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 126c482ae4dSHaojian Zhuang 127f6fb7af4Seric miao pxa_internal_irq_nr = irq_nr; 128089d0362SDaniel Mack cpu_has_ipr = !cpu_is_pxa25x(); 129089d0362SDaniel Mack pxa_irq_base = io_p2v(0x40d00000); 13053665a50SEric Miao 131a79a9ad9SHaojian Zhuang for (n = 0; n < irq_nr; n += 32) { 1321b624fb6SMarek Vasut void __iomem *base = irq_base(n >> 5); 13353665a50SEric Miao 134a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); /* disable all IRQs */ 135a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 136a79a9ad9SHaojian Zhuang for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 137d2c37068SHaojian Zhuang /* initialize interrupt priority */ 138089d0362SDaniel Mack if (cpu_has_ipr) 139089d0362SDaniel Mack __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i)); 140d2c37068SHaojian Zhuang 141a79a9ad9SHaojian Zhuang irq = PXA_IRQ(i); 142f38c02f3SThomas Gleixner irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, 143f38c02f3SThomas Gleixner handle_level_irq); 1449323f261SThomas Gleixner irq_set_chip_data(irq, base); 14553665a50SEric Miao set_irq_flags(irq, IRQF_VALID); 14653665a50SEric Miao } 147a79a9ad9SHaojian Zhuang } 148a79a9ad9SHaojian Zhuang 149a79a9ad9SHaojian Zhuang /* only unmasked interrupts kick us out of idle */ 150a79a9ad9SHaojian Zhuang __raw_writel(1, irq_base(0) + ICCR); 15153665a50SEric Miao 152a3f4c927SLennert Buytenhek pxa_internal_irq_chip.irq_set_wake = fn; 153c95530c7Seric miao } 154c0165504Seric miao 155c0165504Seric miao #ifdef CONFIG_PM 156c482ae4dSHaojian Zhuang static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 157c482ae4dSHaojian Zhuang static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 158c0165504Seric miao 1592eaa03b5SRafael J. Wysocki static int pxa_irq_suspend(void) 160c0165504Seric miao { 161a79a9ad9SHaojian Zhuang int i; 162f6fb7af4Seric miao 1631b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 164a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 165a79a9ad9SHaojian Zhuang 166a79a9ad9SHaojian Zhuang saved_icmr[i] = __raw_readl(base + ICMR); 167a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICMR); 168c0165504Seric miao } 169c70f5a60SEric Miao 170089d0362SDaniel Mack if (cpu_has_ipr) { 171c482ae4dSHaojian Zhuang for (i = 0; i < pxa_internal_irq_nr; i++) 172089d0362SDaniel Mack saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); 173c70f5a60SEric Miao } 174c0165504Seric miao 175c0165504Seric miao return 0; 176c0165504Seric miao } 177c0165504Seric miao 1782eaa03b5SRafael J. Wysocki static void pxa_irq_resume(void) 179c0165504Seric miao { 180a79a9ad9SHaojian Zhuang int i; 181f6fb7af4Seric miao 1821b624fb6SMarek Vasut for (i = 0; i < pxa_internal_irq_nr / 32; i++) { 183a79a9ad9SHaojian Zhuang void __iomem *base = irq_base(i); 184a79a9ad9SHaojian Zhuang 185a79a9ad9SHaojian Zhuang __raw_writel(saved_icmr[i], base + ICMR); 186a79a9ad9SHaojian Zhuang __raw_writel(0, base + ICLR); 187a79a9ad9SHaojian Zhuang } 188a79a9ad9SHaojian Zhuang 189089d0362SDaniel Mack if (cpu_has_ipr) 190c70f5a60SEric Miao for (i = 0; i < pxa_internal_irq_nr; i++) 191089d0362SDaniel Mack __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); 192c70f5a60SEric Miao 193089d0362SDaniel Mack __raw_writel(1, pxa_irq_base + ICCR); 194c0165504Seric miao } 195c0165504Seric miao #else 196c0165504Seric miao #define pxa_irq_suspend NULL 197c0165504Seric miao #define pxa_irq_resume NULL 198c0165504Seric miao #endif 199c0165504Seric miao 2002eaa03b5SRafael J. Wysocki struct syscore_ops pxa_irq_syscore_ops = { 201c0165504Seric miao .suspend = pxa_irq_suspend, 202c0165504Seric miao .resume = pxa_irq_resume, 203c0165504Seric miao }; 204089d0362SDaniel Mack 205089d0362SDaniel Mack #ifdef CONFIG_OF 206089d0362SDaniel Mack static struct irq_domain *pxa_irq_domain; 207089d0362SDaniel Mack 208089d0362SDaniel Mack static int pxa_irq_map(struct irq_domain *h, unsigned int virq, 209089d0362SDaniel Mack irq_hw_number_t hw) 210089d0362SDaniel Mack { 211089d0362SDaniel Mack void __iomem *base = irq_base(hw / 32); 212089d0362SDaniel Mack 213089d0362SDaniel Mack /* initialize interrupt priority */ 214089d0362SDaniel Mack if (cpu_has_ipr) 215089d0362SDaniel Mack __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); 216089d0362SDaniel Mack 217089d0362SDaniel Mack irq_set_chip_and_handler(hw, &pxa_internal_irq_chip, 218089d0362SDaniel Mack handle_level_irq); 219089d0362SDaniel Mack irq_set_chip_data(hw, base); 220089d0362SDaniel Mack set_irq_flags(hw, IRQF_VALID); 221089d0362SDaniel Mack 222089d0362SDaniel Mack return 0; 223089d0362SDaniel Mack } 224089d0362SDaniel Mack 225089d0362SDaniel Mack static struct irq_domain_ops pxa_irq_ops = { 226089d0362SDaniel Mack .map = pxa_irq_map, 227089d0362SDaniel Mack .xlate = irq_domain_xlate_onecell, 228089d0362SDaniel Mack }; 229089d0362SDaniel Mack 230089d0362SDaniel Mack static const struct of_device_id intc_ids[] __initconst = { 231089d0362SDaniel Mack { .compatible = "marvell,pxa-intc", }, 232089d0362SDaniel Mack {} 233089d0362SDaniel Mack }; 234089d0362SDaniel Mack 235089d0362SDaniel Mack void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) 236089d0362SDaniel Mack { 237089d0362SDaniel Mack struct device_node *node; 238089d0362SDaniel Mack const struct of_device_id *of_id; 239089d0362SDaniel Mack struct pxa_intc_conf *conf; 240089d0362SDaniel Mack struct resource res; 241089d0362SDaniel Mack int n, ret; 242089d0362SDaniel Mack 243089d0362SDaniel Mack node = of_find_matching_node(NULL, intc_ids); 244089d0362SDaniel Mack if (!node) { 245089d0362SDaniel Mack pr_err("Failed to find interrupt controller in arch-pxa\n"); 246089d0362SDaniel Mack return; 247089d0362SDaniel Mack } 248089d0362SDaniel Mack of_id = of_match_node(intc_ids, node); 249089d0362SDaniel Mack conf = of_id->data; 250089d0362SDaniel Mack 251089d0362SDaniel Mack ret = of_property_read_u32(node, "marvell,intc-nr-irqs", 252089d0362SDaniel Mack &pxa_internal_irq_nr); 253089d0362SDaniel Mack if (ret) { 254089d0362SDaniel Mack pr_err("Not found marvell,intc-nr-irqs property\n"); 255089d0362SDaniel Mack return; 256089d0362SDaniel Mack } 257089d0362SDaniel Mack 258089d0362SDaniel Mack ret = of_address_to_resource(node, 0, &res); 259089d0362SDaniel Mack if (ret < 0) { 260089d0362SDaniel Mack pr_err("No registers defined for node\n"); 261089d0362SDaniel Mack return; 262089d0362SDaniel Mack } 263089d0362SDaniel Mack pxa_irq_base = io_p2v(res.start); 264089d0362SDaniel Mack 265089d0362SDaniel Mack if (of_find_property(node, "marvell,intc-priority", NULL)) 266089d0362SDaniel Mack cpu_has_ipr = 1; 267089d0362SDaniel Mack 268089d0362SDaniel Mack ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0); 269089d0362SDaniel Mack if (ret < 0) { 270089d0362SDaniel Mack pr_err("Failed to allocate IRQ numbers\n"); 271089d0362SDaniel Mack return; 272089d0362SDaniel Mack } 273089d0362SDaniel Mack 274089d0362SDaniel Mack pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0, 275089d0362SDaniel Mack &pxa_irq_ops, NULL); 276089d0362SDaniel Mack if (!pxa_irq_domain) 277089d0362SDaniel Mack panic("Unable to add PXA IRQ domain\n"); 278089d0362SDaniel Mack 279089d0362SDaniel Mack irq_set_default_host(pxa_irq_domain); 280089d0362SDaniel Mack 281089d0362SDaniel Mack for (n = 0; n < pxa_internal_irq_nr; n += 32) { 282089d0362SDaniel Mack void __iomem *base = irq_base(n >> 5); 283089d0362SDaniel Mack 284089d0362SDaniel Mack __raw_writel(0, base + ICMR); /* disable all IRQs */ 285089d0362SDaniel Mack __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 286089d0362SDaniel Mack } 287089d0362SDaniel Mack 288089d0362SDaniel Mack /* only unmasked interrupts kick us out of idle */ 289089d0362SDaniel Mack __raw_writel(1, irq_base(0) + ICCR); 290089d0362SDaniel Mack 291089d0362SDaniel Mack pxa_internal_irq_chip.irq_set_wake = fn; 292089d0362SDaniel Mack } 293089d0362SDaniel Mack #endif /* CONFIG_OF */ 294