xref: /openbmc/linux/arch/arm/mach-pxa/devices.c (revision f42b3800) 
1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/platform_device.h>
5 #include <linux/dma-mapping.h>
6 
7 #include <asm/arch/gpio.h>
8 #include <asm/arch/udc.h>
9 #include <asm/arch/pxafb.h>
10 #include <asm/arch/mmc.h>
11 #include <asm/arch/irda.h>
12 #include <asm/arch/i2c.h>
13 #include <asm/arch/ohci.h>
14 
15 #include "devices.h"
16 
17 void __init pxa_register_device(struct platform_device *dev, void *data)
18 {
19 	int ret;
20 
21 	dev->dev.platform_data = data;
22 
23 	ret = platform_device_register(dev);
24 	if (ret)
25 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
26 }
27 
28 static struct resource pxamci_resources[] = {
29 	[0] = {
30 		.start	= 0x41100000,
31 		.end	= 0x41100fff,
32 		.flags	= IORESOURCE_MEM,
33 	},
34 	[1] = {
35 		.start	= IRQ_MMC,
36 		.end	= IRQ_MMC,
37 		.flags	= IORESOURCE_IRQ,
38 	},
39 	[2] = {
40 		.start	= 21,
41 		.end	= 21,
42 		.flags	= IORESOURCE_DMA,
43 	},
44 	[3] = {
45 		.start	= 22,
46 		.end	= 22,
47 		.flags	= IORESOURCE_DMA,
48 	},
49 };
50 
51 static u64 pxamci_dmamask = 0xffffffffUL;
52 
53 struct platform_device pxa_device_mci = {
54 	.name		= "pxa2xx-mci",
55 	.id		= 0,
56 	.dev		= {
57 		.dma_mask = &pxamci_dmamask,
58 		.coherent_dma_mask = 0xffffffff,
59 	},
60 	.num_resources	= ARRAY_SIZE(pxamci_resources),
61 	.resource	= pxamci_resources,
62 };
63 
64 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
65 {
66 	pxa_register_device(&pxa_device_mci, info);
67 }
68 
69 
70 static struct pxa2xx_udc_mach_info pxa_udc_info;
71 
72 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
73 {
74 	memcpy(&pxa_udc_info, info, sizeof *info);
75 }
76 
77 static struct resource pxa2xx_udc_resources[] = {
78 	[0] = {
79 		.start	= 0x40600000,
80 		.end	= 0x4060ffff,
81 		.flags	= IORESOURCE_MEM,
82 	},
83 	[1] = {
84 		.start	= IRQ_USB,
85 		.end	= IRQ_USB,
86 		.flags	= IORESOURCE_IRQ,
87 	},
88 };
89 
90 static u64 udc_dma_mask = ~(u32)0;
91 
92 struct platform_device pxa_device_udc = {
93 	.name		= "pxa2xx-udc",
94 	.id		= -1,
95 	.resource	= pxa2xx_udc_resources,
96 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
97 	.dev		=  {
98 		.platform_data	= &pxa_udc_info,
99 		.dma_mask	= &udc_dma_mask,
100 	}
101 };
102 
103 static struct resource pxafb_resources[] = {
104 	[0] = {
105 		.start	= 0x44000000,
106 		.end	= 0x4400ffff,
107 		.flags	= IORESOURCE_MEM,
108 	},
109 	[1] = {
110 		.start	= IRQ_LCD,
111 		.end	= IRQ_LCD,
112 		.flags	= IORESOURCE_IRQ,
113 	},
114 };
115 
116 static u64 fb_dma_mask = ~(u64)0;
117 
118 struct platform_device pxa_device_fb = {
119 	.name		= "pxa2xx-fb",
120 	.id		= -1,
121 	.dev		= {
122 		.dma_mask	= &fb_dma_mask,
123 		.coherent_dma_mask = 0xffffffff,
124 	},
125 	.num_resources	= ARRAY_SIZE(pxafb_resources),
126 	.resource	= pxafb_resources,
127 };
128 
129 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
130 {
131 	pxa_register_device(&pxa_device_fb, info);
132 }
133 
134 void __init set_pxa_fb_parent(struct device *parent_dev)
135 {
136 	pxa_device_fb.dev.parent = parent_dev;
137 }
138 
139 static struct resource pxa_resource_ffuart[] = {
140 	{
141 		.start	= __PREG(FFUART),
142 		.end	= __PREG(FFUART) + 35,
143 		.flags	= IORESOURCE_MEM,
144 	}, {
145 		.start	= IRQ_FFUART,
146 		.end	= IRQ_FFUART,
147 		.flags	= IORESOURCE_IRQ,
148 	}
149 };
150 
151 struct platform_device pxa_device_ffuart= {
152 	.name		= "pxa2xx-uart",
153 	.id		= 0,
154 	.resource	= pxa_resource_ffuart,
155 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
156 };
157 
158 static struct resource pxa_resource_btuart[] = {
159 	{
160 		.start	= __PREG(BTUART),
161 		.end	= __PREG(BTUART) + 35,
162 		.flags	= IORESOURCE_MEM,
163 	}, {
164 		.start	= IRQ_BTUART,
165 		.end	= IRQ_BTUART,
166 		.flags	= IORESOURCE_IRQ,
167 	}
168 };
169 
170 struct platform_device pxa_device_btuart = {
171 	.name		= "pxa2xx-uart",
172 	.id		= 1,
173 	.resource	= pxa_resource_btuart,
174 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
175 };
176 
177 static struct resource pxa_resource_stuart[] = {
178 	{
179 		.start	= __PREG(STUART),
180 		.end	= __PREG(STUART) + 35,
181 		.flags	= IORESOURCE_MEM,
182 	}, {
183 		.start	= IRQ_STUART,
184 		.end	= IRQ_STUART,
185 		.flags	= IORESOURCE_IRQ,
186 	}
187 };
188 
189 struct platform_device pxa_device_stuart = {
190 	.name		= "pxa2xx-uart",
191 	.id		= 2,
192 	.resource	= pxa_resource_stuart,
193 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
194 };
195 
196 static struct resource pxa_resource_hwuart[] = {
197 	{
198 		.start	= __PREG(HWUART),
199 		.end	= __PREG(HWUART) + 47,
200 		.flags	= IORESOURCE_MEM,
201 	}, {
202 		.start	= IRQ_HWUART,
203 		.end	= IRQ_HWUART,
204 		.flags	= IORESOURCE_IRQ,
205 	}
206 };
207 
208 struct platform_device pxa_device_hwuart = {
209 	.name		= "pxa2xx-uart",
210 	.id		= 3,
211 	.resource	= pxa_resource_hwuart,
212 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
213 };
214 
215 static struct resource pxai2c_resources[] = {
216 	{
217 		.start	= 0x40301680,
218 		.end	= 0x403016a3,
219 		.flags	= IORESOURCE_MEM,
220 	}, {
221 		.start	= IRQ_I2C,
222 		.end	= IRQ_I2C,
223 		.flags	= IORESOURCE_IRQ,
224 	},
225 };
226 
227 struct platform_device pxa_device_i2c = {
228 	.name		= "pxa2xx-i2c",
229 	.id		= 0,
230 	.resource	= pxai2c_resources,
231 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
232 };
233 
234 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
235 {
236 	pxa_register_device(&pxa_device_i2c, info);
237 }
238 
239 static struct resource pxai2s_resources[] = {
240 	{
241 		.start	= 0x40400000,
242 		.end	= 0x40400083,
243 		.flags	= IORESOURCE_MEM,
244 	}, {
245 		.start	= IRQ_I2S,
246 		.end	= IRQ_I2S,
247 		.flags	= IORESOURCE_IRQ,
248 	},
249 };
250 
251 struct platform_device pxa_device_i2s = {
252 	.name		= "pxa2xx-i2s",
253 	.id		= -1,
254 	.resource	= pxai2s_resources,
255 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
256 };
257 
258 static u64 pxaficp_dmamask = ~(u32)0;
259 
260 struct platform_device pxa_device_ficp = {
261 	.name		= "pxa2xx-ir",
262 	.id		= -1,
263 	.dev		= {
264 		.dma_mask = &pxaficp_dmamask,
265 		.coherent_dma_mask = 0xffffffff,
266 	},
267 };
268 
269 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
270 {
271 	pxa_register_device(&pxa_device_ficp, info);
272 }
273 
274 struct platform_device pxa_device_rtc = {
275 	.name		= "sa1100-rtc",
276 	.id		= -1,
277 };
278 
279 #ifdef CONFIG_PXA25x
280 
281 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
282 
283 static struct resource pxa25x_resource_ssp[] = {
284 	[0] = {
285 		.start	= 0x41000000,
286 		.end	= 0x4100001f,
287 		.flags	= IORESOURCE_MEM,
288 	},
289 	[1] = {
290 		.start	= IRQ_SSP,
291 		.end	= IRQ_SSP,
292 		.flags	= IORESOURCE_IRQ,
293 	},
294 	[2] = {
295 		/* DRCMR for RX */
296 		.start	= 13,
297 		.end	= 13,
298 		.flags	= IORESOURCE_DMA,
299 	},
300 	[3] = {
301 		/* DRCMR for TX */
302 		.start	= 14,
303 		.end	= 14,
304 		.flags	= IORESOURCE_DMA,
305 	},
306 };
307 
308 struct platform_device pxa25x_device_ssp = {
309 	.name		= "pxa25x-ssp",
310 	.id		= 0,
311 	.dev		= {
312 		.dma_mask = &pxa25x_ssp_dma_mask,
313 		.coherent_dma_mask = DMA_BIT_MASK(32),
314 	},
315 	.resource	= pxa25x_resource_ssp,
316 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
317 };
318 
319 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
320 
321 static struct resource pxa25x_resource_nssp[] = {
322 	[0] = {
323 		.start	= 0x41400000,
324 		.end	= 0x4140002f,
325 		.flags	= IORESOURCE_MEM,
326 	},
327 	[1] = {
328 		.start	= IRQ_NSSP,
329 		.end	= IRQ_NSSP,
330 		.flags	= IORESOURCE_IRQ,
331 	},
332 	[2] = {
333 		/* DRCMR for RX */
334 		.start	= 15,
335 		.end	= 15,
336 		.flags	= IORESOURCE_DMA,
337 	},
338 	[3] = {
339 		/* DRCMR for TX */
340 		.start	= 16,
341 		.end	= 16,
342 		.flags	= IORESOURCE_DMA,
343 	},
344 };
345 
346 struct platform_device pxa25x_device_nssp = {
347 	.name		= "pxa25x-nssp",
348 	.id		= 1,
349 	.dev		= {
350 		.dma_mask = &pxa25x_nssp_dma_mask,
351 		.coherent_dma_mask = DMA_BIT_MASK(32),
352 	},
353 	.resource	= pxa25x_resource_nssp,
354 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
355 };
356 
357 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
358 
359 static struct resource pxa25x_resource_assp[] = {
360 	[0] = {
361 		.start	= 0x41500000,
362 		.end	= 0x4150002f,
363 		.flags	= IORESOURCE_MEM,
364 	},
365 	[1] = {
366 		.start	= IRQ_ASSP,
367 		.end	= IRQ_ASSP,
368 		.flags	= IORESOURCE_IRQ,
369 	},
370 	[2] = {
371 		/* DRCMR for RX */
372 		.start	= 23,
373 		.end	= 23,
374 		.flags	= IORESOURCE_DMA,
375 	},
376 	[3] = {
377 		/* DRCMR for TX */
378 		.start	= 24,
379 		.end	= 24,
380 		.flags	= IORESOURCE_DMA,
381 	},
382 };
383 
384 struct platform_device pxa25x_device_assp = {
385 	/* ASSP is basically equivalent to NSSP */
386 	.name		= "pxa25x-nssp",
387 	.id		= 2,
388 	.dev		= {
389 		.dma_mask = &pxa25x_assp_dma_mask,
390 		.coherent_dma_mask = DMA_BIT_MASK(32),
391 	},
392 	.resource	= pxa25x_resource_assp,
393 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
394 };
395 #endif /* CONFIG_PXA25x */
396 
397 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
398 
399 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
400 
401 static struct resource pxa27x_resource_ohci[] = {
402 	[0] = {
403 		.start  = 0x4C000000,
404 		.end    = 0x4C00ff6f,
405 		.flags  = IORESOURCE_MEM,
406 	},
407 	[1] = {
408 		.start  = IRQ_USBH1,
409 		.end    = IRQ_USBH1,
410 		.flags  = IORESOURCE_IRQ,
411 	},
412 };
413 
414 struct platform_device pxa27x_device_ohci = {
415 	.name		= "pxa27x-ohci",
416 	.id		= -1,
417 	.dev		= {
418 		.dma_mask = &pxa27x_ohci_dma_mask,
419 		.coherent_dma_mask = DMA_BIT_MASK(32),
420 	},
421 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
422 	.resource       = pxa27x_resource_ohci,
423 };
424 
425 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
426 {
427 	pxa_register_device(&pxa27x_device_ohci, info);
428 }
429 
430 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
431 
432 static struct resource pxa27x_resource_ssp1[] = {
433 	[0] = {
434 		.start	= 0x41000000,
435 		.end	= 0x4100003f,
436 		.flags	= IORESOURCE_MEM,
437 	},
438 	[1] = {
439 		.start	= IRQ_SSP,
440 		.end	= IRQ_SSP,
441 		.flags	= IORESOURCE_IRQ,
442 	},
443 	[2] = {
444 		/* DRCMR for RX */
445 		.start	= 13,
446 		.end	= 13,
447 		.flags	= IORESOURCE_DMA,
448 	},
449 	[3] = {
450 		/* DRCMR for TX */
451 		.start	= 14,
452 		.end	= 14,
453 		.flags	= IORESOURCE_DMA,
454 	},
455 };
456 
457 struct platform_device pxa27x_device_ssp1 = {
458 	.name		= "pxa27x-ssp",
459 	.id		= 0,
460 	.dev		= {
461 		.dma_mask = &pxa27x_ssp1_dma_mask,
462 		.coherent_dma_mask = DMA_BIT_MASK(32),
463 	},
464 	.resource	= pxa27x_resource_ssp1,
465 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
466 };
467 
468 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
469 
470 static struct resource pxa27x_resource_ssp2[] = {
471 	[0] = {
472 		.start	= 0x41700000,
473 		.end	= 0x4170003f,
474 		.flags	= IORESOURCE_MEM,
475 	},
476 	[1] = {
477 		.start	= IRQ_SSP2,
478 		.end	= IRQ_SSP2,
479 		.flags	= IORESOURCE_IRQ,
480 	},
481 	[2] = {
482 		/* DRCMR for RX */
483 		.start	= 15,
484 		.end	= 15,
485 		.flags	= IORESOURCE_DMA,
486 	},
487 	[3] = {
488 		/* DRCMR for TX */
489 		.start	= 16,
490 		.end	= 16,
491 		.flags	= IORESOURCE_DMA,
492 	},
493 };
494 
495 struct platform_device pxa27x_device_ssp2 = {
496 	.name		= "pxa27x-ssp",
497 	.id		= 1,
498 	.dev		= {
499 		.dma_mask = &pxa27x_ssp2_dma_mask,
500 		.coherent_dma_mask = DMA_BIT_MASK(32),
501 	},
502 	.resource	= pxa27x_resource_ssp2,
503 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
504 };
505 
506 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
507 
508 static struct resource pxa27x_resource_ssp3[] = {
509 	[0] = {
510 		.start	= 0x41900000,
511 		.end	= 0x4190003f,
512 		.flags	= IORESOURCE_MEM,
513 	},
514 	[1] = {
515 		.start	= IRQ_SSP3,
516 		.end	= IRQ_SSP3,
517 		.flags	= IORESOURCE_IRQ,
518 	},
519 	[2] = {
520 		/* DRCMR for RX */
521 		.start	= 66,
522 		.end	= 66,
523 		.flags	= IORESOURCE_DMA,
524 	},
525 	[3] = {
526 		/* DRCMR for TX */
527 		.start	= 67,
528 		.end	= 67,
529 		.flags	= IORESOURCE_DMA,
530 	},
531 };
532 
533 struct platform_device pxa27x_device_ssp3 = {
534 	.name		= "pxa27x-ssp",
535 	.id		= 2,
536 	.dev		= {
537 		.dma_mask = &pxa27x_ssp3_dma_mask,
538 		.coherent_dma_mask = DMA_BIT_MASK(32),
539 	},
540 	.resource	= pxa27x_resource_ssp3,
541 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
542 };
543 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
544 
545 #ifdef CONFIG_PXA3xx
546 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
547 
548 static struct resource pxa3xx_resource_ssp4[] = {
549 	[0] = {
550 		.start	= 0x41a00000,
551 		.end	= 0x41a0003f,
552 		.flags	= IORESOURCE_MEM,
553 	},
554 	[1] = {
555 		.start	= IRQ_SSP4,
556 		.end	= IRQ_SSP4,
557 		.flags	= IORESOURCE_IRQ,
558 	},
559 	[2] = {
560 		/* DRCMR for RX */
561 		.start	= 2,
562 		.end	= 2,
563 		.flags	= IORESOURCE_DMA,
564 	},
565 	[3] = {
566 		/* DRCMR for TX */
567 		.start	= 3,
568 		.end	= 3,
569 		.flags	= IORESOURCE_DMA,
570 	},
571 };
572 
573 struct platform_device pxa3xx_device_ssp4 = {
574 	/* PXA3xx SSP is basically equivalent to PXA27x */
575 	.name		= "pxa27x-ssp",
576 	.id		= 3,
577 	.dev		= {
578 		.dma_mask = &pxa3xx_ssp4_dma_mask,
579 		.coherent_dma_mask = DMA_BIT_MASK(32),
580 	},
581 	.resource	= pxa3xx_resource_ssp4,
582 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
583 };
584 
585 static struct resource pxa3xx_resources_mci2[] = {
586 	[0] = {
587 		.start	= 0x42000000,
588 		.end	= 0x42000fff,
589 		.flags	= IORESOURCE_MEM,
590 	},
591 	[1] = {
592 		.start	= IRQ_MMC2,
593 		.end	= IRQ_MMC2,
594 		.flags	= IORESOURCE_IRQ,
595 	},
596 	[2] = {
597 		.start	= 93,
598 		.end	= 93,
599 		.flags	= IORESOURCE_DMA,
600 	},
601 	[3] = {
602 		.start	= 94,
603 		.end	= 94,
604 		.flags	= IORESOURCE_DMA,
605 	},
606 };
607 
608 struct platform_device pxa3xx_device_mci2 = {
609 	.name		= "pxa2xx-mci",
610 	.id		= 1,
611 	.dev		= {
612 		.dma_mask = &pxamci_dmamask,
613 		.coherent_dma_mask =	0xffffffff,
614 	},
615 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
616 	.resource	= pxa3xx_resources_mci2,
617 };
618 
619 void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
620 {
621 	pxa_register_device(&pxa3xx_device_mci2, info);
622 }
623 
624 static struct resource pxa3xx_resources_mci3[] = {
625 	[0] = {
626 		.start	= 0x42500000,
627 		.end	= 0x42500fff,
628 		.flags	= IORESOURCE_MEM,
629 	},
630 	[1] = {
631 		.start	= IRQ_MMC3,
632 		.end	= IRQ_MMC3,
633 		.flags	= IORESOURCE_IRQ,
634 	},
635 	[2] = {
636 		.start	= 100,
637 		.end	= 100,
638 		.flags	= IORESOURCE_DMA,
639 	},
640 	[3] = {
641 		.start	= 101,
642 		.end	= 101,
643 		.flags	= IORESOURCE_DMA,
644 	},
645 };
646 
647 struct platform_device pxa3xx_device_mci3 = {
648 	.name		= "pxa2xx-mci",
649 	.id		= 2,
650 	.dev		= {
651 		.dma_mask = &pxamci_dmamask,
652 		.coherent_dma_mask = 0xffffffff,
653 	},
654 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
655 	.resource	= pxa3xx_resources_mci3,
656 };
657 
658 void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
659 {
660 	pxa_register_device(&pxa3xx_device_mci3, info);
661 }
662 
663 #endif /* CONFIG_PXA3xx */
664