xref: /openbmc/linux/arch/arm/mach-pxa/devices.c (revision a09d2831)
1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/platform_device.h>
5 #include <linux/dma-mapping.h>
6 
7 #include <mach/udc.h>
8 #include <mach/pxafb.h>
9 #include <mach/mmc.h>
10 #include <mach/irda.h>
11 #include <mach/ohci.h>
12 #include <mach/pxa27x_keypad.h>
13 #include <mach/pxa2xx_spi.h>
14 #include <mach/camera.h>
15 #include <mach/audio.h>
16 #include <mach/hardware.h>
17 #include <plat/i2c.h>
18 #include <plat/pxa3xx_nand.h>
19 
20 #include "devices.h"
21 #include "generic.h"
22 
23 void __init pxa_register_device(struct platform_device *dev, void *data)
24 {
25 	int ret;
26 
27 	dev->dev.platform_data = data;
28 
29 	ret = platform_device_register(dev);
30 	if (ret)
31 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
32 }
33 
34 static struct resource pxamci_resources[] = {
35 	[0] = {
36 		.start	= 0x41100000,
37 		.end	= 0x41100fff,
38 		.flags	= IORESOURCE_MEM,
39 	},
40 	[1] = {
41 		.start	= IRQ_MMC,
42 		.end	= IRQ_MMC,
43 		.flags	= IORESOURCE_IRQ,
44 	},
45 	[2] = {
46 		.start	= 21,
47 		.end	= 21,
48 		.flags	= IORESOURCE_DMA,
49 	},
50 	[3] = {
51 		.start	= 22,
52 		.end	= 22,
53 		.flags	= IORESOURCE_DMA,
54 	},
55 };
56 
57 static u64 pxamci_dmamask = 0xffffffffUL;
58 
59 struct platform_device pxa_device_mci = {
60 	.name		= "pxa2xx-mci",
61 	.id		= 0,
62 	.dev		= {
63 		.dma_mask = &pxamci_dmamask,
64 		.coherent_dma_mask = 0xffffffff,
65 	},
66 	.num_resources	= ARRAY_SIZE(pxamci_resources),
67 	.resource	= pxamci_resources,
68 };
69 
70 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
71 {
72 	pxa_register_device(&pxa_device_mci, info);
73 }
74 
75 
76 static struct pxa2xx_udc_mach_info pxa_udc_info = {
77 	.gpio_pullup = -1,
78 	.gpio_vbus   = -1,
79 };
80 
81 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
82 {
83 	memcpy(&pxa_udc_info, info, sizeof *info);
84 }
85 
86 static struct resource pxa2xx_udc_resources[] = {
87 	[0] = {
88 		.start	= 0x40600000,
89 		.end	= 0x4060ffff,
90 		.flags	= IORESOURCE_MEM,
91 	},
92 	[1] = {
93 		.start	= IRQ_USB,
94 		.end	= IRQ_USB,
95 		.flags	= IORESOURCE_IRQ,
96 	},
97 };
98 
99 static u64 udc_dma_mask = ~(u32)0;
100 
101 struct platform_device pxa25x_device_udc = {
102 	.name		= "pxa25x-udc",
103 	.id		= -1,
104 	.resource	= pxa2xx_udc_resources,
105 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
106 	.dev		=  {
107 		.platform_data	= &pxa_udc_info,
108 		.dma_mask	= &udc_dma_mask,
109 	}
110 };
111 
112 struct platform_device pxa27x_device_udc = {
113 	.name		= "pxa27x-udc",
114 	.id		= -1,
115 	.resource	= pxa2xx_udc_resources,
116 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
117 	.dev		=  {
118 		.platform_data	= &pxa_udc_info,
119 		.dma_mask	= &udc_dma_mask,
120 	}
121 };
122 
123 static struct resource pxafb_resources[] = {
124 	[0] = {
125 		.start	= 0x44000000,
126 		.end	= 0x4400ffff,
127 		.flags	= IORESOURCE_MEM,
128 	},
129 	[1] = {
130 		.start	= IRQ_LCD,
131 		.end	= IRQ_LCD,
132 		.flags	= IORESOURCE_IRQ,
133 	},
134 };
135 
136 static u64 fb_dma_mask = ~(u64)0;
137 
138 struct platform_device pxa_device_fb = {
139 	.name		= "pxa2xx-fb",
140 	.id		= -1,
141 	.dev		= {
142 		.dma_mask	= &fb_dma_mask,
143 		.coherent_dma_mask = 0xffffffff,
144 	},
145 	.num_resources	= ARRAY_SIZE(pxafb_resources),
146 	.resource	= pxafb_resources,
147 };
148 
149 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
150 {
151 	pxa_register_device(&pxa_device_fb, info);
152 }
153 
154 void __init set_pxa_fb_parent(struct device *parent_dev)
155 {
156 	pxa_device_fb.dev.parent = parent_dev;
157 }
158 
159 static struct resource pxa_resource_ffuart[] = {
160 	{
161 		.start	= 0x40100000,
162 		.end	= 0x40100023,
163 		.flags	= IORESOURCE_MEM,
164 	}, {
165 		.start	= IRQ_FFUART,
166 		.end	= IRQ_FFUART,
167 		.flags	= IORESOURCE_IRQ,
168 	}
169 };
170 
171 struct platform_device pxa_device_ffuart = {
172 	.name		= "pxa2xx-uart",
173 	.id		= 0,
174 	.resource	= pxa_resource_ffuart,
175 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
176 };
177 
178 void __init pxa_set_ffuart_info(void *info)
179 {
180 	pxa_register_device(&pxa_device_ffuart, info);
181 }
182 
183 static struct resource pxa_resource_btuart[] = {
184 	{
185 		.start	= 0x40200000,
186 		.end	= 0x40200023,
187 		.flags	= IORESOURCE_MEM,
188 	}, {
189 		.start	= IRQ_BTUART,
190 		.end	= IRQ_BTUART,
191 		.flags	= IORESOURCE_IRQ,
192 	}
193 };
194 
195 struct platform_device pxa_device_btuart = {
196 	.name		= "pxa2xx-uart",
197 	.id		= 1,
198 	.resource	= pxa_resource_btuart,
199 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
200 };
201 
202 void __init pxa_set_btuart_info(void *info)
203 {
204 	pxa_register_device(&pxa_device_btuart, info);
205 }
206 
207 static struct resource pxa_resource_stuart[] = {
208 	{
209 		.start	= 0x40700000,
210 		.end	= 0x40700023,
211 		.flags	= IORESOURCE_MEM,
212 	}, {
213 		.start	= IRQ_STUART,
214 		.end	= IRQ_STUART,
215 		.flags	= IORESOURCE_IRQ,
216 	}
217 };
218 
219 struct platform_device pxa_device_stuart = {
220 	.name		= "pxa2xx-uart",
221 	.id		= 2,
222 	.resource	= pxa_resource_stuart,
223 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
224 };
225 
226 void __init pxa_set_stuart_info(void *info)
227 {
228 	pxa_register_device(&pxa_device_stuart, info);
229 }
230 
231 static struct resource pxa_resource_hwuart[] = {
232 	{
233 		.start	= 0x41600000,
234 		.end	= 0x4160002F,
235 		.flags	= IORESOURCE_MEM,
236 	}, {
237 		.start	= IRQ_HWUART,
238 		.end	= IRQ_HWUART,
239 		.flags	= IORESOURCE_IRQ,
240 	}
241 };
242 
243 struct platform_device pxa_device_hwuart = {
244 	.name		= "pxa2xx-uart",
245 	.id		= 3,
246 	.resource	= pxa_resource_hwuart,
247 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
248 };
249 
250 void __init pxa_set_hwuart_info(void *info)
251 {
252 	if (cpu_is_pxa255())
253 		pxa_register_device(&pxa_device_hwuart, info);
254 	else
255 		pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
256 }
257 
258 static struct resource pxai2c_resources[] = {
259 	{
260 		.start	= 0x40301680,
261 		.end	= 0x403016a3,
262 		.flags	= IORESOURCE_MEM,
263 	}, {
264 		.start	= IRQ_I2C,
265 		.end	= IRQ_I2C,
266 		.flags	= IORESOURCE_IRQ,
267 	},
268 };
269 
270 struct platform_device pxa_device_i2c = {
271 	.name		= "pxa2xx-i2c",
272 	.id		= 0,
273 	.resource	= pxai2c_resources,
274 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
275 };
276 
277 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
278 {
279 	pxa_register_device(&pxa_device_i2c, info);
280 }
281 
282 #ifdef CONFIG_PXA27x
283 static struct resource pxa27x_resources_i2c_power[] = {
284 	{
285 		.start	= 0x40f00180,
286 		.end	= 0x40f001a3,
287 		.flags	= IORESOURCE_MEM,
288 	}, {
289 		.start	= IRQ_PWRI2C,
290 		.end	= IRQ_PWRI2C,
291 		.flags	= IORESOURCE_IRQ,
292 	},
293 };
294 
295 struct platform_device pxa27x_device_i2c_power = {
296 	.name		= "pxa2xx-i2c",
297 	.id		= 1,
298 	.resource	= pxa27x_resources_i2c_power,
299 	.num_resources	= ARRAY_SIZE(pxa27x_resources_i2c_power),
300 };
301 #endif
302 
303 #ifdef CONFIG_PXA3xx
304 static struct resource pxa3xx_resources_i2c_power[] = {
305 	{
306 		.start  = 0x40f500c0,
307 		.end    = 0x40f500d3,
308 		.flags	= IORESOURCE_MEM,
309 	}, {
310 		.start	= IRQ_PWRI2C,
311 		.end	= IRQ_PWRI2C,
312 		.flags	= IORESOURCE_IRQ,
313 	},
314 };
315 
316 struct platform_device pxa3xx_device_i2c_power = {
317 	.name		= "pxa3xx-pwri2c",
318 	.id		= 1,
319 	.resource	= pxa3xx_resources_i2c_power,
320 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_i2c_power),
321 };
322 #endif
323 
324 static struct resource pxai2s_resources[] = {
325 	{
326 		.start	= 0x40400000,
327 		.end	= 0x40400083,
328 		.flags	= IORESOURCE_MEM,
329 	}, {
330 		.start	= IRQ_I2S,
331 		.end	= IRQ_I2S,
332 		.flags	= IORESOURCE_IRQ,
333 	},
334 };
335 
336 struct platform_device pxa_device_i2s = {
337 	.name		= "pxa2xx-i2s",
338 	.id		= -1,
339 	.resource	= pxai2s_resources,
340 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
341 };
342 
343 static u64 pxaficp_dmamask = ~(u32)0;
344 
345 struct platform_device pxa_device_ficp = {
346 	.name		= "pxa2xx-ir",
347 	.id		= -1,
348 	.dev		= {
349 		.dma_mask = &pxaficp_dmamask,
350 		.coherent_dma_mask = 0xffffffff,
351 	},
352 };
353 
354 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
355 {
356 	pxa_register_device(&pxa_device_ficp, info);
357 }
358 
359 static struct resource pxa_rtc_resources[] = {
360 	[0] = {
361 		.start  = 0x40900000,
362 		.end	= 0x40900000 + 0x3b,
363 		.flags  = IORESOURCE_MEM,
364 	},
365 	[1] = {
366 		.start  = IRQ_RTC1Hz,
367 		.end    = IRQ_RTC1Hz,
368 		.flags  = IORESOURCE_IRQ,
369 	},
370 	[2] = {
371 		.start  = IRQ_RTCAlrm,
372 		.end    = IRQ_RTCAlrm,
373 		.flags  = IORESOURCE_IRQ,
374 	},
375 };
376 
377 struct platform_device sa1100_device_rtc = {
378 	.name		= "sa1100-rtc",
379 	.id		= -1,
380 };
381 
382 struct platform_device pxa_device_rtc = {
383 	.name		= "pxa-rtc",
384 	.id		= -1,
385 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
386 	.resource       = pxa_rtc_resources,
387 };
388 
389 static struct resource pxa_ac97_resources[] = {
390 	[0] = {
391 		.start  = 0x40500000,
392 		.end	= 0x40500000 + 0xfff,
393 		.flags  = IORESOURCE_MEM,
394 	},
395 	[1] = {
396 		.start  = IRQ_AC97,
397 		.end    = IRQ_AC97,
398 		.flags  = IORESOURCE_IRQ,
399 	},
400 };
401 
402 static u64 pxa_ac97_dmamask = 0xffffffffUL;
403 
404 struct platform_device pxa_device_ac97 = {
405 	.name           = "pxa2xx-ac97",
406 	.id             = -1,
407 	.dev            = {
408 		.dma_mask = &pxa_ac97_dmamask,
409 		.coherent_dma_mask = 0xffffffff,
410 	},
411 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
412 	.resource       = pxa_ac97_resources,
413 };
414 
415 void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
416 {
417 	pxa_register_device(&pxa_device_ac97, ops);
418 }
419 
420 #ifdef CONFIG_PXA25x
421 
422 static struct resource pxa25x_resource_pwm0[] = {
423 	[0] = {
424 		.start	= 0x40b00000,
425 		.end	= 0x40b0000f,
426 		.flags	= IORESOURCE_MEM,
427 	},
428 };
429 
430 struct platform_device pxa25x_device_pwm0 = {
431 	.name		= "pxa25x-pwm",
432 	.id		= 0,
433 	.resource	= pxa25x_resource_pwm0,
434 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
435 };
436 
437 static struct resource pxa25x_resource_pwm1[] = {
438 	[0] = {
439 		.start	= 0x40c00000,
440 		.end	= 0x40c0000f,
441 		.flags	= IORESOURCE_MEM,
442 	},
443 };
444 
445 struct platform_device pxa25x_device_pwm1 = {
446 	.name		= "pxa25x-pwm",
447 	.id		= 1,
448 	.resource	= pxa25x_resource_pwm1,
449 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
450 };
451 
452 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
453 
454 static struct resource pxa25x_resource_ssp[] = {
455 	[0] = {
456 		.start	= 0x41000000,
457 		.end	= 0x4100001f,
458 		.flags	= IORESOURCE_MEM,
459 	},
460 	[1] = {
461 		.start	= IRQ_SSP,
462 		.end	= IRQ_SSP,
463 		.flags	= IORESOURCE_IRQ,
464 	},
465 	[2] = {
466 		/* DRCMR for RX */
467 		.start	= 13,
468 		.end	= 13,
469 		.flags	= IORESOURCE_DMA,
470 	},
471 	[3] = {
472 		/* DRCMR for TX */
473 		.start	= 14,
474 		.end	= 14,
475 		.flags	= IORESOURCE_DMA,
476 	},
477 };
478 
479 struct platform_device pxa25x_device_ssp = {
480 	.name		= "pxa25x-ssp",
481 	.id		= 0,
482 	.dev		= {
483 		.dma_mask = &pxa25x_ssp_dma_mask,
484 		.coherent_dma_mask = DMA_BIT_MASK(32),
485 	},
486 	.resource	= pxa25x_resource_ssp,
487 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
488 };
489 
490 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
491 
492 static struct resource pxa25x_resource_nssp[] = {
493 	[0] = {
494 		.start	= 0x41400000,
495 		.end	= 0x4140002f,
496 		.flags	= IORESOURCE_MEM,
497 	},
498 	[1] = {
499 		.start	= IRQ_NSSP,
500 		.end	= IRQ_NSSP,
501 		.flags	= IORESOURCE_IRQ,
502 	},
503 	[2] = {
504 		/* DRCMR for RX */
505 		.start	= 15,
506 		.end	= 15,
507 		.flags	= IORESOURCE_DMA,
508 	},
509 	[3] = {
510 		/* DRCMR for TX */
511 		.start	= 16,
512 		.end	= 16,
513 		.flags	= IORESOURCE_DMA,
514 	},
515 };
516 
517 struct platform_device pxa25x_device_nssp = {
518 	.name		= "pxa25x-nssp",
519 	.id		= 1,
520 	.dev		= {
521 		.dma_mask = &pxa25x_nssp_dma_mask,
522 		.coherent_dma_mask = DMA_BIT_MASK(32),
523 	},
524 	.resource	= pxa25x_resource_nssp,
525 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
526 };
527 
528 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
529 
530 static struct resource pxa25x_resource_assp[] = {
531 	[0] = {
532 		.start	= 0x41500000,
533 		.end	= 0x4150002f,
534 		.flags	= IORESOURCE_MEM,
535 	},
536 	[1] = {
537 		.start	= IRQ_ASSP,
538 		.end	= IRQ_ASSP,
539 		.flags	= IORESOURCE_IRQ,
540 	},
541 	[2] = {
542 		/* DRCMR for RX */
543 		.start	= 23,
544 		.end	= 23,
545 		.flags	= IORESOURCE_DMA,
546 	},
547 	[3] = {
548 		/* DRCMR for TX */
549 		.start	= 24,
550 		.end	= 24,
551 		.flags	= IORESOURCE_DMA,
552 	},
553 };
554 
555 struct platform_device pxa25x_device_assp = {
556 	/* ASSP is basically equivalent to NSSP */
557 	.name		= "pxa25x-nssp",
558 	.id		= 2,
559 	.dev		= {
560 		.dma_mask = &pxa25x_assp_dma_mask,
561 		.coherent_dma_mask = DMA_BIT_MASK(32),
562 	},
563 	.resource	= pxa25x_resource_assp,
564 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
565 };
566 #endif /* CONFIG_PXA25x */
567 
568 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
569 
570 static struct resource pxa27x_resource_keypad[] = {
571 	[0] = {
572 		.start	= 0x41500000,
573 		.end	= 0x4150004c,
574 		.flags	= IORESOURCE_MEM,
575 	},
576 	[1] = {
577 		.start	= IRQ_KEYPAD,
578 		.end	= IRQ_KEYPAD,
579 		.flags	= IORESOURCE_IRQ,
580 	},
581 };
582 
583 struct platform_device pxa27x_device_keypad = {
584 	.name		= "pxa27x-keypad",
585 	.id		= -1,
586 	.resource	= pxa27x_resource_keypad,
587 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
588 };
589 
590 void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
591 {
592 	pxa_register_device(&pxa27x_device_keypad, info);
593 }
594 
595 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
596 
597 static struct resource pxa27x_resource_ohci[] = {
598 	[0] = {
599 		.start  = 0x4C000000,
600 		.end    = 0x4C00ff6f,
601 		.flags  = IORESOURCE_MEM,
602 	},
603 	[1] = {
604 		.start  = IRQ_USBH1,
605 		.end    = IRQ_USBH1,
606 		.flags  = IORESOURCE_IRQ,
607 	},
608 };
609 
610 struct platform_device pxa27x_device_ohci = {
611 	.name		= "pxa27x-ohci",
612 	.id		= -1,
613 	.dev		= {
614 		.dma_mask = &pxa27x_ohci_dma_mask,
615 		.coherent_dma_mask = DMA_BIT_MASK(32),
616 	},
617 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
618 	.resource       = pxa27x_resource_ohci,
619 };
620 
621 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
622 {
623 	pxa_register_device(&pxa27x_device_ohci, info);
624 }
625 
626 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
627 
628 static struct resource pxa27x_resource_ssp1[] = {
629 	[0] = {
630 		.start	= 0x41000000,
631 		.end	= 0x4100003f,
632 		.flags	= IORESOURCE_MEM,
633 	},
634 	[1] = {
635 		.start	= IRQ_SSP,
636 		.end	= IRQ_SSP,
637 		.flags	= IORESOURCE_IRQ,
638 	},
639 	[2] = {
640 		/* DRCMR for RX */
641 		.start	= 13,
642 		.end	= 13,
643 		.flags	= IORESOURCE_DMA,
644 	},
645 	[3] = {
646 		/* DRCMR for TX */
647 		.start	= 14,
648 		.end	= 14,
649 		.flags	= IORESOURCE_DMA,
650 	},
651 };
652 
653 struct platform_device pxa27x_device_ssp1 = {
654 	.name		= "pxa27x-ssp",
655 	.id		= 0,
656 	.dev		= {
657 		.dma_mask = &pxa27x_ssp1_dma_mask,
658 		.coherent_dma_mask = DMA_BIT_MASK(32),
659 	},
660 	.resource	= pxa27x_resource_ssp1,
661 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
662 };
663 
664 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
665 
666 static struct resource pxa27x_resource_ssp2[] = {
667 	[0] = {
668 		.start	= 0x41700000,
669 		.end	= 0x4170003f,
670 		.flags	= IORESOURCE_MEM,
671 	},
672 	[1] = {
673 		.start	= IRQ_SSP2,
674 		.end	= IRQ_SSP2,
675 		.flags	= IORESOURCE_IRQ,
676 	},
677 	[2] = {
678 		/* DRCMR for RX */
679 		.start	= 15,
680 		.end	= 15,
681 		.flags	= IORESOURCE_DMA,
682 	},
683 	[3] = {
684 		/* DRCMR for TX */
685 		.start	= 16,
686 		.end	= 16,
687 		.flags	= IORESOURCE_DMA,
688 	},
689 };
690 
691 struct platform_device pxa27x_device_ssp2 = {
692 	.name		= "pxa27x-ssp",
693 	.id		= 1,
694 	.dev		= {
695 		.dma_mask = &pxa27x_ssp2_dma_mask,
696 		.coherent_dma_mask = DMA_BIT_MASK(32),
697 	},
698 	.resource	= pxa27x_resource_ssp2,
699 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
700 };
701 
702 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
703 
704 static struct resource pxa27x_resource_ssp3[] = {
705 	[0] = {
706 		.start	= 0x41900000,
707 		.end	= 0x4190003f,
708 		.flags	= IORESOURCE_MEM,
709 	},
710 	[1] = {
711 		.start	= IRQ_SSP3,
712 		.end	= IRQ_SSP3,
713 		.flags	= IORESOURCE_IRQ,
714 	},
715 	[2] = {
716 		/* DRCMR for RX */
717 		.start	= 66,
718 		.end	= 66,
719 		.flags	= IORESOURCE_DMA,
720 	},
721 	[3] = {
722 		/* DRCMR for TX */
723 		.start	= 67,
724 		.end	= 67,
725 		.flags	= IORESOURCE_DMA,
726 	},
727 };
728 
729 struct platform_device pxa27x_device_ssp3 = {
730 	.name		= "pxa27x-ssp",
731 	.id		= 2,
732 	.dev		= {
733 		.dma_mask = &pxa27x_ssp3_dma_mask,
734 		.coherent_dma_mask = DMA_BIT_MASK(32),
735 	},
736 	.resource	= pxa27x_resource_ssp3,
737 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
738 };
739 
740 static struct resource pxa27x_resource_pwm0[] = {
741 	[0] = {
742 		.start	= 0x40b00000,
743 		.end	= 0x40b0001f,
744 		.flags	= IORESOURCE_MEM,
745 	},
746 };
747 
748 struct platform_device pxa27x_device_pwm0 = {
749 	.name		= "pxa27x-pwm",
750 	.id		= 0,
751 	.resource	= pxa27x_resource_pwm0,
752 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
753 };
754 
755 static struct resource pxa27x_resource_pwm1[] = {
756 	[0] = {
757 		.start	= 0x40c00000,
758 		.end	= 0x40c0001f,
759 		.flags	= IORESOURCE_MEM,
760 	},
761 };
762 
763 struct platform_device pxa27x_device_pwm1 = {
764 	.name		= "pxa27x-pwm",
765 	.id		= 1,
766 	.resource	= pxa27x_resource_pwm1,
767 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
768 };
769 
770 static struct resource pxa27x_resource_camera[] = {
771 	[0] = {
772 		.start	= 0x50000000,
773 		.end	= 0x50000fff,
774 		.flags	= IORESOURCE_MEM,
775 	},
776 	[1] = {
777 		.start	= IRQ_CAMERA,
778 		.end	= IRQ_CAMERA,
779 		.flags	= IORESOURCE_IRQ,
780 	},
781 };
782 
783 static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
784 
785 static struct platform_device pxa27x_device_camera = {
786 	.name		= "pxa27x-camera",
787 	.id		= 0, /* This is used to put cameras on this interface */
788 	.dev		= {
789 		.dma_mask      		= &pxa27x_dma_mask_camera,
790 		.coherent_dma_mask	= 0xffffffff,
791 	},
792 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
793 	.resource	= pxa27x_resource_camera,
794 };
795 
796 void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
797 {
798 	pxa_register_device(&pxa27x_device_camera, info);
799 }
800 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
801 
802 #ifdef CONFIG_PXA3xx
803 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
804 
805 static struct resource pxa3xx_resource_ssp4[] = {
806 	[0] = {
807 		.start	= 0x41a00000,
808 		.end	= 0x41a0003f,
809 		.flags	= IORESOURCE_MEM,
810 	},
811 	[1] = {
812 		.start	= IRQ_SSP4,
813 		.end	= IRQ_SSP4,
814 		.flags	= IORESOURCE_IRQ,
815 	},
816 	[2] = {
817 		/* DRCMR for RX */
818 		.start	= 2,
819 		.end	= 2,
820 		.flags	= IORESOURCE_DMA,
821 	},
822 	[3] = {
823 		/* DRCMR for TX */
824 		.start	= 3,
825 		.end	= 3,
826 		.flags	= IORESOURCE_DMA,
827 	},
828 };
829 
830 struct platform_device pxa3xx_device_ssp4 = {
831 	/* PXA3xx SSP is basically equivalent to PXA27x */
832 	.name		= "pxa27x-ssp",
833 	.id		= 3,
834 	.dev		= {
835 		.dma_mask = &pxa3xx_ssp4_dma_mask,
836 		.coherent_dma_mask = DMA_BIT_MASK(32),
837 	},
838 	.resource	= pxa3xx_resource_ssp4,
839 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
840 };
841 
842 static struct resource pxa3xx_resources_mci2[] = {
843 	[0] = {
844 		.start	= 0x42000000,
845 		.end	= 0x42000fff,
846 		.flags	= IORESOURCE_MEM,
847 	},
848 	[1] = {
849 		.start	= IRQ_MMC2,
850 		.end	= IRQ_MMC2,
851 		.flags	= IORESOURCE_IRQ,
852 	},
853 	[2] = {
854 		.start	= 93,
855 		.end	= 93,
856 		.flags	= IORESOURCE_DMA,
857 	},
858 	[3] = {
859 		.start	= 94,
860 		.end	= 94,
861 		.flags	= IORESOURCE_DMA,
862 	},
863 };
864 
865 struct platform_device pxa3xx_device_mci2 = {
866 	.name		= "pxa2xx-mci",
867 	.id		= 1,
868 	.dev		= {
869 		.dma_mask = &pxamci_dmamask,
870 		.coherent_dma_mask =	0xffffffff,
871 	},
872 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
873 	.resource	= pxa3xx_resources_mci2,
874 };
875 
876 void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
877 {
878 	pxa_register_device(&pxa3xx_device_mci2, info);
879 }
880 
881 static struct resource pxa3xx_resources_mci3[] = {
882 	[0] = {
883 		.start	= 0x42500000,
884 		.end	= 0x42500fff,
885 		.flags	= IORESOURCE_MEM,
886 	},
887 	[1] = {
888 		.start	= IRQ_MMC3,
889 		.end	= IRQ_MMC3,
890 		.flags	= IORESOURCE_IRQ,
891 	},
892 	[2] = {
893 		.start	= 100,
894 		.end	= 100,
895 		.flags	= IORESOURCE_DMA,
896 	},
897 	[3] = {
898 		.start	= 101,
899 		.end	= 101,
900 		.flags	= IORESOURCE_DMA,
901 	},
902 };
903 
904 struct platform_device pxa3xx_device_mci3 = {
905 	.name		= "pxa2xx-mci",
906 	.id		= 2,
907 	.dev		= {
908 		.dma_mask = &pxamci_dmamask,
909 		.coherent_dma_mask = 0xffffffff,
910 	},
911 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
912 	.resource	= pxa3xx_resources_mci3,
913 };
914 
915 void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
916 {
917 	pxa_register_device(&pxa3xx_device_mci3, info);
918 }
919 
920 static struct resource pxa3xx_resources_nand[] = {
921 	[0] = {
922 		.start	= 0x43100000,
923 		.end	= 0x43100053,
924 		.flags	= IORESOURCE_MEM,
925 	},
926 	[1] = {
927 		.start	= IRQ_NAND,
928 		.end	= IRQ_NAND,
929 		.flags	= IORESOURCE_IRQ,
930 	},
931 	[2] = {
932 		/* DRCMR for Data DMA */
933 		.start	= 97,
934 		.end	= 97,
935 		.flags	= IORESOURCE_DMA,
936 	},
937 	[3] = {
938 		/* DRCMR for Command DMA */
939 		.start	= 99,
940 		.end	= 99,
941 		.flags	= IORESOURCE_DMA,
942 	},
943 };
944 
945 static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
946 
947 struct platform_device pxa3xx_device_nand = {
948 	.name		= "pxa3xx-nand",
949 	.id		= -1,
950 	.dev		= {
951 		.dma_mask = &pxa3xx_nand_dma_mask,
952 		.coherent_dma_mask = DMA_BIT_MASK(32),
953 	},
954 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
955 	.resource	= pxa3xx_resources_nand,
956 };
957 
958 void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
959 {
960 	pxa_register_device(&pxa3xx_device_nand, info);
961 }
962 
963 static struct resource pxa3xx_resources_gcu[] = {
964 	{
965 		.start	= 0x54000000,
966 		.end	= 0x54000fff,
967 		.flags	= IORESOURCE_MEM,
968 	},
969 	{
970 		.start	= IRQ_GCU,
971 		.end	= IRQ_GCU,
972 		.flags	= IORESOURCE_IRQ,
973 	},
974 };
975 
976 static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
977 
978 struct platform_device pxa3xx_device_gcu = {
979 	.name		= "pxa3xx-gcu",
980 	.id		= -1,
981 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_gcu),
982 	.resource	= pxa3xx_resources_gcu,
983 	.dev		= {
984 		.dma_mask = &pxa3xx_gcu_dmamask,
985 		.coherent_dma_mask = 0xffffffff,
986 	},
987 };
988 
989 #endif /* CONFIG_PXA3xx */
990 
991 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
992  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
993 void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
994 {
995 	struct platform_device *pd;
996 
997 	pd = platform_device_alloc("pxa2xx-spi", id);
998 	if (pd == NULL) {
999 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1000 		       id);
1001 		return;
1002 	}
1003 
1004 	pd->dev.platform_data = info;
1005 	platform_device_add(pd);
1006 }
1007