1 /* 2 * arch/arm/mach-orion5x/pci.c 3 * 4 * PCI and PCIe functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/mbus.h> 16 #include <asm/irq.h> 17 #include <asm/mach/pci.h> 18 #include <plat/pcie.h> 19 #include "common.h" 20 21 /***************************************************************************** 22 * Orion has one PCIe controller and one PCI controller. 23 * 24 * Note1: The local PCIe bus number is '0'. The local PCI bus number 25 * follows the scanned PCIe bridged busses, if any. 26 * 27 * Note2: It is possible for PCI/PCIe agents to access many subsystem's 28 * space, by configuring BARs and Address Decode Windows, e.g. flashes on 29 * device bus, Orion registers, etc. However this code only enable the 30 * access to DDR banks. 31 ****************************************************************************/ 32 33 34 /***************************************************************************** 35 * PCIe controller 36 ****************************************************************************/ 37 #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) 38 39 void __init orion5x_pcie_id(u32 *dev, u32 *rev) 40 { 41 *dev = orion_pcie_dev_id(PCIE_BASE); 42 *rev = orion_pcie_rev(PCIE_BASE); 43 } 44 45 static int pcie_valid_config(int bus, int dev) 46 { 47 /* 48 * Don't go out when trying to access -- 49 * 1. nonexisting device on local bus 50 * 2. where there's no device connected (no link) 51 */ 52 if (bus == 0 && dev == 0) 53 return 1; 54 55 if (!orion_pcie_link_up(PCIE_BASE)) 56 return 0; 57 58 if (bus == 0 && dev != 1) 59 return 0; 60 61 return 1; 62 } 63 64 65 /* 66 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 67 * and then reading the PCIE_CONF_DATA register. Need to make sure these 68 * transactions are atomic. 69 */ 70 static DEFINE_SPINLOCK(orion5x_pcie_lock); 71 72 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 73 int size, u32 *val) 74 { 75 unsigned long flags; 76 int ret; 77 78 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 79 *val = 0xffffffff; 80 return PCIBIOS_DEVICE_NOT_FOUND; 81 } 82 83 spin_lock_irqsave(&orion5x_pcie_lock, flags); 84 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 85 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 86 87 return ret; 88 } 89 90 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, 91 int where, int size, u32 *val) 92 { 93 int ret; 94 95 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 96 *val = 0xffffffff; 97 return PCIBIOS_DEVICE_NOT_FOUND; 98 } 99 100 /* 101 * We only support access to the non-extended configuration 102 * space when using the WA access method (or we would have to 103 * sacrifice 256M of CPU virtual address space.) 104 */ 105 if (where >= 0x100) { 106 *val = 0xffffffff; 107 return PCIBIOS_DEVICE_NOT_FOUND; 108 } 109 110 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, 111 bus, devfn, where, size, val); 112 113 return ret; 114 } 115 116 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 117 int where, int size, u32 val) 118 { 119 unsigned long flags; 120 int ret; 121 122 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 123 return PCIBIOS_DEVICE_NOT_FOUND; 124 125 spin_lock_irqsave(&orion5x_pcie_lock, flags); 126 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 127 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 128 129 return ret; 130 } 131 132 static struct pci_ops pcie_ops = { 133 .read = pcie_rd_conf, 134 .write = pcie_wr_conf, 135 }; 136 137 138 static int __init pcie_setup(struct pci_sys_data *sys) 139 { 140 struct resource *res; 141 int dev; 142 143 /* 144 * Generic PCIe unit setup. 145 */ 146 orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); 147 148 /* 149 * Check whether to apply Orion-1/Orion-NAS PCIe config 150 * read transaction workaround. 151 */ 152 dev = orion_pcie_dev_id(PCIE_BASE); 153 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 154 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 155 "read transaction workaround\n"); 156 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 157 ORION5X_PCIE_WA_SIZE); 158 pcie_ops.read = pcie_rd_conf_wa; 159 } 160 161 /* 162 * Request resources. 163 */ 164 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 165 if (!res) 166 panic("pcie_setup unable to alloc resources"); 167 168 /* 169 * IORESOURCE_IO 170 */ 171 res[0].name = "PCIe I/O Space"; 172 res[0].flags = IORESOURCE_IO; 173 res[0].start = ORION5X_PCIE_IO_BUS_BASE; 174 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; 175 if (request_resource(&ioport_resource, &res[0])) 176 panic("Request PCIe IO resource failed\n"); 177 sys->resource[0] = &res[0]; 178 179 /* 180 * IORESOURCE_MEM 181 */ 182 res[1].name = "PCIe Memory Space"; 183 res[1].flags = IORESOURCE_MEM; 184 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; 185 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 186 if (request_resource(&iomem_resource, &res[1])) 187 panic("Request PCIe Memory resource failed\n"); 188 sys->resource[1] = &res[1]; 189 190 sys->resource[2] = NULL; 191 sys->io_offset = 0; 192 193 return 1; 194 } 195 196 /***************************************************************************** 197 * PCI controller 198 ****************************************************************************/ 199 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 200 #define PCI_MODE ORION5X_PCI_REG(0xd00) 201 #define PCI_CMD ORION5X_PCI_REG(0xc00) 202 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 203 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) 204 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) 205 206 /* 207 * PCI_MODE bits 208 */ 209 #define PCI_MODE_64BIT (1 << 2) 210 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) 211 212 /* 213 * PCI_CMD bits 214 */ 215 #define PCI_CMD_HOST_REORDER (1 << 29) 216 217 /* 218 * PCI_P2P_CONF bits 219 */ 220 #define PCI_P2P_BUS_OFFS 16 221 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) 222 #define PCI_P2P_DEV_OFFS 24 223 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) 224 225 /* 226 * PCI_CONF_ADDR bits 227 */ 228 #define PCI_CONF_REG(reg) ((reg) & 0xfc) 229 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) 230 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) 231 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) 232 #define PCI_CONF_ADDR_EN (1 << 31) 233 234 /* 235 * Internal configuration space 236 */ 237 #define PCI_CONF_FUNC_STAT_CMD 0 238 #define PCI_CONF_REG_STAT_CMD 4 239 #define PCIX_STAT 0x64 240 #define PCIX_STAT_BUS_OFFS 8 241 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) 242 243 /* 244 * PCI Address Decode Windows registers 245 */ 246 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 247 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 248 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 249 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 250 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 251 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 252 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 253 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 254 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 255 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 256 257 /* 258 * PCI configuration helpers for BAR settings 259 */ 260 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) 261 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) 262 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) 263 264 /* 265 * PCI config cycles are done by programming the PCI_CONF_ADDR register 266 * and then reading the PCI_CONF_DATA register. Need to make sure these 267 * transactions are atomic. 268 */ 269 static DEFINE_SPINLOCK(orion5x_pci_lock); 270 271 static int orion5x_pci_cardbus_mode; 272 273 static int orion5x_pci_local_bus_nr(void) 274 { 275 u32 conf = readl(PCI_P2P_CONF); 276 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 277 } 278 279 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, 280 u32 where, u32 size, u32 *val) 281 { 282 unsigned long flags; 283 spin_lock_irqsave(&orion5x_pci_lock, flags); 284 285 writel(PCI_CONF_BUS(bus) | 286 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 287 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 288 289 *val = readl(PCI_CONF_DATA); 290 291 if (size == 1) 292 *val = (*val >> (8*(where & 0x3))) & 0xff; 293 else if (size == 2) 294 *val = (*val >> (8*(where & 0x3))) & 0xffff; 295 296 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 297 298 return PCIBIOS_SUCCESSFUL; 299 } 300 301 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, 302 u32 where, u32 size, u32 val) 303 { 304 unsigned long flags; 305 int ret = PCIBIOS_SUCCESSFUL; 306 307 spin_lock_irqsave(&orion5x_pci_lock, flags); 308 309 writel(PCI_CONF_BUS(bus) | 310 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 311 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 312 313 if (size == 4) { 314 __raw_writel(val, PCI_CONF_DATA); 315 } else if (size == 2) { 316 __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); 317 } else if (size == 1) { 318 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); 319 } else { 320 ret = PCIBIOS_BAD_REGISTER_NUMBER; 321 } 322 323 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 324 325 return ret; 326 } 327 328 static int orion5x_pci_valid_config(int bus, u32 devfn) 329 { 330 if (bus == orion5x_pci_local_bus_nr()) { 331 /* 332 * Don't go out for local device 333 */ 334 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) 335 return 0; 336 337 /* 338 * When the PCI signals are directly connected to a 339 * Cardbus slot, ignore all but device IDs 0 and 1. 340 */ 341 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) 342 return 0; 343 } 344 345 return 1; 346 } 347 348 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 349 int where, int size, u32 *val) 350 { 351 if (!orion5x_pci_valid_config(bus->number, devfn)) { 352 *val = 0xffffffff; 353 return PCIBIOS_DEVICE_NOT_FOUND; 354 } 355 356 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), 357 PCI_FUNC(devfn), where, size, val); 358 } 359 360 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 361 int where, int size, u32 val) 362 { 363 if (!orion5x_pci_valid_config(bus->number, devfn)) 364 return PCIBIOS_DEVICE_NOT_FOUND; 365 366 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 367 PCI_FUNC(devfn), where, size, val); 368 } 369 370 static struct pci_ops pci_ops = { 371 .read = orion5x_pci_rd_conf, 372 .write = orion5x_pci_wr_conf, 373 }; 374 375 static void __init orion5x_pci_set_bus_nr(int nr) 376 { 377 u32 p2p = readl(PCI_P2P_CONF); 378 379 if (readl(PCI_MODE) & PCI_MODE_PCIX) { 380 /* 381 * PCI-X mode 382 */ 383 u32 pcix_status, bus, dev; 384 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; 385 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; 386 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); 387 pcix_status &= ~PCIX_STAT_BUS_MASK; 388 pcix_status |= (nr << PCIX_STAT_BUS_OFFS); 389 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); 390 } else { 391 /* 392 * PCI Conventional mode 393 */ 394 p2p &= ~PCI_P2P_BUS_MASK; 395 p2p |= (nr << PCI_P2P_BUS_OFFS); 396 writel(p2p, PCI_P2P_CONF); 397 } 398 } 399 400 static void __init orion5x_pci_master_slave_enable(void) 401 { 402 int bus_nr, func, reg; 403 u32 val; 404 405 bus_nr = orion5x_pci_local_bus_nr(); 406 func = PCI_CONF_FUNC_STAT_CMD; 407 reg = PCI_CONF_REG_STAT_CMD; 408 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); 409 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 410 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 411 } 412 413 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 414 { 415 u32 win_enable; 416 int bus; 417 int i; 418 419 /* 420 * First, disable windows. 421 */ 422 win_enable = 0xffffffff; 423 writel(win_enable, PCI_BAR_ENABLE); 424 425 /* 426 * Setup windows for DDR banks. 427 */ 428 bus = orion5x_pci_local_bus_nr(); 429 430 for (i = 0; i < dram->num_cs; i++) { 431 struct mbus_dram_window *cs = dram->cs + i; 432 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 433 u32 reg; 434 u32 val; 435 436 /* 437 * Write DRAM bank base address register. 438 */ 439 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); 440 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); 441 val = (cs->base & 0xfffff000) | (val & 0xfff); 442 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); 443 444 /* 445 * Write DRAM bank size register. 446 */ 447 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 448 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 449 writel((cs->size - 1) & 0xfffff000, 450 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); 451 writel(cs->base & 0xfffff000, 452 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); 453 454 /* 455 * Enable decode window for this chip select. 456 */ 457 win_enable &= ~(1 << cs->cs_index); 458 } 459 460 /* 461 * Re-enable decode windows. 462 */ 463 writel(win_enable, PCI_BAR_ENABLE); 464 465 /* 466 * Disable automatic update of address remaping when writing to BARs. 467 */ 468 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); 469 } 470 471 static int __init pci_setup(struct pci_sys_data *sys) 472 { 473 struct resource *res; 474 475 /* 476 * Point PCI unit MBUS decode windows to DRAM space. 477 */ 478 orion5x_setup_pci_wins(&orion5x_mbus_dram_info); 479 480 /* 481 * Master + Slave enable 482 */ 483 orion5x_pci_master_slave_enable(); 484 485 /* 486 * Force ordering 487 */ 488 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 489 490 /* 491 * Request resources 492 */ 493 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 494 if (!res) 495 panic("pci_setup unable to alloc resources"); 496 497 /* 498 * IORESOURCE_IO 499 */ 500 res[0].name = "PCI I/O Space"; 501 res[0].flags = IORESOURCE_IO; 502 res[0].start = ORION5X_PCI_IO_BUS_BASE; 503 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; 504 if (request_resource(&ioport_resource, &res[0])) 505 panic("Request PCI IO resource failed\n"); 506 sys->resource[0] = &res[0]; 507 508 /* 509 * IORESOURCE_MEM 510 */ 511 res[1].name = "PCI Memory Space"; 512 res[1].flags = IORESOURCE_MEM; 513 res[1].start = ORION5X_PCI_MEM_PHYS_BASE; 514 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 515 if (request_resource(&iomem_resource, &res[1])) 516 panic("Request PCI Memory resource failed\n"); 517 sys->resource[1] = &res[1]; 518 519 sys->resource[2] = NULL; 520 sys->io_offset = 0; 521 522 return 1; 523 } 524 525 526 /***************************************************************************** 527 * General PCIe + PCI 528 ****************************************************************************/ 529 static void __devinit rc_pci_fixup(struct pci_dev *dev) 530 { 531 /* 532 * Prevent enumeration of root complex. 533 */ 534 if (dev->bus->parent == NULL && dev->devfn == 0) { 535 int i; 536 537 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 538 dev->resource[i].start = 0; 539 dev->resource[i].end = 0; 540 dev->resource[i].flags = 0; 541 } 542 } 543 } 544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 545 546 static int orion5x_pci_disabled __initdata; 547 548 void __init orion5x_pci_disable(void) 549 { 550 orion5x_pci_disabled = 1; 551 } 552 553 void __init orion5x_pci_set_cardbus_mode(void) 554 { 555 orion5x_pci_cardbus_mode = 1; 556 } 557 558 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 559 { 560 int ret = 0; 561 562 if (nr == 0) { 563 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 564 ret = pcie_setup(sys); 565 } else if (nr == 1 && !orion5x_pci_disabled) { 566 orion5x_pci_set_bus_nr(sys->busnr); 567 ret = pci_setup(sys); 568 } 569 570 return ret; 571 } 572 573 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 574 { 575 struct pci_bus *bus; 576 577 if (nr == 0) { 578 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 579 } else if (nr == 1 && !orion5x_pci_disabled) { 580 bus = pci_scan_bus(sys->busnr, &pci_ops, sys); 581 } else { 582 bus = NULL; 583 BUG(); 584 } 585 586 return bus; 587 } 588 589 int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 590 { 591 int bus = dev->bus->number; 592 593 /* 594 * PCIe endpoint? 595 */ 596 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) 597 return IRQ_ORION5X_PCIE0_INT; 598 599 return -1; 600 } 601