1 /* 2 * arch/arm/mach-orion5x/pci.c 3 * 4 * PCI and PCIe functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/slab.h> 16 #include <linux/mbus.h> 17 #include <video/vga.h> 18 #include <asm/irq.h> 19 #include <asm/mach/pci.h> 20 #include <plat/pcie.h> 21 #include <plat/addr-map.h> 22 #include <mach/orion5x.h> 23 #include "common.h" 24 25 /***************************************************************************** 26 * Orion has one PCIe controller and one PCI controller. 27 * 28 * Note1: The local PCIe bus number is '0'. The local PCI bus number 29 * follows the scanned PCIe bridged busses, if any. 30 * 31 * Note2: It is possible for PCI/PCIe agents to access many subsystem's 32 * space, by configuring BARs and Address Decode Windows, e.g. flashes on 33 * device bus, Orion registers, etc. However this code only enable the 34 * access to DDR banks. 35 ****************************************************************************/ 36 37 38 /***************************************************************************** 39 * PCIe controller 40 ****************************************************************************/ 41 #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) 42 43 void __init orion5x_pcie_id(u32 *dev, u32 *rev) 44 { 45 *dev = orion_pcie_dev_id(PCIE_BASE); 46 *rev = orion_pcie_rev(PCIE_BASE); 47 } 48 49 static int pcie_valid_config(int bus, int dev) 50 { 51 /* 52 * Don't go out when trying to access -- 53 * 1. nonexisting device on local bus 54 * 2. where there's no device connected (no link) 55 */ 56 if (bus == 0 && dev == 0) 57 return 1; 58 59 if (!orion_pcie_link_up(PCIE_BASE)) 60 return 0; 61 62 if (bus == 0 && dev != 1) 63 return 0; 64 65 return 1; 66 } 67 68 69 /* 70 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 71 * and then reading the PCIE_CONF_DATA register. Need to make sure these 72 * transactions are atomic. 73 */ 74 static DEFINE_SPINLOCK(orion5x_pcie_lock); 75 76 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 77 int size, u32 *val) 78 { 79 unsigned long flags; 80 int ret; 81 82 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 83 *val = 0xffffffff; 84 return PCIBIOS_DEVICE_NOT_FOUND; 85 } 86 87 spin_lock_irqsave(&orion5x_pcie_lock, flags); 88 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 89 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 90 91 return ret; 92 } 93 94 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, 95 int where, int size, u32 *val) 96 { 97 int ret; 98 99 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 100 *val = 0xffffffff; 101 return PCIBIOS_DEVICE_NOT_FOUND; 102 } 103 104 /* 105 * We only support access to the non-extended configuration 106 * space when using the WA access method (or we would have to 107 * sacrifice 256M of CPU virtual address space.) 108 */ 109 if (where >= 0x100) { 110 *val = 0xffffffff; 111 return PCIBIOS_DEVICE_NOT_FOUND; 112 } 113 114 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, 115 bus, devfn, where, size, val); 116 117 return ret; 118 } 119 120 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 121 int where, int size, u32 val) 122 { 123 unsigned long flags; 124 int ret; 125 126 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 127 return PCIBIOS_DEVICE_NOT_FOUND; 128 129 spin_lock_irqsave(&orion5x_pcie_lock, flags); 130 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 131 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 132 133 return ret; 134 } 135 136 static struct pci_ops pcie_ops = { 137 .read = pcie_rd_conf, 138 .write = pcie_wr_conf, 139 }; 140 141 142 static int __init pcie_setup(struct pci_sys_data *sys) 143 { 144 struct resource *res; 145 int dev; 146 147 /* 148 * Generic PCIe unit setup. 149 */ 150 orion_pcie_setup(PCIE_BASE); 151 152 /* 153 * Check whether to apply Orion-1/Orion-NAS PCIe config 154 * read transaction workaround. 155 */ 156 dev = orion_pcie_dev_id(PCIE_BASE); 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 159 "read transaction workaround\n"); 160 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 161 ORION5X_PCIE_WA_SIZE); 162 pcie_ops.read = pcie_rd_conf_wa; 163 } 164 165 /* 166 * Request resources. 167 */ 168 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 169 if (!res) 170 panic("pcie_setup unable to alloc resources"); 171 172 /* 173 * IORESOURCE_IO 174 */ 175 sys->io_offset = 0; 176 res[0].name = "PCIe I/O Space"; 177 res[0].flags = IORESOURCE_IO; 178 res[0].start = ORION5X_PCIE_IO_BUS_BASE; 179 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; 180 if (request_resource(&ioport_resource, &res[0])) 181 panic("Request PCIe IO resource failed\n"); 182 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); 183 184 /* 185 * IORESOURCE_MEM 186 */ 187 res[1].name = "PCIe Memory Space"; 188 res[1].flags = IORESOURCE_MEM; 189 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; 190 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 191 if (request_resource(&iomem_resource, &res[1])) 192 panic("Request PCIe Memory resource failed\n"); 193 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 194 195 return 1; 196 } 197 198 /***************************************************************************** 199 * PCI controller 200 ****************************************************************************/ 201 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 202 #define PCI_MODE ORION5X_PCI_REG(0xd00) 203 #define PCI_CMD ORION5X_PCI_REG(0xc00) 204 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 205 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) 206 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) 207 208 /* 209 * PCI_MODE bits 210 */ 211 #define PCI_MODE_64BIT (1 << 2) 212 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) 213 214 /* 215 * PCI_CMD bits 216 */ 217 #define PCI_CMD_HOST_REORDER (1 << 29) 218 219 /* 220 * PCI_P2P_CONF bits 221 */ 222 #define PCI_P2P_BUS_OFFS 16 223 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) 224 #define PCI_P2P_DEV_OFFS 24 225 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) 226 227 /* 228 * PCI_CONF_ADDR bits 229 */ 230 #define PCI_CONF_REG(reg) ((reg) & 0xfc) 231 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) 232 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) 233 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) 234 #define PCI_CONF_ADDR_EN (1 << 31) 235 236 /* 237 * Internal configuration space 238 */ 239 #define PCI_CONF_FUNC_STAT_CMD 0 240 #define PCI_CONF_REG_STAT_CMD 4 241 #define PCIX_STAT 0x64 242 #define PCIX_STAT_BUS_OFFS 8 243 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) 244 245 /* 246 * PCI Address Decode Windows registers 247 */ 248 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 249 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 250 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 251 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 252 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 253 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 254 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 255 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 256 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 257 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 258 259 /* 260 * PCI configuration helpers for BAR settings 261 */ 262 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) 263 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) 264 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) 265 266 /* 267 * PCI config cycles are done by programming the PCI_CONF_ADDR register 268 * and then reading the PCI_CONF_DATA register. Need to make sure these 269 * transactions are atomic. 270 */ 271 static DEFINE_SPINLOCK(orion5x_pci_lock); 272 273 static int orion5x_pci_cardbus_mode; 274 275 static int orion5x_pci_local_bus_nr(void) 276 { 277 u32 conf = readl(PCI_P2P_CONF); 278 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 279 } 280 281 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, 282 u32 where, u32 size, u32 *val) 283 { 284 unsigned long flags; 285 spin_lock_irqsave(&orion5x_pci_lock, flags); 286 287 writel(PCI_CONF_BUS(bus) | 288 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 289 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 290 291 *val = readl(PCI_CONF_DATA); 292 293 if (size == 1) 294 *val = (*val >> (8*(where & 0x3))) & 0xff; 295 else if (size == 2) 296 *val = (*val >> (8*(where & 0x3))) & 0xffff; 297 298 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 299 300 return PCIBIOS_SUCCESSFUL; 301 } 302 303 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, 304 u32 where, u32 size, u32 val) 305 { 306 unsigned long flags; 307 int ret = PCIBIOS_SUCCESSFUL; 308 309 spin_lock_irqsave(&orion5x_pci_lock, flags); 310 311 writel(PCI_CONF_BUS(bus) | 312 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 313 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 314 315 if (size == 4) { 316 __raw_writel(val, PCI_CONF_DATA); 317 } else if (size == 2) { 318 __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); 319 } else if (size == 1) { 320 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); 321 } else { 322 ret = PCIBIOS_BAD_REGISTER_NUMBER; 323 } 324 325 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 326 327 return ret; 328 } 329 330 static int orion5x_pci_valid_config(int bus, u32 devfn) 331 { 332 if (bus == orion5x_pci_local_bus_nr()) { 333 /* 334 * Don't go out for local device 335 */ 336 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) 337 return 0; 338 339 /* 340 * When the PCI signals are directly connected to a 341 * Cardbus slot, ignore all but device IDs 0 and 1. 342 */ 343 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) 344 return 0; 345 } 346 347 return 1; 348 } 349 350 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 351 int where, int size, u32 *val) 352 { 353 if (!orion5x_pci_valid_config(bus->number, devfn)) { 354 *val = 0xffffffff; 355 return PCIBIOS_DEVICE_NOT_FOUND; 356 } 357 358 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), 359 PCI_FUNC(devfn), where, size, val); 360 } 361 362 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 363 int where, int size, u32 val) 364 { 365 if (!orion5x_pci_valid_config(bus->number, devfn)) 366 return PCIBIOS_DEVICE_NOT_FOUND; 367 368 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 369 PCI_FUNC(devfn), where, size, val); 370 } 371 372 static struct pci_ops pci_ops = { 373 .read = orion5x_pci_rd_conf, 374 .write = orion5x_pci_wr_conf, 375 }; 376 377 static void __init orion5x_pci_set_bus_nr(int nr) 378 { 379 u32 p2p = readl(PCI_P2P_CONF); 380 381 if (readl(PCI_MODE) & PCI_MODE_PCIX) { 382 /* 383 * PCI-X mode 384 */ 385 u32 pcix_status, bus, dev; 386 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; 387 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; 388 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); 389 pcix_status &= ~PCIX_STAT_BUS_MASK; 390 pcix_status |= (nr << PCIX_STAT_BUS_OFFS); 391 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); 392 } else { 393 /* 394 * PCI Conventional mode 395 */ 396 p2p &= ~PCI_P2P_BUS_MASK; 397 p2p |= (nr << PCI_P2P_BUS_OFFS); 398 writel(p2p, PCI_P2P_CONF); 399 } 400 } 401 402 static void __init orion5x_pci_master_slave_enable(void) 403 { 404 int bus_nr, func, reg; 405 u32 val; 406 407 bus_nr = orion5x_pci_local_bus_nr(); 408 func = PCI_CONF_FUNC_STAT_CMD; 409 reg = PCI_CONF_REG_STAT_CMD; 410 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); 411 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 412 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 413 } 414 415 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 416 { 417 u32 win_enable; 418 int bus; 419 int i; 420 421 /* 422 * First, disable windows. 423 */ 424 win_enable = 0xffffffff; 425 writel(win_enable, PCI_BAR_ENABLE); 426 427 /* 428 * Setup windows for DDR banks. 429 */ 430 bus = orion5x_pci_local_bus_nr(); 431 432 for (i = 0; i < dram->num_cs; i++) { 433 struct mbus_dram_window *cs = dram->cs + i; 434 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 435 u32 reg; 436 u32 val; 437 438 /* 439 * Write DRAM bank base address register. 440 */ 441 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); 442 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); 443 val = (cs->base & 0xfffff000) | (val & 0xfff); 444 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); 445 446 /* 447 * Write DRAM bank size register. 448 */ 449 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 450 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 451 writel((cs->size - 1) & 0xfffff000, 452 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); 453 writel(cs->base & 0xfffff000, 454 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); 455 456 /* 457 * Enable decode window for this chip select. 458 */ 459 win_enable &= ~(1 << cs->cs_index); 460 } 461 462 /* 463 * Re-enable decode windows. 464 */ 465 writel(win_enable, PCI_BAR_ENABLE); 466 467 /* 468 * Disable automatic update of address remapping when writing to BARs. 469 */ 470 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); 471 } 472 473 static int __init pci_setup(struct pci_sys_data *sys) 474 { 475 struct resource *res; 476 477 /* 478 * Point PCI unit MBUS decode windows to DRAM space. 479 */ 480 orion5x_setup_pci_wins(&orion_mbus_dram_info); 481 482 /* 483 * Master + Slave enable 484 */ 485 orion5x_pci_master_slave_enable(); 486 487 /* 488 * Force ordering 489 */ 490 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 491 492 /* 493 * Request resources 494 */ 495 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 496 if (!res) 497 panic("pci_setup unable to alloc resources"); 498 499 /* 500 * IORESOURCE_IO 501 */ 502 sys->io_offset = 0; 503 res[0].name = "PCI I/O Space"; 504 res[0].flags = IORESOURCE_IO; 505 res[0].start = ORION5X_PCI_IO_BUS_BASE; 506 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; 507 if (request_resource(&ioport_resource, &res[0])) 508 panic("Request PCI IO resource failed\n"); 509 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); 510 511 /* 512 * IORESOURCE_MEM 513 */ 514 res[1].name = "PCI Memory Space"; 515 res[1].flags = IORESOURCE_MEM; 516 res[1].start = ORION5X_PCI_MEM_PHYS_BASE; 517 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 518 if (request_resource(&iomem_resource, &res[1])) 519 panic("Request PCI Memory resource failed\n"); 520 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 521 522 return 1; 523 } 524 525 526 /***************************************************************************** 527 * General PCIe + PCI 528 ****************************************************************************/ 529 static void __devinit rc_pci_fixup(struct pci_dev *dev) 530 { 531 /* 532 * Prevent enumeration of root complex. 533 */ 534 if (dev->bus->parent == NULL && dev->devfn == 0) { 535 int i; 536 537 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 538 dev->resource[i].start = 0; 539 dev->resource[i].end = 0; 540 dev->resource[i].flags = 0; 541 } 542 } 543 } 544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 545 546 static int orion5x_pci_disabled __initdata; 547 548 void __init orion5x_pci_disable(void) 549 { 550 orion5x_pci_disabled = 1; 551 } 552 553 void __init orion5x_pci_set_cardbus_mode(void) 554 { 555 orion5x_pci_cardbus_mode = 1; 556 } 557 558 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 559 { 560 int ret = 0; 561 562 vga_base = ORION5X_PCIE_MEM_PHYS_BASE; 563 564 if (nr == 0) { 565 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 566 ret = pcie_setup(sys); 567 } else if (nr == 1 && !orion5x_pci_disabled) { 568 orion5x_pci_set_bus_nr(sys->busnr); 569 ret = pci_setup(sys); 570 } 571 572 return ret; 573 } 574 575 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 576 { 577 struct pci_bus *bus; 578 579 if (nr == 0) { 580 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, 581 &sys->resources); 582 } else if (nr == 1 && !orion5x_pci_disabled) { 583 bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, 584 &sys->resources); 585 } else { 586 bus = NULL; 587 BUG(); 588 } 589 590 return bus; 591 } 592 593 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 594 { 595 int bus = dev->bus->number; 596 597 /* 598 * PCIe endpoint? 599 */ 600 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) 601 return IRQ_ORION5X_PCIE0_INT; 602 603 return -1; 604 } 605