1 /* 2 * arch/arm/mach-orion5x/pci.c 3 * 4 * PCI and PCIe functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/slab.h> 16 #include <linux/mbus.h> 17 #include <video/vga.h> 18 #include <asm/irq.h> 19 #include <asm/mach/pci.h> 20 #include <plat/pcie.h> 21 #include <plat/addr-map.h> 22 #include <mach/orion5x.h> 23 #include "common.h" 24 25 /***************************************************************************** 26 * Orion has one PCIe controller and one PCI controller. 27 * 28 * Note1: The local PCIe bus number is '0'. The local PCI bus number 29 * follows the scanned PCIe bridged busses, if any. 30 * 31 * Note2: It is possible for PCI/PCIe agents to access many subsystem's 32 * space, by configuring BARs and Address Decode Windows, e.g. flashes on 33 * device bus, Orion registers, etc. However this code only enable the 34 * access to DDR banks. 35 ****************************************************************************/ 36 37 38 /***************************************************************************** 39 * PCIe controller 40 ****************************************************************************/ 41 #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE) 42 43 void __init orion5x_pcie_id(u32 *dev, u32 *rev) 44 { 45 *dev = orion_pcie_dev_id(PCIE_BASE); 46 *rev = orion_pcie_rev(PCIE_BASE); 47 } 48 49 static int pcie_valid_config(int bus, int dev) 50 { 51 /* 52 * Don't go out when trying to access -- 53 * 1. nonexisting device on local bus 54 * 2. where there's no device connected (no link) 55 */ 56 if (bus == 0 && dev == 0) 57 return 1; 58 59 if (!orion_pcie_link_up(PCIE_BASE)) 60 return 0; 61 62 if (bus == 0 && dev != 1) 63 return 0; 64 65 return 1; 66 } 67 68 69 /* 70 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 71 * and then reading the PCIE_CONF_DATA register. Need to make sure these 72 * transactions are atomic. 73 */ 74 static DEFINE_SPINLOCK(orion5x_pcie_lock); 75 76 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 77 int size, u32 *val) 78 { 79 unsigned long flags; 80 int ret; 81 82 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 83 *val = 0xffffffff; 84 return PCIBIOS_DEVICE_NOT_FOUND; 85 } 86 87 spin_lock_irqsave(&orion5x_pcie_lock, flags); 88 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 89 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 90 91 return ret; 92 } 93 94 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, 95 int where, int size, u32 *val) 96 { 97 int ret; 98 99 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 100 *val = 0xffffffff; 101 return PCIBIOS_DEVICE_NOT_FOUND; 102 } 103 104 /* 105 * We only support access to the non-extended configuration 106 * space when using the WA access method (or we would have to 107 * sacrifice 256M of CPU virtual address space.) 108 */ 109 if (where >= 0x100) { 110 *val = 0xffffffff; 111 return PCIBIOS_DEVICE_NOT_FOUND; 112 } 113 114 ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, 115 bus, devfn, where, size, val); 116 117 return ret; 118 } 119 120 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 121 int where, int size, u32 val) 122 { 123 unsigned long flags; 124 int ret; 125 126 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 127 return PCIBIOS_DEVICE_NOT_FOUND; 128 129 spin_lock_irqsave(&orion5x_pcie_lock, flags); 130 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 131 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 132 133 return ret; 134 } 135 136 static struct pci_ops pcie_ops = { 137 .read = pcie_rd_conf, 138 .write = pcie_wr_conf, 139 }; 140 141 142 static int __init pcie_setup(struct pci_sys_data *sys) 143 { 144 struct resource *res; 145 int dev; 146 147 /* 148 * Generic PCIe unit setup. 149 */ 150 orion_pcie_setup(PCIE_BASE); 151 152 /* 153 * Check whether to apply Orion-1/Orion-NAS PCIe config 154 * read transaction workaround. 155 */ 156 dev = orion_pcie_dev_id(PCIE_BASE); 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 159 "read transaction workaround\n"); 160 mvebu_mbus_add_window_remap_flags("pcie0.0", 161 ORION5X_PCIE_WA_PHYS_BASE, 162 ORION5X_PCIE_WA_SIZE, 163 MVEBU_MBUS_NO_REMAP, 164 MVEBU_MBUS_PCI_WA); 165 pcie_ops.read = pcie_rd_conf_wa; 166 } 167 168 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); 169 170 /* 171 * Request resources. 172 */ 173 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 174 if (!res) 175 panic("pcie_setup unable to alloc resources"); 176 177 /* 178 * IORESOURCE_MEM 179 */ 180 res->name = "PCIe Memory Space"; 181 res->flags = IORESOURCE_MEM; 182 res->start = ORION5X_PCIE_MEM_PHYS_BASE; 183 res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1; 184 if (request_resource(&iomem_resource, res)) 185 panic("Request PCIe Memory resource failed\n"); 186 pci_add_resource_offset(&sys->resources, res, sys->mem_offset); 187 188 return 1; 189 } 190 191 /***************************************************************************** 192 * PCI controller 193 ****************************************************************************/ 194 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x)) 195 #define PCI_MODE ORION5X_PCI_REG(0xd00) 196 #define PCI_CMD ORION5X_PCI_REG(0xc00) 197 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 198 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) 199 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) 200 201 /* 202 * PCI_MODE bits 203 */ 204 #define PCI_MODE_64BIT (1 << 2) 205 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) 206 207 /* 208 * PCI_CMD bits 209 */ 210 #define PCI_CMD_HOST_REORDER (1 << 29) 211 212 /* 213 * PCI_P2P_CONF bits 214 */ 215 #define PCI_P2P_BUS_OFFS 16 216 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) 217 #define PCI_P2P_DEV_OFFS 24 218 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) 219 220 /* 221 * PCI_CONF_ADDR bits 222 */ 223 #define PCI_CONF_REG(reg) ((reg) & 0xfc) 224 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) 225 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) 226 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) 227 #define PCI_CONF_ADDR_EN (1 << 31) 228 229 /* 230 * Internal configuration space 231 */ 232 #define PCI_CONF_FUNC_STAT_CMD 0 233 #define PCI_CONF_REG_STAT_CMD 4 234 #define PCIX_STAT 0x64 235 #define PCIX_STAT_BUS_OFFS 8 236 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) 237 238 /* 239 * PCI Address Decode Windows registers 240 */ 241 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 242 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 243 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 244 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 245 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 246 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 247 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 248 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 249 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 250 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 251 252 /* 253 * PCI configuration helpers for BAR settings 254 */ 255 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) 256 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) 257 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) 258 259 /* 260 * PCI config cycles are done by programming the PCI_CONF_ADDR register 261 * and then reading the PCI_CONF_DATA register. Need to make sure these 262 * transactions are atomic. 263 */ 264 static DEFINE_SPINLOCK(orion5x_pci_lock); 265 266 static int orion5x_pci_cardbus_mode; 267 268 static int orion5x_pci_local_bus_nr(void) 269 { 270 u32 conf = readl(PCI_P2P_CONF); 271 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 272 } 273 274 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, 275 u32 where, u32 size, u32 *val) 276 { 277 unsigned long flags; 278 spin_lock_irqsave(&orion5x_pci_lock, flags); 279 280 writel(PCI_CONF_BUS(bus) | 281 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 282 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 283 284 *val = readl(PCI_CONF_DATA); 285 286 if (size == 1) 287 *val = (*val >> (8*(where & 0x3))) & 0xff; 288 else if (size == 2) 289 *val = (*val >> (8*(where & 0x3))) & 0xffff; 290 291 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 292 293 return PCIBIOS_SUCCESSFUL; 294 } 295 296 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, 297 u32 where, u32 size, u32 val) 298 { 299 unsigned long flags; 300 int ret = PCIBIOS_SUCCESSFUL; 301 302 spin_lock_irqsave(&orion5x_pci_lock, flags); 303 304 writel(PCI_CONF_BUS(bus) | 305 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 306 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 307 308 if (size == 4) { 309 __raw_writel(val, PCI_CONF_DATA); 310 } else if (size == 2) { 311 __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); 312 } else if (size == 1) { 313 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); 314 } else { 315 ret = PCIBIOS_BAD_REGISTER_NUMBER; 316 } 317 318 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 319 320 return ret; 321 } 322 323 static int orion5x_pci_valid_config(int bus, u32 devfn) 324 { 325 if (bus == orion5x_pci_local_bus_nr()) { 326 /* 327 * Don't go out for local device 328 */ 329 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) 330 return 0; 331 332 /* 333 * When the PCI signals are directly connected to a 334 * Cardbus slot, ignore all but device IDs 0 and 1. 335 */ 336 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) 337 return 0; 338 } 339 340 return 1; 341 } 342 343 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 344 int where, int size, u32 *val) 345 { 346 if (!orion5x_pci_valid_config(bus->number, devfn)) { 347 *val = 0xffffffff; 348 return PCIBIOS_DEVICE_NOT_FOUND; 349 } 350 351 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), 352 PCI_FUNC(devfn), where, size, val); 353 } 354 355 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 356 int where, int size, u32 val) 357 { 358 if (!orion5x_pci_valid_config(bus->number, devfn)) 359 return PCIBIOS_DEVICE_NOT_FOUND; 360 361 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 362 PCI_FUNC(devfn), where, size, val); 363 } 364 365 static struct pci_ops pci_ops = { 366 .read = orion5x_pci_rd_conf, 367 .write = orion5x_pci_wr_conf, 368 }; 369 370 static void __init orion5x_pci_set_bus_nr(int nr) 371 { 372 u32 p2p = readl(PCI_P2P_CONF); 373 374 if (readl(PCI_MODE) & PCI_MODE_PCIX) { 375 /* 376 * PCI-X mode 377 */ 378 u32 pcix_status, bus, dev; 379 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; 380 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; 381 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); 382 pcix_status &= ~PCIX_STAT_BUS_MASK; 383 pcix_status |= (nr << PCIX_STAT_BUS_OFFS); 384 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); 385 } else { 386 /* 387 * PCI Conventional mode 388 */ 389 p2p &= ~PCI_P2P_BUS_MASK; 390 p2p |= (nr << PCI_P2P_BUS_OFFS); 391 writel(p2p, PCI_P2P_CONF); 392 } 393 } 394 395 static void __init orion5x_pci_master_slave_enable(void) 396 { 397 int bus_nr, func, reg; 398 u32 val; 399 400 bus_nr = orion5x_pci_local_bus_nr(); 401 func = PCI_CONF_FUNC_STAT_CMD; 402 reg = PCI_CONF_REG_STAT_CMD; 403 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); 404 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 405 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 406 } 407 408 static void __init orion5x_setup_pci_wins(void) 409 { 410 const struct mbus_dram_target_info *dram = mv_mbus_dram_info(); 411 u32 win_enable; 412 int bus; 413 int i; 414 415 /* 416 * First, disable windows. 417 */ 418 win_enable = 0xffffffff; 419 writel(win_enable, PCI_BAR_ENABLE); 420 421 /* 422 * Setup windows for DDR banks. 423 */ 424 bus = orion5x_pci_local_bus_nr(); 425 426 for (i = 0; i < dram->num_cs; i++) { 427 const struct mbus_dram_window *cs = dram->cs + i; 428 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 429 u32 reg; 430 u32 val; 431 432 /* 433 * Write DRAM bank base address register. 434 */ 435 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); 436 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); 437 val = (cs->base & 0xfffff000) | (val & 0xfff); 438 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); 439 440 /* 441 * Write DRAM bank size register. 442 */ 443 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 444 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 445 writel((cs->size - 1) & 0xfffff000, 446 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); 447 writel(cs->base & 0xfffff000, 448 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); 449 450 /* 451 * Enable decode window for this chip select. 452 */ 453 win_enable &= ~(1 << cs->cs_index); 454 } 455 456 /* 457 * Re-enable decode windows. 458 */ 459 writel(win_enable, PCI_BAR_ENABLE); 460 461 /* 462 * Disable automatic update of address remapping when writing to BARs. 463 */ 464 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); 465 } 466 467 static int __init pci_setup(struct pci_sys_data *sys) 468 { 469 struct resource *res; 470 471 /* 472 * Point PCI unit MBUS decode windows to DRAM space. 473 */ 474 orion5x_setup_pci_wins(); 475 476 /* 477 * Master + Slave enable 478 */ 479 orion5x_pci_master_slave_enable(); 480 481 /* 482 * Force ordering 483 */ 484 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 485 486 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); 487 488 /* 489 * Request resources 490 */ 491 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 492 if (!res) 493 panic("pci_setup unable to alloc resources"); 494 495 /* 496 * IORESOURCE_MEM 497 */ 498 res->name = "PCI Memory Space"; 499 res->flags = IORESOURCE_MEM; 500 res->start = ORION5X_PCI_MEM_PHYS_BASE; 501 res->end = res->start + ORION5X_PCI_MEM_SIZE - 1; 502 if (request_resource(&iomem_resource, res)) 503 panic("Request PCI Memory resource failed\n"); 504 pci_add_resource_offset(&sys->resources, res, sys->mem_offset); 505 506 return 1; 507 } 508 509 510 /***************************************************************************** 511 * General PCIe + PCI 512 ****************************************************************************/ 513 static void rc_pci_fixup(struct pci_dev *dev) 514 { 515 /* 516 * Prevent enumeration of root complex. 517 */ 518 if (dev->bus->parent == NULL && dev->devfn == 0) { 519 int i; 520 521 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 522 dev->resource[i].start = 0; 523 dev->resource[i].end = 0; 524 dev->resource[i].flags = 0; 525 } 526 } 527 } 528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 529 530 static int orion5x_pci_disabled __initdata; 531 532 void __init orion5x_pci_disable(void) 533 { 534 orion5x_pci_disabled = 1; 535 } 536 537 void __init orion5x_pci_set_cardbus_mode(void) 538 { 539 orion5x_pci_cardbus_mode = 1; 540 } 541 542 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 543 { 544 int ret = 0; 545 546 vga_base = ORION5X_PCIE_MEM_PHYS_BASE; 547 548 if (nr == 0) { 549 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 550 ret = pcie_setup(sys); 551 } else if (nr == 1 && !orion5x_pci_disabled) { 552 orion5x_pci_set_bus_nr(sys->busnr); 553 ret = pci_setup(sys); 554 } 555 556 return ret; 557 } 558 559 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 560 { 561 struct pci_bus *bus; 562 563 if (nr == 0) { 564 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, 565 &sys->resources); 566 } else if (nr == 1 && !orion5x_pci_disabled) { 567 bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, 568 &sys->resources); 569 } else { 570 bus = NULL; 571 BUG(); 572 } 573 574 return bus; 575 } 576 577 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 578 { 579 int bus = dev->bus->number; 580 581 /* 582 * PCIe endpoint? 583 */ 584 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) 585 return IRQ_ORION5X_PCIE0_INT; 586 587 return -1; 588 } 589