1 /* 2 * arch/arm/mach-orion5x/pci.c 3 * 4 * PCI and PCIe functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/slab.h> 16 #include <linux/mbus.h> 17 #include <video/vga.h> 18 #include <asm/irq.h> 19 #include <asm/mach/pci.h> 20 #include <plat/pcie.h> 21 #include <plat/addr-map.h> 22 #include <mach/orion5x.h> 23 #include "common.h" 24 25 /***************************************************************************** 26 * Orion has one PCIe controller and one PCI controller. 27 * 28 * Note1: The local PCIe bus number is '0'. The local PCI bus number 29 * follows the scanned PCIe bridged busses, if any. 30 * 31 * Note2: It is possible for PCI/PCIe agents to access many subsystem's 32 * space, by configuring BARs and Address Decode Windows, e.g. flashes on 33 * device bus, Orion registers, etc. However this code only enable the 34 * access to DDR banks. 35 ****************************************************************************/ 36 37 38 /***************************************************************************** 39 * PCIe controller 40 ****************************************************************************/ 41 #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) 42 43 void __init orion5x_pcie_id(u32 *dev, u32 *rev) 44 { 45 *dev = orion_pcie_dev_id(PCIE_BASE); 46 *rev = orion_pcie_rev(PCIE_BASE); 47 } 48 49 static int pcie_valid_config(int bus, int dev) 50 { 51 /* 52 * Don't go out when trying to access -- 53 * 1. nonexisting device on local bus 54 * 2. where there's no device connected (no link) 55 */ 56 if (bus == 0 && dev == 0) 57 return 1; 58 59 if (!orion_pcie_link_up(PCIE_BASE)) 60 return 0; 61 62 if (bus == 0 && dev != 1) 63 return 0; 64 65 return 1; 66 } 67 68 69 /* 70 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 71 * and then reading the PCIE_CONF_DATA register. Need to make sure these 72 * transactions are atomic. 73 */ 74 static DEFINE_SPINLOCK(orion5x_pcie_lock); 75 76 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 77 int size, u32 *val) 78 { 79 unsigned long flags; 80 int ret; 81 82 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 83 *val = 0xffffffff; 84 return PCIBIOS_DEVICE_NOT_FOUND; 85 } 86 87 spin_lock_irqsave(&orion5x_pcie_lock, flags); 88 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 89 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 90 91 return ret; 92 } 93 94 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, 95 int where, int size, u32 *val) 96 { 97 int ret; 98 99 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 100 *val = 0xffffffff; 101 return PCIBIOS_DEVICE_NOT_FOUND; 102 } 103 104 /* 105 * We only support access to the non-extended configuration 106 * space when using the WA access method (or we would have to 107 * sacrifice 256M of CPU virtual address space.) 108 */ 109 if (where >= 0x100) { 110 *val = 0xffffffff; 111 return PCIBIOS_DEVICE_NOT_FOUND; 112 } 113 114 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, 115 bus, devfn, where, size, val); 116 117 return ret; 118 } 119 120 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 121 int where, int size, u32 val) 122 { 123 unsigned long flags; 124 int ret; 125 126 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 127 return PCIBIOS_DEVICE_NOT_FOUND; 128 129 spin_lock_irqsave(&orion5x_pcie_lock, flags); 130 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 131 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 132 133 return ret; 134 } 135 136 static struct pci_ops pcie_ops = { 137 .read = pcie_rd_conf, 138 .write = pcie_wr_conf, 139 }; 140 141 142 static int __init pcie_setup(struct pci_sys_data *sys) 143 { 144 struct resource *res; 145 int dev; 146 147 /* 148 * Generic PCIe unit setup. 149 */ 150 orion_pcie_setup(PCIE_BASE); 151 152 /* 153 * Check whether to apply Orion-1/Orion-NAS PCIe config 154 * read transaction workaround. 155 */ 156 dev = orion_pcie_dev_id(PCIE_BASE); 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 159 "read transaction workaround\n"); 160 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 161 ORION5X_PCIE_WA_SIZE); 162 pcie_ops.read = pcie_rd_conf_wa; 163 } 164 165 /* 166 * Request resources. 167 */ 168 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 169 if (!res) 170 panic("pcie_setup unable to alloc resources"); 171 172 /* 173 * IORESOURCE_IO 174 */ 175 res[0].name = "PCIe I/O Space"; 176 res[0].flags = IORESOURCE_IO; 177 res[0].start = ORION5X_PCIE_IO_BUS_BASE; 178 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; 179 if (request_resource(&ioport_resource, &res[0])) 180 panic("Request PCIe IO resource failed\n"); 181 pci_add_resource(&sys->resources, &res[0]); 182 183 /* 184 * IORESOURCE_MEM 185 */ 186 res[1].name = "PCIe Memory Space"; 187 res[1].flags = IORESOURCE_MEM; 188 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; 189 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 190 if (request_resource(&iomem_resource, &res[1])) 191 panic("Request PCIe Memory resource failed\n"); 192 pci_add_resource(&sys->resources, &res[1]); 193 194 sys->io_offset = 0; 195 196 return 1; 197 } 198 199 /***************************************************************************** 200 * PCI controller 201 ****************************************************************************/ 202 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 203 #define PCI_MODE ORION5X_PCI_REG(0xd00) 204 #define PCI_CMD ORION5X_PCI_REG(0xc00) 205 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 206 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) 207 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) 208 209 /* 210 * PCI_MODE bits 211 */ 212 #define PCI_MODE_64BIT (1 << 2) 213 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) 214 215 /* 216 * PCI_CMD bits 217 */ 218 #define PCI_CMD_HOST_REORDER (1 << 29) 219 220 /* 221 * PCI_P2P_CONF bits 222 */ 223 #define PCI_P2P_BUS_OFFS 16 224 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) 225 #define PCI_P2P_DEV_OFFS 24 226 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) 227 228 /* 229 * PCI_CONF_ADDR bits 230 */ 231 #define PCI_CONF_REG(reg) ((reg) & 0xfc) 232 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) 233 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) 234 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) 235 #define PCI_CONF_ADDR_EN (1 << 31) 236 237 /* 238 * Internal configuration space 239 */ 240 #define PCI_CONF_FUNC_STAT_CMD 0 241 #define PCI_CONF_REG_STAT_CMD 4 242 #define PCIX_STAT 0x64 243 #define PCIX_STAT_BUS_OFFS 8 244 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) 245 246 /* 247 * PCI Address Decode Windows registers 248 */ 249 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 250 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 251 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 252 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 253 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 254 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 255 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 256 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 257 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 258 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 259 260 /* 261 * PCI configuration helpers for BAR settings 262 */ 263 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) 264 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) 265 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) 266 267 /* 268 * PCI config cycles are done by programming the PCI_CONF_ADDR register 269 * and then reading the PCI_CONF_DATA register. Need to make sure these 270 * transactions are atomic. 271 */ 272 static DEFINE_SPINLOCK(orion5x_pci_lock); 273 274 static int orion5x_pci_cardbus_mode; 275 276 static int orion5x_pci_local_bus_nr(void) 277 { 278 u32 conf = readl(PCI_P2P_CONF); 279 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 280 } 281 282 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, 283 u32 where, u32 size, u32 *val) 284 { 285 unsigned long flags; 286 spin_lock_irqsave(&orion5x_pci_lock, flags); 287 288 writel(PCI_CONF_BUS(bus) | 289 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 290 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 291 292 *val = readl(PCI_CONF_DATA); 293 294 if (size == 1) 295 *val = (*val >> (8*(where & 0x3))) & 0xff; 296 else if (size == 2) 297 *val = (*val >> (8*(where & 0x3))) & 0xffff; 298 299 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 300 301 return PCIBIOS_SUCCESSFUL; 302 } 303 304 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, 305 u32 where, u32 size, u32 val) 306 { 307 unsigned long flags; 308 int ret = PCIBIOS_SUCCESSFUL; 309 310 spin_lock_irqsave(&orion5x_pci_lock, flags); 311 312 writel(PCI_CONF_BUS(bus) | 313 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 314 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 315 316 if (size == 4) { 317 __raw_writel(val, PCI_CONF_DATA); 318 } else if (size == 2) { 319 __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); 320 } else if (size == 1) { 321 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); 322 } else { 323 ret = PCIBIOS_BAD_REGISTER_NUMBER; 324 } 325 326 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 327 328 return ret; 329 } 330 331 static int orion5x_pci_valid_config(int bus, u32 devfn) 332 { 333 if (bus == orion5x_pci_local_bus_nr()) { 334 /* 335 * Don't go out for local device 336 */ 337 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) 338 return 0; 339 340 /* 341 * When the PCI signals are directly connected to a 342 * Cardbus slot, ignore all but device IDs 0 and 1. 343 */ 344 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) 345 return 0; 346 } 347 348 return 1; 349 } 350 351 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 352 int where, int size, u32 *val) 353 { 354 if (!orion5x_pci_valid_config(bus->number, devfn)) { 355 *val = 0xffffffff; 356 return PCIBIOS_DEVICE_NOT_FOUND; 357 } 358 359 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), 360 PCI_FUNC(devfn), where, size, val); 361 } 362 363 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 364 int where, int size, u32 val) 365 { 366 if (!orion5x_pci_valid_config(bus->number, devfn)) 367 return PCIBIOS_DEVICE_NOT_FOUND; 368 369 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 370 PCI_FUNC(devfn), where, size, val); 371 } 372 373 static struct pci_ops pci_ops = { 374 .read = orion5x_pci_rd_conf, 375 .write = orion5x_pci_wr_conf, 376 }; 377 378 static void __init orion5x_pci_set_bus_nr(int nr) 379 { 380 u32 p2p = readl(PCI_P2P_CONF); 381 382 if (readl(PCI_MODE) & PCI_MODE_PCIX) { 383 /* 384 * PCI-X mode 385 */ 386 u32 pcix_status, bus, dev; 387 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; 388 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; 389 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); 390 pcix_status &= ~PCIX_STAT_BUS_MASK; 391 pcix_status |= (nr << PCIX_STAT_BUS_OFFS); 392 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); 393 } else { 394 /* 395 * PCI Conventional mode 396 */ 397 p2p &= ~PCI_P2P_BUS_MASK; 398 p2p |= (nr << PCI_P2P_BUS_OFFS); 399 writel(p2p, PCI_P2P_CONF); 400 } 401 } 402 403 static void __init orion5x_pci_master_slave_enable(void) 404 { 405 int bus_nr, func, reg; 406 u32 val; 407 408 bus_nr = orion5x_pci_local_bus_nr(); 409 func = PCI_CONF_FUNC_STAT_CMD; 410 reg = PCI_CONF_REG_STAT_CMD; 411 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); 412 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 413 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 414 } 415 416 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 417 { 418 u32 win_enable; 419 int bus; 420 int i; 421 422 /* 423 * First, disable windows. 424 */ 425 win_enable = 0xffffffff; 426 writel(win_enable, PCI_BAR_ENABLE); 427 428 /* 429 * Setup windows for DDR banks. 430 */ 431 bus = orion5x_pci_local_bus_nr(); 432 433 for (i = 0; i < dram->num_cs; i++) { 434 struct mbus_dram_window *cs = dram->cs + i; 435 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 436 u32 reg; 437 u32 val; 438 439 /* 440 * Write DRAM bank base address register. 441 */ 442 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); 443 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); 444 val = (cs->base & 0xfffff000) | (val & 0xfff); 445 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); 446 447 /* 448 * Write DRAM bank size register. 449 */ 450 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 451 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 452 writel((cs->size - 1) & 0xfffff000, 453 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); 454 writel(cs->base & 0xfffff000, 455 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); 456 457 /* 458 * Enable decode window for this chip select. 459 */ 460 win_enable &= ~(1 << cs->cs_index); 461 } 462 463 /* 464 * Re-enable decode windows. 465 */ 466 writel(win_enable, PCI_BAR_ENABLE); 467 468 /* 469 * Disable automatic update of address remapping when writing to BARs. 470 */ 471 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); 472 } 473 474 static int __init pci_setup(struct pci_sys_data *sys) 475 { 476 struct resource *res; 477 478 /* 479 * Point PCI unit MBUS decode windows to DRAM space. 480 */ 481 orion5x_setup_pci_wins(&orion_mbus_dram_info); 482 483 /* 484 * Master + Slave enable 485 */ 486 orion5x_pci_master_slave_enable(); 487 488 /* 489 * Force ordering 490 */ 491 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 492 493 /* 494 * Request resources 495 */ 496 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 497 if (!res) 498 panic("pci_setup unable to alloc resources"); 499 500 /* 501 * IORESOURCE_IO 502 */ 503 res[0].name = "PCI I/O Space"; 504 res[0].flags = IORESOURCE_IO; 505 res[0].start = ORION5X_PCI_IO_BUS_BASE; 506 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; 507 if (request_resource(&ioport_resource, &res[0])) 508 panic("Request PCI IO resource failed\n"); 509 pci_add_resource(&sys->resources, &res[0]); 510 511 /* 512 * IORESOURCE_MEM 513 */ 514 res[1].name = "PCI Memory Space"; 515 res[1].flags = IORESOURCE_MEM; 516 res[1].start = ORION5X_PCI_MEM_PHYS_BASE; 517 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 518 if (request_resource(&iomem_resource, &res[1])) 519 panic("Request PCI Memory resource failed\n"); 520 pci_add_resource(&sys->resources, &res[1]); 521 522 sys->io_offset = 0; 523 524 return 1; 525 } 526 527 528 /***************************************************************************** 529 * General PCIe + PCI 530 ****************************************************************************/ 531 static void __devinit rc_pci_fixup(struct pci_dev *dev) 532 { 533 /* 534 * Prevent enumeration of root complex. 535 */ 536 if (dev->bus->parent == NULL && dev->devfn == 0) { 537 int i; 538 539 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 540 dev->resource[i].start = 0; 541 dev->resource[i].end = 0; 542 dev->resource[i].flags = 0; 543 } 544 } 545 } 546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 547 548 static int orion5x_pci_disabled __initdata; 549 550 void __init orion5x_pci_disable(void) 551 { 552 orion5x_pci_disabled = 1; 553 } 554 555 void __init orion5x_pci_set_cardbus_mode(void) 556 { 557 orion5x_pci_cardbus_mode = 1; 558 } 559 560 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 561 { 562 int ret = 0; 563 564 vga_base = ORION5X_PCIE_MEM_PHYS_BASE; 565 566 if (nr == 0) { 567 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 568 ret = pcie_setup(sys); 569 } else if (nr == 1 && !orion5x_pci_disabled) { 570 orion5x_pci_set_bus_nr(sys->busnr); 571 ret = pci_setup(sys); 572 } 573 574 return ret; 575 } 576 577 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 578 { 579 struct pci_bus *bus; 580 581 if (nr == 0) { 582 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, 583 &sys->resources); 584 } else if (nr == 1 && !orion5x_pci_disabled) { 585 bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, 586 &sys->resources); 587 } else { 588 bus = NULL; 589 BUG(); 590 } 591 592 return bus; 593 } 594 595 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 596 { 597 int bus = dev->bus->number; 598 599 /* 600 * PCIe endpoint? 601 */ 602 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) 603 return IRQ_ORION5X_PCIE0_INT; 604 605 return -1; 606 } 607